1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * wm8400 private definitions for audio 2 * wm8400 private definitions for audio
4 * 3 *
5 * Copyright 2008 Wolfson Microelectronics plc 4 * Copyright 2008 Wolfson Microelectronics plc
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify
>> 7 * it under the terms of the GNU General Public License as published by
>> 8 * the Free Software Foundation; either version 2 of the License, or
>> 9 * (at your option) any later version.
>> 10 *
>> 11 * This program is distributed in the hope that it will be useful,
>> 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 14 * GNU General Public License for more details.
>> 15 *
>> 16 * You should have received a copy of the GNU General Public License
>> 17 * along with this program; if not, write to the Free Software
>> 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
6 */ 19 */
7 20
8 #ifndef __LINUX_MFD_WM8400_AUDIO_H 21 #ifndef __LINUX_MFD_WM8400_AUDIO_H
9 #define __LINUX_MFD_WM8400_AUDIO_H 22 #define __LINUX_MFD_WM8400_AUDIO_H
10 23
11 #include <linux/mfd/wm8400-audio.h> 24 #include <linux/mfd/wm8400-audio.h>
12 25
13 /* 26 /*
14 * R2 (0x02) - Power Management (1) 27 * R2 (0x02) - Power Management (1)
15 */ 28 */
16 #define WM8400_CODEC_ENA 29 #define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */
17 #define WM8400_CODEC_ENA_MASK 30 #define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */
18 #define WM8400_CODEC_ENA_SHIFT 31 #define WM8400_CODEC_ENA_SHIFT 15 /* CODEC_ENA */
19 #define WM8400_CODEC_ENA_WIDTH 32 #define WM8400_CODEC_ENA_WIDTH 1 /* CODEC_ENA */
20 #define WM8400_SYSCLK_ENA 33 #define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */
21 #define WM8400_SYSCLK_ENA_MASK 34 #define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */
22 #define WM8400_SYSCLK_ENA_SHIFT 35 #define WM8400_SYSCLK_ENA_SHIFT 14 /* SYSCLK_ENA */
23 #define WM8400_SYSCLK_ENA_WIDTH 36 #define WM8400_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
24 #define WM8400_SPK_MIX_ENA 37 #define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */
25 #define WM8400_SPK_MIX_ENA_MASK 38 #define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */
26 #define WM8400_SPK_MIX_ENA_SHIFT 39 #define WM8400_SPK_MIX_ENA_SHIFT 13 /* SPK_MIX_ENA */
27 #define WM8400_SPK_MIX_ENA_WIDTH 40 #define WM8400_SPK_MIX_ENA_WIDTH 1 /* SPK_MIX_ENA */
28 #define WM8400_SPK_ENA 41 #define WM8400_SPK_ENA 0x1000 /* SPK_ENA */
29 #define WM8400_SPK_ENA_MASK 42 #define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */
30 #define WM8400_SPK_ENA_SHIFT 43 #define WM8400_SPK_ENA_SHIFT 12 /* SPK_ENA */
31 #define WM8400_SPK_ENA_WIDTH 44 #define WM8400_SPK_ENA_WIDTH 1 /* SPK_ENA */
32 #define WM8400_OUT3_ENA 45 #define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */
33 #define WM8400_OUT3_ENA_MASK 46 #define WM8400_OUT3_ENA_MASK 0x0800 /* OUT3_ENA */
34 #define WM8400_OUT3_ENA_SHIFT 47 #define WM8400_OUT3_ENA_SHIFT 11 /* OUT3_ENA */
35 #define WM8400_OUT3_ENA_WIDTH 48 #define WM8400_OUT3_ENA_WIDTH 1 /* OUT3_ENA */
36 #define WM8400_OUT4_ENA 49 #define WM8400_OUT4_ENA 0x0400 /* OUT4_ENA */
37 #define WM8400_OUT4_ENA_MASK 50 #define WM8400_OUT4_ENA_MASK 0x0400 /* OUT4_ENA */
38 #define WM8400_OUT4_ENA_SHIFT 51 #define WM8400_OUT4_ENA_SHIFT 10 /* OUT4_ENA */
39 #define WM8400_OUT4_ENA_WIDTH 52 #define WM8400_OUT4_ENA_WIDTH 1 /* OUT4_ENA */
40 #define WM8400_LOUT_ENA 53 #define WM8400_LOUT_ENA 0x0200 /* LOUT_ENA */
41 #define WM8400_LOUT_ENA_MASK 54 #define WM8400_LOUT_ENA_MASK 0x0200 /* LOUT_ENA */
42 #define WM8400_LOUT_ENA_SHIFT 55 #define WM8400_LOUT_ENA_SHIFT 9 /* LOUT_ENA */
43 #define WM8400_LOUT_ENA_WIDTH 56 #define WM8400_LOUT_ENA_WIDTH 1 /* LOUT_ENA */
44 #define WM8400_ROUT_ENA 57 #define WM8400_ROUT_ENA 0x0100 /* ROUT_ENA */
45 #define WM8400_ROUT_ENA_MASK 58 #define WM8400_ROUT_ENA_MASK 0x0100 /* ROUT_ENA */
46 #define WM8400_ROUT_ENA_SHIFT 59 #define WM8400_ROUT_ENA_SHIFT 8 /* ROUT_ENA */
47 #define WM8400_ROUT_ENA_WIDTH 60 #define WM8400_ROUT_ENA_WIDTH 1 /* ROUT_ENA */
48 #define WM8400_MIC1BIAS_ENA 61 #define WM8400_MIC1BIAS_ENA 0x0010 /* MIC1BIAS_ENA */
49 #define WM8400_MIC1BIAS_ENA_MASK 62 #define WM8400_MIC1BIAS_ENA_MASK 0x0010 /* MIC1BIAS_ENA */
50 #define WM8400_MIC1BIAS_ENA_SHIFT 63 #define WM8400_MIC1BIAS_ENA_SHIFT 4 /* MIC1BIAS_ENA */
51 #define WM8400_MIC1BIAS_ENA_WIDTH 64 #define WM8400_MIC1BIAS_ENA_WIDTH 1 /* MIC1BIAS_ENA */
52 #define WM8400_VMID_MODE_MASK 65 #define WM8400_VMID_MODE_MASK 0x0006 /* VMID_MODE - [2:1] */
53 #define WM8400_VMID_MODE_SHIFT 66 #define WM8400_VMID_MODE_SHIFT 1 /* VMID_MODE - [2:1] */
54 #define WM8400_VMID_MODE_WIDTH 67 #define WM8400_VMID_MODE_WIDTH 2 /* VMID_MODE - [2:1] */
55 #define WM8400_VREF_ENA 68 #define WM8400_VREF_ENA 0x0001 /* VREF_ENA */
56 #define WM8400_VREF_ENA_MASK 69 #define WM8400_VREF_ENA_MASK 0x0001 /* VREF_ENA */
57 #define WM8400_VREF_ENA_SHIFT 70 #define WM8400_VREF_ENA_SHIFT 0 /* VREF_ENA */
58 #define WM8400_VREF_ENA_WIDTH 71 #define WM8400_VREF_ENA_WIDTH 1 /* VREF_ENA */
59 72
60 /* 73 /*
61 * R3 (0x03) - Power Management (2) 74 * R3 (0x03) - Power Management (2)
62 */ 75 */
63 #define WM8400_FLL_ENA 76 #define WM8400_FLL_ENA 0x8000 /* FLL_ENA */
64 #define WM8400_FLL_ENA_MASK 77 #define WM8400_FLL_ENA_MASK 0x8000 /* FLL_ENA */
65 #define WM8400_FLL_ENA_SHIFT 78 #define WM8400_FLL_ENA_SHIFT 15 /* FLL_ENA */
66 #define WM8400_FLL_ENA_WIDTH 79 #define WM8400_FLL_ENA_WIDTH 1 /* FLL_ENA */
67 #define WM8400_TSHUT_ENA 80 #define WM8400_TSHUT_ENA 0x4000 /* TSHUT_ENA */
68 #define WM8400_TSHUT_ENA_MASK 81 #define WM8400_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
69 #define WM8400_TSHUT_ENA_SHIFT 82 #define WM8400_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */
70 #define WM8400_TSHUT_ENA_WIDTH 83 #define WM8400_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
71 #define WM8400_TSHUT_OPDIS 84 #define WM8400_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
72 #define WM8400_TSHUT_OPDIS_MASK 85 #define WM8400_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
73 #define WM8400_TSHUT_OPDIS_SHIFT 86 #define WM8400_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */
74 #define WM8400_TSHUT_OPDIS_WIDTH 87 #define WM8400_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */
75 #define WM8400_OPCLK_ENA 88 #define WM8400_OPCLK_ENA 0x0800 /* OPCLK_ENA */
76 #define WM8400_OPCLK_ENA_MASK 89 #define WM8400_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
77 #define WM8400_OPCLK_ENA_SHIFT 90 #define WM8400_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
78 #define WM8400_OPCLK_ENA_WIDTH 91 #define WM8400_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
79 #define WM8400_AINL_ENA 92 #define WM8400_AINL_ENA 0x0200 /* AINL_ENA */
80 #define WM8400_AINL_ENA_MASK 93 #define WM8400_AINL_ENA_MASK 0x0200 /* AINL_ENA */
81 #define WM8400_AINL_ENA_SHIFT 94 #define WM8400_AINL_ENA_SHIFT 9 /* AINL_ENA */
82 #define WM8400_AINL_ENA_WIDTH 95 #define WM8400_AINL_ENA_WIDTH 1 /* AINL_ENA */
83 #define WM8400_AINR_ENA 96 #define WM8400_AINR_ENA 0x0100 /* AINR_ENA */
84 #define WM8400_AINR_ENA_MASK 97 #define WM8400_AINR_ENA_MASK 0x0100 /* AINR_ENA */
85 #define WM8400_AINR_ENA_SHIFT 98 #define WM8400_AINR_ENA_SHIFT 8 /* AINR_ENA */
86 #define WM8400_AINR_ENA_WIDTH 99 #define WM8400_AINR_ENA_WIDTH 1 /* AINR_ENA */
87 #define WM8400_LIN34_ENA 100 #define WM8400_LIN34_ENA 0x0080 /* LIN34_ENA */
88 #define WM8400_LIN34_ENA_MASK 101 #define WM8400_LIN34_ENA_MASK 0x0080 /* LIN34_ENA */
89 #define WM8400_LIN34_ENA_SHIFT 102 #define WM8400_LIN34_ENA_SHIFT 7 /* LIN34_ENA */
90 #define WM8400_LIN34_ENA_WIDTH 103 #define WM8400_LIN34_ENA_WIDTH 1 /* LIN34_ENA */
91 #define WM8400_LIN12_ENA 104 #define WM8400_LIN12_ENA 0x0040 /* LIN12_ENA */
92 #define WM8400_LIN12_ENA_MASK 105 #define WM8400_LIN12_ENA_MASK 0x0040 /* LIN12_ENA */
93 #define WM8400_LIN12_ENA_SHIFT 106 #define WM8400_LIN12_ENA_SHIFT 6 /* LIN12_ENA */
94 #define WM8400_LIN12_ENA_WIDTH 107 #define WM8400_LIN12_ENA_WIDTH 1 /* LIN12_ENA */
95 #define WM8400_RIN34_ENA 108 #define WM8400_RIN34_ENA 0x0020 /* RIN34_ENA */
96 #define WM8400_RIN34_ENA_MASK 109 #define WM8400_RIN34_ENA_MASK 0x0020 /* RIN34_ENA */
97 #define WM8400_RIN34_ENA_SHIFT 110 #define WM8400_RIN34_ENA_SHIFT 5 /* RIN34_ENA */
98 #define WM8400_RIN34_ENA_WIDTH 111 #define WM8400_RIN34_ENA_WIDTH 1 /* RIN34_ENA */
99 #define WM8400_RIN12_ENA 112 #define WM8400_RIN12_ENA 0x0010 /* RIN12_ENA */
100 #define WM8400_RIN12_ENA_MASK 113 #define WM8400_RIN12_ENA_MASK 0x0010 /* RIN12_ENA */
101 #define WM8400_RIN12_ENA_SHIFT 114 #define WM8400_RIN12_ENA_SHIFT 4 /* RIN12_ENA */
102 #define WM8400_RIN12_ENA_WIDTH 115 #define WM8400_RIN12_ENA_WIDTH 1 /* RIN12_ENA */
103 #define WM8400_ADCL_ENA 116 #define WM8400_ADCL_ENA 0x0002 /* ADCL_ENA */
104 #define WM8400_ADCL_ENA_MASK 117 #define WM8400_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
105 #define WM8400_ADCL_ENA_SHIFT 118 #define WM8400_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
106 #define WM8400_ADCL_ENA_WIDTH 119 #define WM8400_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
107 #define WM8400_ADCR_ENA 120 #define WM8400_ADCR_ENA 0x0001 /* ADCR_ENA */
108 #define WM8400_ADCR_ENA_MASK 121 #define WM8400_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
109 #define WM8400_ADCR_ENA_SHIFT 122 #define WM8400_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
110 #define WM8400_ADCR_ENA_WIDTH 123 #define WM8400_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
111 124
112 /* 125 /*
113 * R4 (0x04) - Power Management (3) 126 * R4 (0x04) - Power Management (3)
114 */ 127 */
115 #define WM8400_LON_ENA 128 #define WM8400_LON_ENA 0x2000 /* LON_ENA */
116 #define WM8400_LON_ENA_MASK 129 #define WM8400_LON_ENA_MASK 0x2000 /* LON_ENA */
117 #define WM8400_LON_ENA_SHIFT 130 #define WM8400_LON_ENA_SHIFT 13 /* LON_ENA */
118 #define WM8400_LON_ENA_WIDTH 131 #define WM8400_LON_ENA_WIDTH 1 /* LON_ENA */
119 #define WM8400_LOP_ENA 132 #define WM8400_LOP_ENA 0x1000 /* LOP_ENA */
120 #define WM8400_LOP_ENA_MASK 133 #define WM8400_LOP_ENA_MASK 0x1000 /* LOP_ENA */
121 #define WM8400_LOP_ENA_SHIFT 134 #define WM8400_LOP_ENA_SHIFT 12 /* LOP_ENA */
122 #define WM8400_LOP_ENA_WIDTH 135 #define WM8400_LOP_ENA_WIDTH 1 /* LOP_ENA */
123 #define WM8400_RON_ENA 136 #define WM8400_RON_ENA 0x0800 /* RON_ENA */
124 #define WM8400_RON_ENA_MASK 137 #define WM8400_RON_ENA_MASK 0x0800 /* RON_ENA */
125 #define WM8400_RON_ENA_SHIFT 138 #define WM8400_RON_ENA_SHIFT 11 /* RON_ENA */
126 #define WM8400_RON_ENA_WIDTH 139 #define WM8400_RON_ENA_WIDTH 1 /* RON_ENA */
127 #define WM8400_ROP_ENA 140 #define WM8400_ROP_ENA 0x0400 /* ROP_ENA */
128 #define WM8400_ROP_ENA_MASK 141 #define WM8400_ROP_ENA_MASK 0x0400 /* ROP_ENA */
129 #define WM8400_ROP_ENA_SHIFT 142 #define WM8400_ROP_ENA_SHIFT 10 /* ROP_ENA */
130 #define WM8400_ROP_ENA_WIDTH 143 #define WM8400_ROP_ENA_WIDTH 1 /* ROP_ENA */
131 #define WM8400_LOPGA_ENA 144 #define WM8400_LOPGA_ENA 0x0080 /* LOPGA_ENA */
132 #define WM8400_LOPGA_ENA_MASK 145 #define WM8400_LOPGA_ENA_MASK 0x0080 /* LOPGA_ENA */
133 #define WM8400_LOPGA_ENA_SHIFT 146 #define WM8400_LOPGA_ENA_SHIFT 7 /* LOPGA_ENA */
134 #define WM8400_LOPGA_ENA_WIDTH 147 #define WM8400_LOPGA_ENA_WIDTH 1 /* LOPGA_ENA */
135 #define WM8400_ROPGA_ENA 148 #define WM8400_ROPGA_ENA 0x0040 /* ROPGA_ENA */
136 #define WM8400_ROPGA_ENA_MASK 149 #define WM8400_ROPGA_ENA_MASK 0x0040 /* ROPGA_ENA */
137 #define WM8400_ROPGA_ENA_SHIFT 150 #define WM8400_ROPGA_ENA_SHIFT 6 /* ROPGA_ENA */
138 #define WM8400_ROPGA_ENA_WIDTH 151 #define WM8400_ROPGA_ENA_WIDTH 1 /* ROPGA_ENA */
139 #define WM8400_LOMIX_ENA 152 #define WM8400_LOMIX_ENA 0x0020 /* LOMIX_ENA */
140 #define WM8400_LOMIX_ENA_MASK 153 #define WM8400_LOMIX_ENA_MASK 0x0020 /* LOMIX_ENA */
141 #define WM8400_LOMIX_ENA_SHIFT 154 #define WM8400_LOMIX_ENA_SHIFT 5 /* LOMIX_ENA */
142 #define WM8400_LOMIX_ENA_WIDTH 155 #define WM8400_LOMIX_ENA_WIDTH 1 /* LOMIX_ENA */
143 #define WM8400_ROMIX_ENA 156 #define WM8400_ROMIX_ENA 0x0010 /* ROMIX_ENA */
144 #define WM8400_ROMIX_ENA_MASK 157 #define WM8400_ROMIX_ENA_MASK 0x0010 /* ROMIX_ENA */
145 #define WM8400_ROMIX_ENA_SHIFT 158 #define WM8400_ROMIX_ENA_SHIFT 4 /* ROMIX_ENA */
146 #define WM8400_ROMIX_ENA_WIDTH 159 #define WM8400_ROMIX_ENA_WIDTH 1 /* ROMIX_ENA */
147 #define WM8400_DACL_ENA 160 #define WM8400_DACL_ENA 0x0002 /* DACL_ENA */
148 #define WM8400_DACL_ENA_MASK 161 #define WM8400_DACL_ENA_MASK 0x0002 /* DACL_ENA */
149 #define WM8400_DACL_ENA_SHIFT 162 #define WM8400_DACL_ENA_SHIFT 1 /* DACL_ENA */
150 #define WM8400_DACL_ENA_WIDTH 163 #define WM8400_DACL_ENA_WIDTH 1 /* DACL_ENA */
151 #define WM8400_DACR_ENA 164 #define WM8400_DACR_ENA 0x0001 /* DACR_ENA */
152 #define WM8400_DACR_ENA_MASK 165 #define WM8400_DACR_ENA_MASK 0x0001 /* DACR_ENA */
153 #define WM8400_DACR_ENA_SHIFT 166 #define WM8400_DACR_ENA_SHIFT 0 /* DACR_ENA */
154 #define WM8400_DACR_ENA_WIDTH 167 #define WM8400_DACR_ENA_WIDTH 1 /* DACR_ENA */
155 168
156 /* 169 /*
157 * R5 (0x05) - Audio Interface (1) 170 * R5 (0x05) - Audio Interface (1)
158 */ 171 */
159 #define WM8400_AIFADCL_SRC 172 #define WM8400_AIFADCL_SRC 0x8000 /* AIFADCL_SRC */
160 #define WM8400_AIFADCL_SRC_MASK 173 #define WM8400_AIFADCL_SRC_MASK 0x8000 /* AIFADCL_SRC */
161 #define WM8400_AIFADCL_SRC_SHIFT 174 #define WM8400_AIFADCL_SRC_SHIFT 15 /* AIFADCL_SRC */
162 #define WM8400_AIFADCL_SRC_WIDTH 175 #define WM8400_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */
163 #define WM8400_AIFADCR_SRC 176 #define WM8400_AIFADCR_SRC 0x4000 /* AIFADCR_SRC */
164 #define WM8400_AIFADCR_SRC_MASK 177 #define WM8400_AIFADCR_SRC_MASK 0x4000 /* AIFADCR_SRC */
165 #define WM8400_AIFADCR_SRC_SHIFT 178 #define WM8400_AIFADCR_SRC_SHIFT 14 /* AIFADCR_SRC */
166 #define WM8400_AIFADCR_SRC_WIDTH 179 #define WM8400_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */
167 #define WM8400_AIFADC_TDM 180 #define WM8400_AIFADC_TDM 0x2000 /* AIFADC_TDM */
168 #define WM8400_AIFADC_TDM_MASK 181 #define WM8400_AIFADC_TDM_MASK 0x2000 /* AIFADC_TDM */
169 #define WM8400_AIFADC_TDM_SHIFT 182 #define WM8400_AIFADC_TDM_SHIFT 13 /* AIFADC_TDM */
170 #define WM8400_AIFADC_TDM_WIDTH 183 #define WM8400_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */
171 #define WM8400_AIFADC_TDM_CHAN 184 #define WM8400_AIFADC_TDM_CHAN 0x1000 /* AIFADC_TDM_CHAN */
172 #define WM8400_AIFADC_TDM_CHAN_MASK 185 #define WM8400_AIFADC_TDM_CHAN_MASK 0x1000 /* AIFADC_TDM_CHAN */
173 #define WM8400_AIFADC_TDM_CHAN_SHIFT 186 #define WM8400_AIFADC_TDM_CHAN_SHIFT 12 /* AIFADC_TDM_CHAN */
174 #define WM8400_AIFADC_TDM_CHAN_WIDTH 187 #define WM8400_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */
175 #define WM8400_AIF_BCLK_INV 188 #define WM8400_AIF_BCLK_INV 0x0100 /* AIF_BCLK_INV */
176 #define WM8400_AIF_BCLK_INV_MASK 189 #define WM8400_AIF_BCLK_INV_MASK 0x0100 /* AIF_BCLK_INV */
177 #define WM8400_AIF_BCLK_INV_SHIFT 190 #define WM8400_AIF_BCLK_INV_SHIFT 8 /* AIF_BCLK_INV */
178 #define WM8400_AIF_BCLK_INV_WIDTH 191 #define WM8400_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
179 #define WM8400_AIF_LRCLK_INV 192 #define WM8400_AIF_LRCLK_INV 0x0080 /* AIF_LRCLK_INV */
180 #define WM8400_AIF_LRCLK_INV_MASK 193 #define WM8400_AIF_LRCLK_INV_MASK 0x0080 /* AIF_LRCLK_INV */
181 #define WM8400_AIF_LRCLK_INV_SHIFT 194 #define WM8400_AIF_LRCLK_INV_SHIFT 7 /* AIF_LRCLK_INV */
182 #define WM8400_AIF_LRCLK_INV_WIDTH 195 #define WM8400_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
183 #define WM8400_AIF_WL_MASK 196 #define WM8400_AIF_WL_MASK 0x0060 /* AIF_WL - [6:5] */
184 #define WM8400_AIF_WL_SHIFT 197 #define WM8400_AIF_WL_SHIFT 5 /* AIF_WL - [6:5] */
185 #define WM8400_AIF_WL_WIDTH 198 #define WM8400_AIF_WL_WIDTH 2 /* AIF_WL - [6:5] */
186 #define WM8400_AIF_WL_16BITS 199 #define WM8400_AIF_WL_16BITS (0 << 5)
187 #define WM8400_AIF_WL_20BITS 200 #define WM8400_AIF_WL_20BITS (1 << 5)
188 #define WM8400_AIF_WL_24BITS 201 #define WM8400_AIF_WL_24BITS (2 << 5)
189 #define WM8400_AIF_WL_32BITS 202 #define WM8400_AIF_WL_32BITS (3 << 5)
190 #define WM8400_AIF_FMT_MASK 203 #define WM8400_AIF_FMT_MASK 0x0018 /* AIF_FMT - [4:3] */
191 #define WM8400_AIF_FMT_SHIFT 204 #define WM8400_AIF_FMT_SHIFT 3 /* AIF_FMT - [4:3] */
192 #define WM8400_AIF_FMT_WIDTH 205 #define WM8400_AIF_FMT_WIDTH 2 /* AIF_FMT - [4:3] */
193 #define WM8400_AIF_FMT_RIGHTJ 206 #define WM8400_AIF_FMT_RIGHTJ (0 << 3)
194 #define WM8400_AIF_FMT_LEFTJ 207 #define WM8400_AIF_FMT_LEFTJ (1 << 3)
195 #define WM8400_AIF_FMT_I2S 208 #define WM8400_AIF_FMT_I2S (2 << 3)
196 #define WM8400_AIF_FMT_DSP 209 #define WM8400_AIF_FMT_DSP (3 << 3)
197 210
198 /* 211 /*
199 * R6 (0x06) - Audio Interface (2) 212 * R6 (0x06) - Audio Interface (2)
200 */ 213 */
201 #define WM8400_DACL_SRC 214 #define WM8400_DACL_SRC 0x8000 /* DACL_SRC */
202 #define WM8400_DACL_SRC_MASK 215 #define WM8400_DACL_SRC_MASK 0x8000 /* DACL_SRC */
203 #define WM8400_DACL_SRC_SHIFT 216 #define WM8400_DACL_SRC_SHIFT 15 /* DACL_SRC */
204 #define WM8400_DACL_SRC_WIDTH 217 #define WM8400_DACL_SRC_WIDTH 1 /* DACL_SRC */
205 #define WM8400_DACR_SRC 218 #define WM8400_DACR_SRC 0x4000 /* DACR_SRC */
206 #define WM8400_DACR_SRC_MASK 219 #define WM8400_DACR_SRC_MASK 0x4000 /* DACR_SRC */
207 #define WM8400_DACR_SRC_SHIFT 220 #define WM8400_DACR_SRC_SHIFT 14 /* DACR_SRC */
208 #define WM8400_DACR_SRC_WIDTH 221 #define WM8400_DACR_SRC_WIDTH 1 /* DACR_SRC */
209 #define WM8400_AIFDAC_TDM 222 #define WM8400_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */
210 #define WM8400_AIFDAC_TDM_MASK 223 #define WM8400_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */
211 #define WM8400_AIFDAC_TDM_SHIFT 224 #define WM8400_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */
212 #define WM8400_AIFDAC_TDM_WIDTH 225 #define WM8400_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */
213 #define WM8400_AIFDAC_TDM_CHAN 226 #define WM8400_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */
214 #define WM8400_AIFDAC_TDM_CHAN_MASK 227 #define WM8400_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */
215 #define WM8400_AIFDAC_TDM_CHAN_SHIFT 228 #define WM8400_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */
216 #define WM8400_AIFDAC_TDM_CHAN_WIDTH 229 #define WM8400_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */
217 #define WM8400_DAC_BOOST_MASK 230 #define WM8400_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */
218 #define WM8400_DAC_BOOST_SHIFT 231 #define WM8400_DAC_BOOST_SHIFT 10 /* DAC_BOOST - [11:10] */
219 #define WM8400_DAC_BOOST_WIDTH 232 #define WM8400_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [11:10] */
220 #define WM8400_DAC_COMP 233 #define WM8400_DAC_COMP 0x0010 /* DAC_COMP */
221 #define WM8400_DAC_COMP_MASK 234 #define WM8400_DAC_COMP_MASK 0x0010 /* DAC_COMP */
222 #define WM8400_DAC_COMP_SHIFT 235 #define WM8400_DAC_COMP_SHIFT 4 /* DAC_COMP */
223 #define WM8400_DAC_COMP_WIDTH 236 #define WM8400_DAC_COMP_WIDTH 1 /* DAC_COMP */
224 #define WM8400_DAC_COMPMODE 237 #define WM8400_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */
225 #define WM8400_DAC_COMPMODE_MASK 238 #define WM8400_DAC_COMPMODE_MASK 0x0008 /* DAC_COMPMODE */
226 #define WM8400_DAC_COMPMODE_SHIFT 239 #define WM8400_DAC_COMPMODE_SHIFT 3 /* DAC_COMPMODE */
227 #define WM8400_DAC_COMPMODE_WIDTH 240 #define WM8400_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
228 #define WM8400_ADC_COMP 241 #define WM8400_ADC_COMP 0x0004 /* ADC_COMP */
229 #define WM8400_ADC_COMP_MASK 242 #define WM8400_ADC_COMP_MASK 0x0004 /* ADC_COMP */
230 #define WM8400_ADC_COMP_SHIFT 243 #define WM8400_ADC_COMP_SHIFT 2 /* ADC_COMP */
231 #define WM8400_ADC_COMP_WIDTH 244 #define WM8400_ADC_COMP_WIDTH 1 /* ADC_COMP */
232 #define WM8400_ADC_COMPMODE 245 #define WM8400_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */
233 #define WM8400_ADC_COMPMODE_MASK 246 #define WM8400_ADC_COMPMODE_MASK 0x0002 /* ADC_COMPMODE */
234 #define WM8400_ADC_COMPMODE_SHIFT 247 #define WM8400_ADC_COMPMODE_SHIFT 1 /* ADC_COMPMODE */
235 #define WM8400_ADC_COMPMODE_WIDTH 248 #define WM8400_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */
236 #define WM8400_LOOPBACK 249 #define WM8400_LOOPBACK 0x0001 /* LOOPBACK */
237 #define WM8400_LOOPBACK_MASK 250 #define WM8400_LOOPBACK_MASK 0x0001 /* LOOPBACK */
238 #define WM8400_LOOPBACK_SHIFT 251 #define WM8400_LOOPBACK_SHIFT 0 /* LOOPBACK */
239 #define WM8400_LOOPBACK_WIDTH 252 #define WM8400_LOOPBACK_WIDTH 1 /* LOOPBACK */
240 253
241 /* 254 /*
242 * R7 (0x07) - Clocking (1) 255 * R7 (0x07) - Clocking (1)
243 */ 256 */
244 #define WM8400_TOCLK_RATE 257 #define WM8400_TOCLK_RATE 0x8000 /* TOCLK_RATE */
245 #define WM8400_TOCLK_RATE_MASK 258 #define WM8400_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */
246 #define WM8400_TOCLK_RATE_SHIFT 259 #define WM8400_TOCLK_RATE_SHIFT 15 /* TOCLK_RATE */
247 #define WM8400_TOCLK_RATE_WIDTH 260 #define WM8400_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */
248 #define WM8400_TOCLK_ENA 261 #define WM8400_TOCLK_ENA 0x4000 /* TOCLK_ENA */
249 #define WM8400_TOCLK_ENA_MASK 262 #define WM8400_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */
250 #define WM8400_TOCLK_ENA_SHIFT 263 #define WM8400_TOCLK_ENA_SHIFT 14 /* TOCLK_ENA */
251 #define WM8400_TOCLK_ENA_WIDTH 264 #define WM8400_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
252 #define WM8400_OPCLKDIV_MASK 265 #define WM8400_OPCLKDIV_MASK 0x1E00 /* OPCLKDIV - [12:9] */
253 #define WM8400_OPCLKDIV_SHIFT 266 #define WM8400_OPCLKDIV_SHIFT 9 /* OPCLKDIV - [12:9] */
254 #define WM8400_OPCLKDIV_WIDTH 267 #define WM8400_OPCLKDIV_WIDTH 4 /* OPCLKDIV - [12:9] */
255 #define WM8400_DCLKDIV_MASK 268 #define WM8400_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */
256 #define WM8400_DCLKDIV_SHIFT 269 #define WM8400_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */
257 #define WM8400_DCLKDIV_WIDTH 270 #define WM8400_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */
258 #define WM8400_BCLK_DIV_MASK 271 #define WM8400_BCLK_DIV_MASK 0x001E /* BCLK_DIV - [4:1] */
259 #define WM8400_BCLK_DIV_SHIFT 272 #define WM8400_BCLK_DIV_SHIFT 1 /* BCLK_DIV - [4:1] */
260 #define WM8400_BCLK_DIV_WIDTH 273 #define WM8400_BCLK_DIV_WIDTH 4 /* BCLK_DIV - [4:1] */
261 274
262 /* 275 /*
263 * R8 (0x08) - Clocking (2) 276 * R8 (0x08) - Clocking (2)
264 */ 277 */
265 #define WM8400_MCLK_SRC 278 #define WM8400_MCLK_SRC 0x8000 /* MCLK_SRC */
266 #define WM8400_MCLK_SRC_MASK 279 #define WM8400_MCLK_SRC_MASK 0x8000 /* MCLK_SRC */
267 #define WM8400_MCLK_SRC_SHIFT 280 #define WM8400_MCLK_SRC_SHIFT 15 /* MCLK_SRC */
268 #define WM8400_MCLK_SRC_WIDTH 281 #define WM8400_MCLK_SRC_WIDTH 1 /* MCLK_SRC */
269 #define WM8400_SYSCLK_SRC 282 #define WM8400_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */
270 #define WM8400_SYSCLK_SRC_MASK 283 #define WM8400_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */
271 #define WM8400_SYSCLK_SRC_SHIFT 284 #define WM8400_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */
272 #define WM8400_SYSCLK_SRC_WIDTH 285 #define WM8400_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
273 #define WM8400_CLK_FORCE 286 #define WM8400_CLK_FORCE 0x2000 /* CLK_FORCE */
274 #define WM8400_CLK_FORCE_MASK 287 #define WM8400_CLK_FORCE_MASK 0x2000 /* CLK_FORCE */
275 #define WM8400_CLK_FORCE_SHIFT 288 #define WM8400_CLK_FORCE_SHIFT 13 /* CLK_FORCE */
276 #define WM8400_CLK_FORCE_WIDTH 289 #define WM8400_CLK_FORCE_WIDTH 1 /* CLK_FORCE */
277 #define WM8400_MCLK_DIV_MASK 290 #define WM8400_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */
278 #define WM8400_MCLK_DIV_SHIFT 291 #define WM8400_MCLK_DIV_SHIFT 11 /* MCLK_DIV - [12:11] */
279 #define WM8400_MCLK_DIV_WIDTH 292 #define WM8400_MCLK_DIV_WIDTH 2 /* MCLK_DIV - [12:11] */
280 #define WM8400_MCLK_INV 293 #define WM8400_MCLK_INV 0x0400 /* MCLK_INV */
281 #define WM8400_MCLK_INV_MASK 294 #define WM8400_MCLK_INV_MASK 0x0400 /* MCLK_INV */
282 #define WM8400_MCLK_INV_SHIFT 295 #define WM8400_MCLK_INV_SHIFT 10 /* MCLK_INV */
283 #define WM8400_MCLK_INV_WIDTH 296 #define WM8400_MCLK_INV_WIDTH 1 /* MCLK_INV */
284 #define WM8400_ADC_CLKDIV_MASK 297 #define WM8400_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */
285 #define WM8400_ADC_CLKDIV_SHIFT 298 #define WM8400_ADC_CLKDIV_SHIFT 5 /* ADC_CLKDIV - [7:5] */
286 #define WM8400_ADC_CLKDIV_WIDTH 299 #define WM8400_ADC_CLKDIV_WIDTH 3 /* ADC_CLKDIV - [7:5] */
287 #define WM8400_DAC_CLKDIV_MASK 300 #define WM8400_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */
288 #define WM8400_DAC_CLKDIV_SHIFT 301 #define WM8400_DAC_CLKDIV_SHIFT 2 /* DAC_CLKDIV - [4:2] */
289 #define WM8400_DAC_CLKDIV_WIDTH 302 #define WM8400_DAC_CLKDIV_WIDTH 3 /* DAC_CLKDIV - [4:2] */
290 303
291 /* 304 /*
292 * R9 (0x09) - Audio Interface (3) 305 * R9 (0x09) - Audio Interface (3)
293 */ 306 */
294 #define WM8400_AIF_MSTR1 307 #define WM8400_AIF_MSTR1 0x8000 /* AIF_MSTR1 */
295 #define WM8400_AIF_MSTR1_MASK 308 #define WM8400_AIF_MSTR1_MASK 0x8000 /* AIF_MSTR1 */
296 #define WM8400_AIF_MSTR1_SHIFT 309 #define WM8400_AIF_MSTR1_SHIFT 15 /* AIF_MSTR1 */
297 #define WM8400_AIF_MSTR1_WIDTH 310 #define WM8400_AIF_MSTR1_WIDTH 1 /* AIF_MSTR1 */
298 #define WM8400_AIF_MSTR2 311 #define WM8400_AIF_MSTR2 0x4000 /* AIF_MSTR2 */
299 #define WM8400_AIF_MSTR2_MASK 312 #define WM8400_AIF_MSTR2_MASK 0x4000 /* AIF_MSTR2 */
300 #define WM8400_AIF_MSTR2_SHIFT 313 #define WM8400_AIF_MSTR2_SHIFT 14 /* AIF_MSTR2 */
301 #define WM8400_AIF_MSTR2_WIDTH 314 #define WM8400_AIF_MSTR2_WIDTH 1 /* AIF_MSTR2 */
302 #define WM8400_AIF_SEL 315 #define WM8400_AIF_SEL 0x2000 /* AIF_SEL */
303 #define WM8400_AIF_SEL_MASK 316 #define WM8400_AIF_SEL_MASK 0x2000 /* AIF_SEL */
304 #define WM8400_AIF_SEL_SHIFT 317 #define WM8400_AIF_SEL_SHIFT 13 /* AIF_SEL */
305 #define WM8400_AIF_SEL_WIDTH 318 #define WM8400_AIF_SEL_WIDTH 1 /* AIF_SEL */
306 #define WM8400_ADCLRC_DIR 319 #define WM8400_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */
307 #define WM8400_ADCLRC_DIR_MASK 320 #define WM8400_ADCLRC_DIR_MASK 0x0800 /* ADCLRC_DIR */
308 #define WM8400_ADCLRC_DIR_SHIFT 321 #define WM8400_ADCLRC_DIR_SHIFT 11 /* ADCLRC_DIR */
309 #define WM8400_ADCLRC_DIR_WIDTH 322 #define WM8400_ADCLRC_DIR_WIDTH 1 /* ADCLRC_DIR */
310 #define WM8400_ADCLRC_RATE_MASK 323 #define WM8400_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */
311 #define WM8400_ADCLRC_RATE_SHIFT 324 #define WM8400_ADCLRC_RATE_SHIFT 0 /* ADCLRC_RATE - [10:0] */
312 #define WM8400_ADCLRC_RATE_WIDTH 325 #define WM8400_ADCLRC_RATE_WIDTH 11 /* ADCLRC_RATE - [10:0] */
313 326
314 /* 327 /*
315 * R10 (0x0A) - Audio Interface (4) 328 * R10 (0x0A) - Audio Interface (4)
316 */ 329 */
317 #define WM8400_ALRCGPIO1 330 #define WM8400_ALRCGPIO1 0x8000 /* ALRCGPIO1 */
318 #define WM8400_ALRCGPIO1_MASK 331 #define WM8400_ALRCGPIO1_MASK 0x8000 /* ALRCGPIO1 */
319 #define WM8400_ALRCGPIO1_SHIFT 332 #define WM8400_ALRCGPIO1_SHIFT 15 /* ALRCGPIO1 */
320 #define WM8400_ALRCGPIO1_WIDTH 333 #define WM8400_ALRCGPIO1_WIDTH 1 /* ALRCGPIO1 */
321 #define WM8400_ALRCBGPIO6 334 #define WM8400_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */
322 #define WM8400_ALRCBGPIO6_MASK 335 #define WM8400_ALRCBGPIO6_MASK 0x4000 /* ALRCBGPIO6 */
323 #define WM8400_ALRCBGPIO6_SHIFT 336 #define WM8400_ALRCBGPIO6_SHIFT 14 /* ALRCBGPIO6 */
324 #define WM8400_ALRCBGPIO6_WIDTH 337 #define WM8400_ALRCBGPIO6_WIDTH 1 /* ALRCBGPIO6 */
325 #define WM8400_AIF_TRIS 338 #define WM8400_AIF_TRIS 0x2000 /* AIF_TRIS */
326 #define WM8400_AIF_TRIS_MASK 339 #define WM8400_AIF_TRIS_MASK 0x2000 /* AIF_TRIS */
327 #define WM8400_AIF_TRIS_SHIFT 340 #define WM8400_AIF_TRIS_SHIFT 13 /* AIF_TRIS */
328 #define WM8400_AIF_TRIS_WIDTH 341 #define WM8400_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
329 #define WM8400_DACLRC_DIR 342 #define WM8400_DACLRC_DIR 0x0800 /* DACLRC_DIR */
330 #define WM8400_DACLRC_DIR_MASK 343 #define WM8400_DACLRC_DIR_MASK 0x0800 /* DACLRC_DIR */
331 #define WM8400_DACLRC_DIR_SHIFT 344 #define WM8400_DACLRC_DIR_SHIFT 11 /* DACLRC_DIR */
332 #define WM8400_DACLRC_DIR_WIDTH 345 #define WM8400_DACLRC_DIR_WIDTH 1 /* DACLRC_DIR */
333 #define WM8400_DACLRC_RATE_MASK 346 #define WM8400_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */
334 #define WM8400_DACLRC_RATE_SHIFT 347 #define WM8400_DACLRC_RATE_SHIFT 0 /* DACLRC_RATE - [10:0] */
335 #define WM8400_DACLRC_RATE_WIDTH 348 #define WM8400_DACLRC_RATE_WIDTH 11 /* DACLRC_RATE - [10:0] */
336 349
337 /* 350 /*
338 * R11 (0x0B) - DAC CTRL 351 * R11 (0x0B) - DAC CTRL
339 */ 352 */
340 #define WM8400_DAC_SDMCLK_RATE 353 #define WM8400_DAC_SDMCLK_RATE 0x2000 /* DAC_SDMCLK_RATE */
341 #define WM8400_DAC_SDMCLK_RATE_MASK 354 #define WM8400_DAC_SDMCLK_RATE_MASK 0x2000 /* DAC_SDMCLK_RATE */
342 #define WM8400_DAC_SDMCLK_RATE_SHIFT 355 #define WM8400_DAC_SDMCLK_RATE_SHIFT 13 /* DAC_SDMCLK_RATE */
343 #define WM8400_DAC_SDMCLK_RATE_WIDTH 356 #define WM8400_DAC_SDMCLK_RATE_WIDTH 1 /* DAC_SDMCLK_RATE */
344 #define WM8400_AIF_LRCLKRATE 357 #define WM8400_AIF_LRCLKRATE 0x0400 /* AIF_LRCLKRATE */
345 #define WM8400_AIF_LRCLKRATE_MASK 358 #define WM8400_AIF_LRCLKRATE_MASK 0x0400 /* AIF_LRCLKRATE */
346 #define WM8400_AIF_LRCLKRATE_SHIFT 359 #define WM8400_AIF_LRCLKRATE_SHIFT 10 /* AIF_LRCLKRATE */
347 #define WM8400_AIF_LRCLKRATE_WIDTH 360 #define WM8400_AIF_LRCLKRATE_WIDTH 1 /* AIF_LRCLKRATE */
348 #define WM8400_DAC_MONO 361 #define WM8400_DAC_MONO 0x0200 /* DAC_MONO */
349 #define WM8400_DAC_MONO_MASK 362 #define WM8400_DAC_MONO_MASK 0x0200 /* DAC_MONO */
350 #define WM8400_DAC_MONO_SHIFT 363 #define WM8400_DAC_MONO_SHIFT 9 /* DAC_MONO */
351 #define WM8400_DAC_MONO_WIDTH 364 #define WM8400_DAC_MONO_WIDTH 1 /* DAC_MONO */
352 #define WM8400_DAC_SB_FILT 365 #define WM8400_DAC_SB_FILT 0x0100 /* DAC_SB_FILT */
353 #define WM8400_DAC_SB_FILT_MASK 366 #define WM8400_DAC_SB_FILT_MASK 0x0100 /* DAC_SB_FILT */
354 #define WM8400_DAC_SB_FILT_SHIFT 367 #define WM8400_DAC_SB_FILT_SHIFT 8 /* DAC_SB_FILT */
355 #define WM8400_DAC_SB_FILT_WIDTH 368 #define WM8400_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */
356 #define WM8400_DAC_MUTERATE 369 #define WM8400_DAC_MUTERATE 0x0080 /* DAC_MUTERATE */
357 #define WM8400_DAC_MUTERATE_MASK 370 #define WM8400_DAC_MUTERATE_MASK 0x0080 /* DAC_MUTERATE */
358 #define WM8400_DAC_MUTERATE_SHIFT 371 #define WM8400_DAC_MUTERATE_SHIFT 7 /* DAC_MUTERATE */
359 #define WM8400_DAC_MUTERATE_WIDTH 372 #define WM8400_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
360 #define WM8400_DAC_MUTEMODE 373 #define WM8400_DAC_MUTEMODE 0x0040 /* DAC_MUTEMODE */
361 #define WM8400_DAC_MUTEMODE_MASK 374 #define WM8400_DAC_MUTEMODE_MASK 0x0040 /* DAC_MUTEMODE */
362 #define WM8400_DAC_MUTEMODE_SHIFT 375 #define WM8400_DAC_MUTEMODE_SHIFT 6 /* DAC_MUTEMODE */
363 #define WM8400_DAC_MUTEMODE_WIDTH 376 #define WM8400_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
364 #define WM8400_DEEMP_MASK 377 #define WM8400_DEEMP_MASK 0x0030 /* DEEMP - [5:4] */
365 #define WM8400_DEEMP_SHIFT 378 #define WM8400_DEEMP_SHIFT 4 /* DEEMP - [5:4] */
366 #define WM8400_DEEMP_WIDTH 379 #define WM8400_DEEMP_WIDTH 2 /* DEEMP - [5:4] */
367 #define WM8400_DAC_MUTE 380 #define WM8400_DAC_MUTE 0x0004 /* DAC_MUTE */
368 #define WM8400_DAC_MUTE_MASK 381 #define WM8400_DAC_MUTE_MASK 0x0004 /* DAC_MUTE */
369 #define WM8400_DAC_MUTE_SHIFT 382 #define WM8400_DAC_MUTE_SHIFT 2 /* DAC_MUTE */
370 #define WM8400_DAC_MUTE_WIDTH 383 #define WM8400_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
371 #define WM8400_DACL_DATINV 384 #define WM8400_DACL_DATINV 0x0002 /* DACL_DATINV */
372 #define WM8400_DACL_DATINV_MASK 385 #define WM8400_DACL_DATINV_MASK 0x0002 /* DACL_DATINV */
373 #define WM8400_DACL_DATINV_SHIFT 386 #define WM8400_DACL_DATINV_SHIFT 1 /* DACL_DATINV */
374 #define WM8400_DACL_DATINV_WIDTH 387 #define WM8400_DACL_DATINV_WIDTH 1 /* DACL_DATINV */
375 #define WM8400_DACR_DATINV 388 #define WM8400_DACR_DATINV 0x0001 /* DACR_DATINV */
376 #define WM8400_DACR_DATINV_MASK 389 #define WM8400_DACR_DATINV_MASK 0x0001 /* DACR_DATINV */
377 #define WM8400_DACR_DATINV_SHIFT 390 #define WM8400_DACR_DATINV_SHIFT 0 /* DACR_DATINV */
378 #define WM8400_DACR_DATINV_WIDTH 391 #define WM8400_DACR_DATINV_WIDTH 1 /* DACR_DATINV */
379 392
380 /* 393 /*
381 * R12 (0x0C) - Left DAC Digital Volume 394 * R12 (0x0C) - Left DAC Digital Volume
382 */ 395 */
383 #define WM8400_DAC_VU 396 #define WM8400_DAC_VU 0x0100 /* DAC_VU */
384 #define WM8400_DAC_VU_MASK 397 #define WM8400_DAC_VU_MASK 0x0100 /* DAC_VU */
385 #define WM8400_DAC_VU_SHIFT 398 #define WM8400_DAC_VU_SHIFT 8 /* DAC_VU */
386 #define WM8400_DAC_VU_WIDTH 399 #define WM8400_DAC_VU_WIDTH 1 /* DAC_VU */
387 #define WM8400_DACL_VOL_MASK 400 #define WM8400_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
388 #define WM8400_DACL_VOL_SHIFT 401 #define WM8400_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */
389 #define WM8400_DACL_VOL_WIDTH 402 #define WM8400_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */
390 403
391 /* 404 /*
392 * R13 (0x0D) - Right DAC Digital Volume 405 * R13 (0x0D) - Right DAC Digital Volume
393 */ 406 */
394 #define WM8400_DAC_VU 407 #define WM8400_DAC_VU 0x0100 /* DAC_VU */
395 #define WM8400_DAC_VU_MASK 408 #define WM8400_DAC_VU_MASK 0x0100 /* DAC_VU */
396 #define WM8400_DAC_VU_SHIFT 409 #define WM8400_DAC_VU_SHIFT 8 /* DAC_VU */
397 #define WM8400_DAC_VU_WIDTH 410 #define WM8400_DAC_VU_WIDTH 1 /* DAC_VU */
398 #define WM8400_DACR_VOL_MASK 411 #define WM8400_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
399 #define WM8400_DACR_VOL_SHIFT 412 #define WM8400_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */
400 #define WM8400_DACR_VOL_WIDTH 413 #define WM8400_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */
401 414
402 /* 415 /*
403 * R14 (0x0E) - Digital Side Tone 416 * R14 (0x0E) - Digital Side Tone
404 */ 417 */
405 #define WM8400_ADCL_DAC_SVOL_MASK 418 #define WM8400_ADCL_DAC_SVOL_MASK 0x1E00 /* ADCL_DAC_SVOL - [12:9] */
406 #define WM8400_ADCL_DAC_SVOL_SHIFT 419 #define WM8400_ADCL_DAC_SVOL_SHIFT 9 /* ADCL_DAC_SVOL - [12:9] */
407 #define WM8400_ADCL_DAC_SVOL_WIDTH 420 #define WM8400_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [12:9] */
408 #define WM8400_ADCR_DAC_SVOL_MASK 421 #define WM8400_ADCR_DAC_SVOL_MASK 0x01E0 /* ADCR_DAC_SVOL - [8:5] */
409 #define WM8400_ADCR_DAC_SVOL_SHIFT 422 #define WM8400_ADCR_DAC_SVOL_SHIFT 5 /* ADCR_DAC_SVOL - [8:5] */
410 #define WM8400_ADCR_DAC_SVOL_WIDTH 423 #define WM8400_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [8:5] */
411 #define WM8400_ADC_TO_DACL_MASK 424 #define WM8400_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */
412 #define WM8400_ADC_TO_DACL_SHIFT 425 #define WM8400_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */
413 #define WM8400_ADC_TO_DACL_WIDTH 426 #define WM8400_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */
414 #define WM8400_ADC_TO_DACR_MASK 427 #define WM8400_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */
415 #define WM8400_ADC_TO_DACR_SHIFT 428 #define WM8400_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */
416 #define WM8400_ADC_TO_DACR_WIDTH 429 #define WM8400_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */
417 430
418 /* 431 /*
419 * R15 (0x0F) - ADC CTRL 432 * R15 (0x0F) - ADC CTRL
420 */ 433 */
421 #define WM8400_ADC_HPF_ENA 434 #define WM8400_ADC_HPF_ENA 0x0100 /* ADC_HPF_ENA */
422 #define WM8400_ADC_HPF_ENA_MASK 435 #define WM8400_ADC_HPF_ENA_MASK 0x0100 /* ADC_HPF_ENA */
423 #define WM8400_ADC_HPF_ENA_SHIFT 436 #define WM8400_ADC_HPF_ENA_SHIFT 8 /* ADC_HPF_ENA */
424 #define WM8400_ADC_HPF_ENA_WIDTH 437 #define WM8400_ADC_HPF_ENA_WIDTH 1 /* ADC_HPF_ENA */
425 #define WM8400_ADC_HPF_CUT_MASK 438 #define WM8400_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */
426 #define WM8400_ADC_HPF_CUT_SHIFT 439 #define WM8400_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */
427 #define WM8400_ADC_HPF_CUT_WIDTH 440 #define WM8400_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */
428 #define WM8400_ADCL_DATINV 441 #define WM8400_ADCL_DATINV 0x0002 /* ADCL_DATINV */
429 #define WM8400_ADCL_DATINV_MASK 442 #define WM8400_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */
430 #define WM8400_ADCL_DATINV_SHIFT 443 #define WM8400_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */
431 #define WM8400_ADCL_DATINV_WIDTH 444 #define WM8400_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */
432 #define WM8400_ADCR_DATINV 445 #define WM8400_ADCR_DATINV 0x0001 /* ADCR_DATINV */
433 #define WM8400_ADCR_DATINV_MASK 446 #define WM8400_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */
434 #define WM8400_ADCR_DATINV_SHIFT 447 #define WM8400_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */
435 #define WM8400_ADCR_DATINV_WIDTH 448 #define WM8400_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */
436 449
437 /* 450 /*
438 * R16 (0x10) - Left ADC Digital Volume 451 * R16 (0x10) - Left ADC Digital Volume
439 */ 452 */
440 #define WM8400_ADC_VU 453 #define WM8400_ADC_VU 0x0100 /* ADC_VU */
441 #define WM8400_ADC_VU_MASK 454 #define WM8400_ADC_VU_MASK 0x0100 /* ADC_VU */
442 #define WM8400_ADC_VU_SHIFT 455 #define WM8400_ADC_VU_SHIFT 8 /* ADC_VU */
443 #define WM8400_ADC_VU_WIDTH 456 #define WM8400_ADC_VU_WIDTH 1 /* ADC_VU */
444 #define WM8400_ADCL_VOL_MASK 457 #define WM8400_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
445 #define WM8400_ADCL_VOL_SHIFT 458 #define WM8400_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */
446 #define WM8400_ADCL_VOL_WIDTH 459 #define WM8400_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */
447 460
448 /* 461 /*
449 * R17 (0x11) - Right ADC Digital Volume 462 * R17 (0x11) - Right ADC Digital Volume
450 */ 463 */
451 #define WM8400_ADC_VU 464 #define WM8400_ADC_VU 0x0100 /* ADC_VU */
452 #define WM8400_ADC_VU_MASK 465 #define WM8400_ADC_VU_MASK 0x0100 /* ADC_VU */
453 #define WM8400_ADC_VU_SHIFT 466 #define WM8400_ADC_VU_SHIFT 8 /* ADC_VU */
454 #define WM8400_ADC_VU_WIDTH 467 #define WM8400_ADC_VU_WIDTH 1 /* ADC_VU */
455 #define WM8400_ADCR_VOL_MASK 468 #define WM8400_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
456 #define WM8400_ADCR_VOL_SHIFT 469 #define WM8400_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */
457 #define WM8400_ADCR_VOL_WIDTH 470 #define WM8400_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */
458 471
459 /* 472 /*
460 * R24 (0x18) - Left Line Input 1&2 Volume 473 * R24 (0x18) - Left Line Input 1&2 Volume
461 */ 474 */
462 #define WM8400_IPVU 475 #define WM8400_IPVU 0x0100 /* IPVU */
463 #define WM8400_IPVU_MASK 476 #define WM8400_IPVU_MASK 0x0100 /* IPVU */
464 #define WM8400_IPVU_SHIFT 477 #define WM8400_IPVU_SHIFT 8 /* IPVU */
465 #define WM8400_IPVU_WIDTH 478 #define WM8400_IPVU_WIDTH 1 /* IPVU */
466 #define WM8400_LI12MUTE 479 #define WM8400_LI12MUTE 0x0080 /* LI12MUTE */
467 #define WM8400_LI12MUTE_MASK 480 #define WM8400_LI12MUTE_MASK 0x0080 /* LI12MUTE */
468 #define WM8400_LI12MUTE_SHIFT 481 #define WM8400_LI12MUTE_SHIFT 7 /* LI12MUTE */
469 #define WM8400_LI12MUTE_WIDTH 482 #define WM8400_LI12MUTE_WIDTH 1 /* LI12MUTE */
470 #define WM8400_LI12ZC 483 #define WM8400_LI12ZC 0x0040 /* LI12ZC */
471 #define WM8400_LI12ZC_MASK 484 #define WM8400_LI12ZC_MASK 0x0040 /* LI12ZC */
472 #define WM8400_LI12ZC_SHIFT 485 #define WM8400_LI12ZC_SHIFT 6 /* LI12ZC */
473 #define WM8400_LI12ZC_WIDTH 486 #define WM8400_LI12ZC_WIDTH 1 /* LI12ZC */
474 #define WM8400_LIN12VOL_MASK 487 #define WM8400_LIN12VOL_MASK 0x001F /* LIN12VOL - [4:0] */
475 #define WM8400_LIN12VOL_SHIFT 488 #define WM8400_LIN12VOL_SHIFT 0 /* LIN12VOL - [4:0] */
476 #define WM8400_LIN12VOL_WIDTH 489 #define WM8400_LIN12VOL_WIDTH 5 /* LIN12VOL - [4:0] */
477 490
478 /* 491 /*
479 * R25 (0x19) - Left Line Input 3&4 Volume 492 * R25 (0x19) - Left Line Input 3&4 Volume
480 */ 493 */
481 #define WM8400_IPVU 494 #define WM8400_IPVU 0x0100 /* IPVU */
482 #define WM8400_IPVU_MASK 495 #define WM8400_IPVU_MASK 0x0100 /* IPVU */
483 #define WM8400_IPVU_SHIFT 496 #define WM8400_IPVU_SHIFT 8 /* IPVU */
484 #define WM8400_IPVU_WIDTH 497 #define WM8400_IPVU_WIDTH 1 /* IPVU */
485 #define WM8400_LI34MUTE 498 #define WM8400_LI34MUTE 0x0080 /* LI34MUTE */
486 #define WM8400_LI34MUTE_MASK 499 #define WM8400_LI34MUTE_MASK 0x0080 /* LI34MUTE */
487 #define WM8400_LI34MUTE_SHIFT 500 #define WM8400_LI34MUTE_SHIFT 7 /* LI34MUTE */
488 #define WM8400_LI34MUTE_WIDTH 501 #define WM8400_LI34MUTE_WIDTH 1 /* LI34MUTE */
489 #define WM8400_LI34ZC 502 #define WM8400_LI34ZC 0x0040 /* LI34ZC */
490 #define WM8400_LI34ZC_MASK 503 #define WM8400_LI34ZC_MASK 0x0040 /* LI34ZC */
491 #define WM8400_LI34ZC_SHIFT 504 #define WM8400_LI34ZC_SHIFT 6 /* LI34ZC */
492 #define WM8400_LI34ZC_WIDTH 505 #define WM8400_LI34ZC_WIDTH 1 /* LI34ZC */
493 #define WM8400_LIN34VOL_MASK 506 #define WM8400_LIN34VOL_MASK 0x001F /* LIN34VOL - [4:0] */
494 #define WM8400_LIN34VOL_SHIFT 507 #define WM8400_LIN34VOL_SHIFT 0 /* LIN34VOL - [4:0] */
495 #define WM8400_LIN34VOL_WIDTH 508 #define WM8400_LIN34VOL_WIDTH 5 /* LIN34VOL - [4:0] */
496 509
497 /* 510 /*
498 * R26 (0x1A) - Right Line Input 1&2 Volume 511 * R26 (0x1A) - Right Line Input 1&2 Volume
499 */ 512 */
500 #define WM8400_IPVU 513 #define WM8400_IPVU 0x0100 /* IPVU */
501 #define WM8400_IPVU_MASK 514 #define WM8400_IPVU_MASK 0x0100 /* IPVU */
502 #define WM8400_IPVU_SHIFT 515 #define WM8400_IPVU_SHIFT 8 /* IPVU */
503 #define WM8400_IPVU_WIDTH 516 #define WM8400_IPVU_WIDTH 1 /* IPVU */
504 #define WM8400_RI12MUTE 517 #define WM8400_RI12MUTE 0x0080 /* RI12MUTE */
505 #define WM8400_RI12MUTE_MASK 518 #define WM8400_RI12MUTE_MASK 0x0080 /* RI12MUTE */
506 #define WM8400_RI12MUTE_SHIFT 519 #define WM8400_RI12MUTE_SHIFT 7 /* RI12MUTE */
507 #define WM8400_RI12MUTE_WIDTH 520 #define WM8400_RI12MUTE_WIDTH 1 /* RI12MUTE */
508 #define WM8400_RI12ZC 521 #define WM8400_RI12ZC 0x0040 /* RI12ZC */
509 #define WM8400_RI12ZC_MASK 522 #define WM8400_RI12ZC_MASK 0x0040 /* RI12ZC */
510 #define WM8400_RI12ZC_SHIFT 523 #define WM8400_RI12ZC_SHIFT 6 /* RI12ZC */
511 #define WM8400_RI12ZC_WIDTH 524 #define WM8400_RI12ZC_WIDTH 1 /* RI12ZC */
512 #define WM8400_RIN12VOL_MASK 525 #define WM8400_RIN12VOL_MASK 0x001F /* RIN12VOL - [4:0] */
513 #define WM8400_RIN12VOL_SHIFT 526 #define WM8400_RIN12VOL_SHIFT 0 /* RIN12VOL - [4:0] */
514 #define WM8400_RIN12VOL_WIDTH 527 #define WM8400_RIN12VOL_WIDTH 5 /* RIN12VOL - [4:0] */
515 528
516 /* 529 /*
517 * R27 (0x1B) - Right Line Input 3&4 Volume 530 * R27 (0x1B) - Right Line Input 3&4 Volume
518 */ 531 */
519 #define WM8400_IPVU 532 #define WM8400_IPVU 0x0100 /* IPVU */
520 #define WM8400_IPVU_MASK 533 #define WM8400_IPVU_MASK 0x0100 /* IPVU */
521 #define WM8400_IPVU_SHIFT 534 #define WM8400_IPVU_SHIFT 8 /* IPVU */
522 #define WM8400_IPVU_WIDTH 535 #define WM8400_IPVU_WIDTH 1 /* IPVU */
523 #define WM8400_RI34MUTE 536 #define WM8400_RI34MUTE 0x0080 /* RI34MUTE */
524 #define WM8400_RI34MUTE_MASK 537 #define WM8400_RI34MUTE_MASK 0x0080 /* RI34MUTE */
525 #define WM8400_RI34MUTE_SHIFT 538 #define WM8400_RI34MUTE_SHIFT 7 /* RI34MUTE */
526 #define WM8400_RI34MUTE_WIDTH 539 #define WM8400_RI34MUTE_WIDTH 1 /* RI34MUTE */
527 #define WM8400_RI34ZC 540 #define WM8400_RI34ZC 0x0040 /* RI34ZC */
528 #define WM8400_RI34ZC_MASK 541 #define WM8400_RI34ZC_MASK 0x0040 /* RI34ZC */
529 #define WM8400_RI34ZC_SHIFT 542 #define WM8400_RI34ZC_SHIFT 6 /* RI34ZC */
530 #define WM8400_RI34ZC_WIDTH 543 #define WM8400_RI34ZC_WIDTH 1 /* RI34ZC */
531 #define WM8400_RIN34VOL_MASK 544 #define WM8400_RIN34VOL_MASK 0x001F /* RIN34VOL - [4:0] */
532 #define WM8400_RIN34VOL_SHIFT 545 #define WM8400_RIN34VOL_SHIFT 0 /* RIN34VOL - [4:0] */
533 #define WM8400_RIN34VOL_WIDTH 546 #define WM8400_RIN34VOL_WIDTH 5 /* RIN34VOL - [4:0] */
534 547
535 /* 548 /*
536 * R28 (0x1C) - Left Output Volume 549 * R28 (0x1C) - Left Output Volume
537 */ 550 */
538 #define WM8400_OPVU 551 #define WM8400_OPVU 0x0100 /* OPVU */
539 #define WM8400_OPVU_MASK 552 #define WM8400_OPVU_MASK 0x0100 /* OPVU */
540 #define WM8400_OPVU_SHIFT 553 #define WM8400_OPVU_SHIFT 8 /* OPVU */
541 #define WM8400_OPVU_WIDTH 554 #define WM8400_OPVU_WIDTH 1 /* OPVU */
542 #define WM8400_LOZC 555 #define WM8400_LOZC 0x0080 /* LOZC */
543 #define WM8400_LOZC_MASK 556 #define WM8400_LOZC_MASK 0x0080 /* LOZC */
544 #define WM8400_LOZC_SHIFT 557 #define WM8400_LOZC_SHIFT 7 /* LOZC */
545 #define WM8400_LOZC_WIDTH 558 #define WM8400_LOZC_WIDTH 1 /* LOZC */
546 #define WM8400_LOUTVOL_MASK 559 #define WM8400_LOUTVOL_MASK 0x007F /* LOUTVOL - [6:0] */
547 #define WM8400_LOUTVOL_SHIFT 560 #define WM8400_LOUTVOL_SHIFT 0 /* LOUTVOL - [6:0] */
548 #define WM8400_LOUTVOL_WIDTH 561 #define WM8400_LOUTVOL_WIDTH 7 /* LOUTVOL - [6:0] */
549 562
550 /* 563 /*
551 * R29 (0x1D) - Right Output Volume 564 * R29 (0x1D) - Right Output Volume
552 */ 565 */
553 #define WM8400_OPVU 566 #define WM8400_OPVU 0x0100 /* OPVU */
554 #define WM8400_OPVU_MASK 567 #define WM8400_OPVU_MASK 0x0100 /* OPVU */
555 #define WM8400_OPVU_SHIFT 568 #define WM8400_OPVU_SHIFT 8 /* OPVU */
556 #define WM8400_OPVU_WIDTH 569 #define WM8400_OPVU_WIDTH 1 /* OPVU */
557 #define WM8400_ROZC 570 #define WM8400_ROZC 0x0080 /* ROZC */
558 #define WM8400_ROZC_MASK 571 #define WM8400_ROZC_MASK 0x0080 /* ROZC */
559 #define WM8400_ROZC_SHIFT 572 #define WM8400_ROZC_SHIFT 7 /* ROZC */
560 #define WM8400_ROZC_WIDTH 573 #define WM8400_ROZC_WIDTH 1 /* ROZC */
561 #define WM8400_ROUTVOL_MASK 574 #define WM8400_ROUTVOL_MASK 0x007F /* ROUTVOL - [6:0] */
562 #define WM8400_ROUTVOL_SHIFT 575 #define WM8400_ROUTVOL_SHIFT 0 /* ROUTVOL - [6:0] */
563 #define WM8400_ROUTVOL_WIDTH 576 #define WM8400_ROUTVOL_WIDTH 7 /* ROUTVOL - [6:0] */
564 577
565 /* 578 /*
566 * R30 (0x1E) - Line Outputs Volume 579 * R30 (0x1E) - Line Outputs Volume
567 */ 580 */
568 #define WM8400_LONMUTE 581 #define WM8400_LONMUTE 0x0040 /* LONMUTE */
569 #define WM8400_LONMUTE_MASK 582 #define WM8400_LONMUTE_MASK 0x0040 /* LONMUTE */
570 #define WM8400_LONMUTE_SHIFT 583 #define WM8400_LONMUTE_SHIFT 6 /* LONMUTE */
571 #define WM8400_LONMUTE_WIDTH 584 #define WM8400_LONMUTE_WIDTH 1 /* LONMUTE */
572 #define WM8400_LOPMUTE 585 #define WM8400_LOPMUTE 0x0020 /* LOPMUTE */
573 #define WM8400_LOPMUTE_MASK 586 #define WM8400_LOPMUTE_MASK 0x0020 /* LOPMUTE */
574 #define WM8400_LOPMUTE_SHIFT 587 #define WM8400_LOPMUTE_SHIFT 5 /* LOPMUTE */
575 #define WM8400_LOPMUTE_WIDTH 588 #define WM8400_LOPMUTE_WIDTH 1 /* LOPMUTE */
576 #define WM8400_LOATTN 589 #define WM8400_LOATTN 0x0010 /* LOATTN */
577 #define WM8400_LOATTN_MASK 590 #define WM8400_LOATTN_MASK 0x0010 /* LOATTN */
578 #define WM8400_LOATTN_SHIFT 591 #define WM8400_LOATTN_SHIFT 4 /* LOATTN */
579 #define WM8400_LOATTN_WIDTH 592 #define WM8400_LOATTN_WIDTH 1 /* LOATTN */
580 #define WM8400_RONMUTE 593 #define WM8400_RONMUTE 0x0004 /* RONMUTE */
581 #define WM8400_RONMUTE_MASK 594 #define WM8400_RONMUTE_MASK 0x0004 /* RONMUTE */
582 #define WM8400_RONMUTE_SHIFT 595 #define WM8400_RONMUTE_SHIFT 2 /* RONMUTE */
583 #define WM8400_RONMUTE_WIDTH 596 #define WM8400_RONMUTE_WIDTH 1 /* RONMUTE */
584 #define WM8400_ROPMUTE 597 #define WM8400_ROPMUTE 0x0002 /* ROPMUTE */
585 #define WM8400_ROPMUTE_MASK 598 #define WM8400_ROPMUTE_MASK 0x0002 /* ROPMUTE */
586 #define WM8400_ROPMUTE_SHIFT 599 #define WM8400_ROPMUTE_SHIFT 1 /* ROPMUTE */
587 #define WM8400_ROPMUTE_WIDTH 600 #define WM8400_ROPMUTE_WIDTH 1 /* ROPMUTE */
588 #define WM8400_ROATTN 601 #define WM8400_ROATTN 0x0001 /* ROATTN */
589 #define WM8400_ROATTN_MASK 602 #define WM8400_ROATTN_MASK 0x0001 /* ROATTN */
590 #define WM8400_ROATTN_SHIFT 603 #define WM8400_ROATTN_SHIFT 0 /* ROATTN */
591 #define WM8400_ROATTN_WIDTH 604 #define WM8400_ROATTN_WIDTH 1 /* ROATTN */
592 605
593 /* 606 /*
594 * R31 (0x1F) - Out3/4 Volume 607 * R31 (0x1F) - Out3/4 Volume
595 */ 608 */
596 #define WM8400_OUT3MUTE 609 #define WM8400_OUT3MUTE 0x0020 /* OUT3MUTE */
597 #define WM8400_OUT3MUTE_MASK 610 #define WM8400_OUT3MUTE_MASK 0x0020 /* OUT3MUTE */
598 #define WM8400_OUT3MUTE_SHIFT 611 #define WM8400_OUT3MUTE_SHIFT 5 /* OUT3MUTE */
599 #define WM8400_OUT3MUTE_WIDTH 612 #define WM8400_OUT3MUTE_WIDTH 1 /* OUT3MUTE */
600 #define WM8400_OUT3ATTN 613 #define WM8400_OUT3ATTN 0x0010 /* OUT3ATTN */
601 #define WM8400_OUT3ATTN_MASK 614 #define WM8400_OUT3ATTN_MASK 0x0010 /* OUT3ATTN */
602 #define WM8400_OUT3ATTN_SHIFT 615 #define WM8400_OUT3ATTN_SHIFT 4 /* OUT3ATTN */
603 #define WM8400_OUT3ATTN_WIDTH 616 #define WM8400_OUT3ATTN_WIDTH 1 /* OUT3ATTN */
604 #define WM8400_OUT4MUTE 617 #define WM8400_OUT4MUTE 0x0002 /* OUT4MUTE */
605 #define WM8400_OUT4MUTE_MASK 618 #define WM8400_OUT4MUTE_MASK 0x0002 /* OUT4MUTE */
606 #define WM8400_OUT4MUTE_SHIFT 619 #define WM8400_OUT4MUTE_SHIFT 1 /* OUT4MUTE */
607 #define WM8400_OUT4MUTE_WIDTH 620 #define WM8400_OUT4MUTE_WIDTH 1 /* OUT4MUTE */
608 #define WM8400_OUT4ATTN 621 #define WM8400_OUT4ATTN 0x0001 /* OUT4ATTN */
609 #define WM8400_OUT4ATTN_MASK 622 #define WM8400_OUT4ATTN_MASK 0x0001 /* OUT4ATTN */
610 #define WM8400_OUT4ATTN_SHIFT 623 #define WM8400_OUT4ATTN_SHIFT 0 /* OUT4ATTN */
611 #define WM8400_OUT4ATTN_WIDTH 624 #define WM8400_OUT4ATTN_WIDTH 1 /* OUT4ATTN */
612 625
613 /* 626 /*
614 * R32 (0x20) - Left OPGA Volume 627 * R32 (0x20) - Left OPGA Volume
615 */ 628 */
616 #define WM8400_OPVU 629 #define WM8400_OPVU 0x0100 /* OPVU */
617 #define WM8400_OPVU_MASK 630 #define WM8400_OPVU_MASK 0x0100 /* OPVU */
618 #define WM8400_OPVU_SHIFT 631 #define WM8400_OPVU_SHIFT 8 /* OPVU */
619 #define WM8400_OPVU_WIDTH 632 #define WM8400_OPVU_WIDTH 1 /* OPVU */
620 #define WM8400_LOPGAZC 633 #define WM8400_LOPGAZC 0x0080 /* LOPGAZC */
621 #define WM8400_LOPGAZC_MASK 634 #define WM8400_LOPGAZC_MASK 0x0080 /* LOPGAZC */
622 #define WM8400_LOPGAZC_SHIFT 635 #define WM8400_LOPGAZC_SHIFT 7 /* LOPGAZC */
623 #define WM8400_LOPGAZC_WIDTH 636 #define WM8400_LOPGAZC_WIDTH 1 /* LOPGAZC */
624 #define WM8400_LOPGAVOL_MASK 637 #define WM8400_LOPGAVOL_MASK 0x007F /* LOPGAVOL - [6:0] */
625 #define WM8400_LOPGAVOL_SHIFT 638 #define WM8400_LOPGAVOL_SHIFT 0 /* LOPGAVOL - [6:0] */
626 #define WM8400_LOPGAVOL_WIDTH 639 #define WM8400_LOPGAVOL_WIDTH 7 /* LOPGAVOL - [6:0] */
627 640
628 /* 641 /*
629 * R33 (0x21) - Right OPGA Volume 642 * R33 (0x21) - Right OPGA Volume
630 */ 643 */
631 #define WM8400_OPVU 644 #define WM8400_OPVU 0x0100 /* OPVU */
632 #define WM8400_OPVU_MASK 645 #define WM8400_OPVU_MASK 0x0100 /* OPVU */
633 #define WM8400_OPVU_SHIFT 646 #define WM8400_OPVU_SHIFT 8 /* OPVU */
634 #define WM8400_OPVU_WIDTH 647 #define WM8400_OPVU_WIDTH 1 /* OPVU */
635 #define WM8400_ROPGAZC 648 #define WM8400_ROPGAZC 0x0080 /* ROPGAZC */
636 #define WM8400_ROPGAZC_MASK 649 #define WM8400_ROPGAZC_MASK 0x0080 /* ROPGAZC */
637 #define WM8400_ROPGAZC_SHIFT 650 #define WM8400_ROPGAZC_SHIFT 7 /* ROPGAZC */
638 #define WM8400_ROPGAZC_WIDTH 651 #define WM8400_ROPGAZC_WIDTH 1 /* ROPGAZC */
639 #define WM8400_ROPGAVOL_MASK 652 #define WM8400_ROPGAVOL_MASK 0x007F /* ROPGAVOL - [6:0] */
640 #define WM8400_ROPGAVOL_SHIFT 653 #define WM8400_ROPGAVOL_SHIFT 0 /* ROPGAVOL - [6:0] */
641 #define WM8400_ROPGAVOL_WIDTH 654 #define WM8400_ROPGAVOL_WIDTH 7 /* ROPGAVOL - [6:0] */
642 655
643 /* 656 /*
644 * R34 (0x22) - Speaker Volume 657 * R34 (0x22) - Speaker Volume
645 */ 658 */
646 #define WM8400_SPKATTN_MASK 659 #define WM8400_SPKATTN_MASK 0x0003 /* SPKATTN - [1:0] */
647 #define WM8400_SPKATTN_SHIFT 660 #define WM8400_SPKATTN_SHIFT 0 /* SPKATTN - [1:0] */
648 #define WM8400_SPKATTN_WIDTH 661 #define WM8400_SPKATTN_WIDTH 2 /* SPKATTN - [1:0] */
649 662
650 /* 663 /*
651 * R35 (0x23) - ClassD1 664 * R35 (0x23) - ClassD1
652 */ 665 */
653 #define WM8400_CDMODE 666 #define WM8400_CDMODE 0x0100 /* CDMODE */
654 #define WM8400_CDMODE_MASK 667 #define WM8400_CDMODE_MASK 0x0100 /* CDMODE */
655 #define WM8400_CDMODE_SHIFT 668 #define WM8400_CDMODE_SHIFT 8 /* CDMODE */
656 #define WM8400_CDMODE_WIDTH 669 #define WM8400_CDMODE_WIDTH 1 /* CDMODE */
657 #define WM8400_CLASSD_CLK_SEL 670 #define WM8400_CLASSD_CLK_SEL 0x0080 /* CLASSD_CLK_SEL */
658 #define WM8400_CLASSD_CLK_SEL_MASK 671 #define WM8400_CLASSD_CLK_SEL_MASK 0x0080 /* CLASSD_CLK_SEL */
659 #define WM8400_CLASSD_CLK_SEL_SHIFT 672 #define WM8400_CLASSD_CLK_SEL_SHIFT 7 /* CLASSD_CLK_SEL */
660 #define WM8400_CLASSD_CLK_SEL_WIDTH 673 #define WM8400_CLASSD_CLK_SEL_WIDTH 1 /* CLASSD_CLK_SEL */
661 #define WM8400_CD_SRCTRL 674 #define WM8400_CD_SRCTRL 0x0040 /* CD_SRCTRL */
662 #define WM8400_CD_SRCTRL_MASK 675 #define WM8400_CD_SRCTRL_MASK 0x0040 /* CD_SRCTRL */
663 #define WM8400_CD_SRCTRL_SHIFT 676 #define WM8400_CD_SRCTRL_SHIFT 6 /* CD_SRCTRL */
664 #define WM8400_CD_SRCTRL_WIDTH 677 #define WM8400_CD_SRCTRL_WIDTH 1 /* CD_SRCTRL */
665 #define WM8400_SPKNOPOP 678 #define WM8400_SPKNOPOP 0x0020 /* SPKNOPOP */
666 #define WM8400_SPKNOPOP_MASK 679 #define WM8400_SPKNOPOP_MASK 0x0020 /* SPKNOPOP */
667 #define WM8400_SPKNOPOP_SHIFT 680 #define WM8400_SPKNOPOP_SHIFT 5 /* SPKNOPOP */
668 #define WM8400_SPKNOPOP_WIDTH 681 #define WM8400_SPKNOPOP_WIDTH 1 /* SPKNOPOP */
669 #define WM8400_DBLERATE 682 #define WM8400_DBLERATE 0x0010 /* DBLERATE */
670 #define WM8400_DBLERATE_MASK 683 #define WM8400_DBLERATE_MASK 0x0010 /* DBLERATE */
671 #define WM8400_DBLERATE_SHIFT 684 #define WM8400_DBLERATE_SHIFT 4 /* DBLERATE */
672 #define WM8400_DBLERATE_WIDTH 685 #define WM8400_DBLERATE_WIDTH 1 /* DBLERATE */
673 #define WM8400_LOOPTEST 686 #define WM8400_LOOPTEST 0x0008 /* LOOPTEST */
674 #define WM8400_LOOPTEST_MASK 687 #define WM8400_LOOPTEST_MASK 0x0008 /* LOOPTEST */
675 #define WM8400_LOOPTEST_SHIFT 688 #define WM8400_LOOPTEST_SHIFT 3 /* LOOPTEST */
676 #define WM8400_LOOPTEST_WIDTH 689 #define WM8400_LOOPTEST_WIDTH 1 /* LOOPTEST */
677 #define WM8400_HALFABBIAS 690 #define WM8400_HALFABBIAS 0x0004 /* HALFABBIAS */
678 #define WM8400_HALFABBIAS_MASK 691 #define WM8400_HALFABBIAS_MASK 0x0004 /* HALFABBIAS */
679 #define WM8400_HALFABBIAS_SHIFT 692 #define WM8400_HALFABBIAS_SHIFT 2 /* HALFABBIAS */
680 #define WM8400_HALFABBIAS_WIDTH 693 #define WM8400_HALFABBIAS_WIDTH 1 /* HALFABBIAS */
681 #define WM8400_TRIDEL_MASK 694 #define WM8400_TRIDEL_MASK 0x0003 /* TRIDEL - [1:0] */
682 #define WM8400_TRIDEL_SHIFT 695 #define WM8400_TRIDEL_SHIFT 0 /* TRIDEL - [1:0] */
683 #define WM8400_TRIDEL_WIDTH 696 #define WM8400_TRIDEL_WIDTH 2 /* TRIDEL - [1:0] */
684 697
685 /* 698 /*
686 * R37 (0x25) - ClassD3 699 * R37 (0x25) - ClassD3
687 */ 700 */
688 #define WM8400_DCGAIN_MASK 701 #define WM8400_DCGAIN_MASK 0x0038 /* DCGAIN - [5:3] */
689 #define WM8400_DCGAIN_SHIFT 702 #define WM8400_DCGAIN_SHIFT 3 /* DCGAIN - [5:3] */
690 #define WM8400_DCGAIN_WIDTH 703 #define WM8400_DCGAIN_WIDTH 3 /* DCGAIN - [5:3] */
691 #define WM8400_ACGAIN_MASK 704 #define WM8400_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */
692 #define WM8400_ACGAIN_SHIFT 705 #define WM8400_ACGAIN_SHIFT 0 /* ACGAIN - [2:0] */
693 #define WM8400_ACGAIN_WIDTH 706 #define WM8400_ACGAIN_WIDTH 3 /* ACGAIN - [2:0] */
694 707
695 /* 708 /*
696 * R39 (0x27) - Input Mixer1 709 * R39 (0x27) - Input Mixer1
697 */ 710 */
698 #define WM8400_AINLMODE_MASK 711 #define WM8400_AINLMODE_MASK 0x000C /* AINLMODE - [3:2] */
699 #define WM8400_AINLMODE_SHIFT 712 #define WM8400_AINLMODE_SHIFT 2 /* AINLMODE - [3:2] */
700 #define WM8400_AINLMODE_WIDTH 713 #define WM8400_AINLMODE_WIDTH 2 /* AINLMODE - [3:2] */
701 #define WM8400_AINRMODE_MASK 714 #define WM8400_AINRMODE_MASK 0x0003 /* AINRMODE - [1:0] */
702 #define WM8400_AINRMODE_SHIFT 715 #define WM8400_AINRMODE_SHIFT 0 /* AINRMODE - [1:0] */
703 #define WM8400_AINRMODE_WIDTH 716 #define WM8400_AINRMODE_WIDTH 2 /* AINRMODE - [1:0] */
704 717
705 /* 718 /*
706 * R40 (0x28) - Input Mixer2 719 * R40 (0x28) - Input Mixer2
707 */ 720 */
708 #define WM8400_LMP4 721 #define WM8400_LMP4 0x0080 /* LMP4 */
709 #define WM8400_LMP4_MASK 722 #define WM8400_LMP4_MASK 0x0080 /* LMP4 */
710 #define WM8400_LMP4_SHIFT 723 #define WM8400_LMP4_SHIFT 7 /* LMP4 */
711 #define WM8400_LMP4_WIDTH 724 #define WM8400_LMP4_WIDTH 1 /* LMP4 */
712 #define WM8400_LMN3 725 #define WM8400_LMN3 0x0040 /* LMN3 */
713 #define WM8400_LMN3_MASK 726 #define WM8400_LMN3_MASK 0x0040 /* LMN3 */
714 #define WM8400_LMN3_SHIFT 727 #define WM8400_LMN3_SHIFT 6 /* LMN3 */
715 #define WM8400_LMN3_WIDTH 728 #define WM8400_LMN3_WIDTH 1 /* LMN3 */
716 #define WM8400_LMP2 729 #define WM8400_LMP2 0x0020 /* LMP2 */
717 #define WM8400_LMP2_MASK 730 #define WM8400_LMP2_MASK 0x0020 /* LMP2 */
718 #define WM8400_LMP2_SHIFT 731 #define WM8400_LMP2_SHIFT 5 /* LMP2 */
719 #define WM8400_LMP2_WIDTH 732 #define WM8400_LMP2_WIDTH 1 /* LMP2 */
720 #define WM8400_LMN1 733 #define WM8400_LMN1 0x0010 /* LMN1 */
721 #define WM8400_LMN1_MASK 734 #define WM8400_LMN1_MASK 0x0010 /* LMN1 */
722 #define WM8400_LMN1_SHIFT 735 #define WM8400_LMN1_SHIFT 4 /* LMN1 */
723 #define WM8400_LMN1_WIDTH 736 #define WM8400_LMN1_WIDTH 1 /* LMN1 */
724 #define WM8400_RMP4 737 #define WM8400_RMP4 0x0008 /* RMP4 */
725 #define WM8400_RMP4_MASK 738 #define WM8400_RMP4_MASK 0x0008 /* RMP4 */
726 #define WM8400_RMP4_SHIFT 739 #define WM8400_RMP4_SHIFT 3 /* RMP4 */
727 #define WM8400_RMP4_WIDTH 740 #define WM8400_RMP4_WIDTH 1 /* RMP4 */
728 #define WM8400_RMN3 741 #define WM8400_RMN3 0x0004 /* RMN3 */
729 #define WM8400_RMN3_MASK 742 #define WM8400_RMN3_MASK 0x0004 /* RMN3 */
730 #define WM8400_RMN3_SHIFT 743 #define WM8400_RMN3_SHIFT 2 /* RMN3 */
731 #define WM8400_RMN3_WIDTH 744 #define WM8400_RMN3_WIDTH 1 /* RMN3 */
732 #define WM8400_RMP2 745 #define WM8400_RMP2 0x0002 /* RMP2 */
733 #define WM8400_RMP2_MASK 746 #define WM8400_RMP2_MASK 0x0002 /* RMP2 */
734 #define WM8400_RMP2_SHIFT 747 #define WM8400_RMP2_SHIFT 1 /* RMP2 */
735 #define WM8400_RMP2_WIDTH 748 #define WM8400_RMP2_WIDTH 1 /* RMP2 */
736 #define WM8400_RMN1 749 #define WM8400_RMN1 0x0001 /* RMN1 */
737 #define WM8400_RMN1_MASK 750 #define WM8400_RMN1_MASK 0x0001 /* RMN1 */
738 #define WM8400_RMN1_SHIFT 751 #define WM8400_RMN1_SHIFT 0 /* RMN1 */
739 #define WM8400_RMN1_WIDTH 752 #define WM8400_RMN1_WIDTH 1 /* RMN1 */
740 753
741 /* 754 /*
742 * R41 (0x29) - Input Mixer3 755 * R41 (0x29) - Input Mixer3
743 */ 756 */
744 #define WM8400_L34MNB 757 #define WM8400_L34MNB 0x0100 /* L34MNB */
745 #define WM8400_L34MNB_MASK 758 #define WM8400_L34MNB_MASK 0x0100 /* L34MNB */
746 #define WM8400_L34MNB_SHIFT 759 #define WM8400_L34MNB_SHIFT 8 /* L34MNB */
747 #define WM8400_L34MNB_WIDTH 760 #define WM8400_L34MNB_WIDTH 1 /* L34MNB */
748 #define WM8400_L34MNBST 761 #define WM8400_L34MNBST 0x0080 /* L34MNBST */
749 #define WM8400_L34MNBST_MASK 762 #define WM8400_L34MNBST_MASK 0x0080 /* L34MNBST */
750 #define WM8400_L34MNBST_SHIFT 763 #define WM8400_L34MNBST_SHIFT 7 /* L34MNBST */
751 #define WM8400_L34MNBST_WIDTH 764 #define WM8400_L34MNBST_WIDTH 1 /* L34MNBST */
752 #define WM8400_L12MNB 765 #define WM8400_L12MNB 0x0020 /* L12MNB */
753 #define WM8400_L12MNB_MASK 766 #define WM8400_L12MNB_MASK 0x0020 /* L12MNB */
754 #define WM8400_L12MNB_SHIFT 767 #define WM8400_L12MNB_SHIFT 5 /* L12MNB */
755 #define WM8400_L12MNB_WIDTH 768 #define WM8400_L12MNB_WIDTH 1 /* L12MNB */
756 #define WM8400_L12MNBST 769 #define WM8400_L12MNBST 0x0010 /* L12MNBST */
757 #define WM8400_L12MNBST_MASK 770 #define WM8400_L12MNBST_MASK 0x0010 /* L12MNBST */
758 #define WM8400_L12MNBST_SHIFT 771 #define WM8400_L12MNBST_SHIFT 4 /* L12MNBST */
759 #define WM8400_L12MNBST_WIDTH 772 #define WM8400_L12MNBST_WIDTH 1 /* L12MNBST */
760 #define WM8400_LDBVOL_MASK 773 #define WM8400_LDBVOL_MASK 0x0007 /* LDBVOL - [2:0] */
761 #define WM8400_LDBVOL_SHIFT 774 #define WM8400_LDBVOL_SHIFT 0 /* LDBVOL - [2:0] */
762 #define WM8400_LDBVOL_WIDTH 775 #define WM8400_LDBVOL_WIDTH 3 /* LDBVOL - [2:0] */
763 776
764 /* 777 /*
765 * R42 (0x2A) - Input Mixer4 778 * R42 (0x2A) - Input Mixer4
766 */ 779 */
767 #define WM8400_R34MNB 780 #define WM8400_R34MNB 0x0100 /* R34MNB */
768 #define WM8400_R34MNB_MASK 781 #define WM8400_R34MNB_MASK 0x0100 /* R34MNB */
769 #define WM8400_R34MNB_SHIFT 782 #define WM8400_R34MNB_SHIFT 8 /* R34MNB */
770 #define WM8400_R34MNB_WIDTH 783 #define WM8400_R34MNB_WIDTH 1 /* R34MNB */
771 #define WM8400_R34MNBST 784 #define WM8400_R34MNBST 0x0080 /* R34MNBST */
772 #define WM8400_R34MNBST_MASK 785 #define WM8400_R34MNBST_MASK 0x0080 /* R34MNBST */
773 #define WM8400_R34MNBST_SHIFT 786 #define WM8400_R34MNBST_SHIFT 7 /* R34MNBST */
774 #define WM8400_R34MNBST_WIDTH 787 #define WM8400_R34MNBST_WIDTH 1 /* R34MNBST */
775 #define WM8400_R12MNB 788 #define WM8400_R12MNB 0x0020 /* R12MNB */
776 #define WM8400_R12MNB_MASK 789 #define WM8400_R12MNB_MASK 0x0020 /* R12MNB */
777 #define WM8400_R12MNB_SHIFT 790 #define WM8400_R12MNB_SHIFT 5 /* R12MNB */
778 #define WM8400_R12MNB_WIDTH 791 #define WM8400_R12MNB_WIDTH 1 /* R12MNB */
779 #define WM8400_R12MNBST 792 #define WM8400_R12MNBST 0x0010 /* R12MNBST */
780 #define WM8400_R12MNBST_MASK 793 #define WM8400_R12MNBST_MASK 0x0010 /* R12MNBST */
781 #define WM8400_R12MNBST_SHIFT 794 #define WM8400_R12MNBST_SHIFT 4 /* R12MNBST */
782 #define WM8400_R12MNBST_WIDTH 795 #define WM8400_R12MNBST_WIDTH 1 /* R12MNBST */
783 #define WM8400_RDBVOL_MASK 796 #define WM8400_RDBVOL_MASK 0x0007 /* RDBVOL - [2:0] */
784 #define WM8400_RDBVOL_SHIFT 797 #define WM8400_RDBVOL_SHIFT 0 /* RDBVOL - [2:0] */
785 #define WM8400_RDBVOL_WIDTH 798 #define WM8400_RDBVOL_WIDTH 3 /* RDBVOL - [2:0] */
786 799
787 /* 800 /*
788 * R43 (0x2B) - Input Mixer5 801 * R43 (0x2B) - Input Mixer5
789 */ 802 */
790 #define WM8400_LI2BVOL_MASK 803 #define WM8400_LI2BVOL_MASK 0x01C0 /* LI2BVOL - [8:6] */
791 #define WM8400_LI2BVOL_SHIFT 804 #define WM8400_LI2BVOL_SHIFT 6 /* LI2BVOL - [8:6] */
792 #define WM8400_LI2BVOL_WIDTH 805 #define WM8400_LI2BVOL_WIDTH 3 /* LI2BVOL - [8:6] */
793 #define WM8400_LR4BVOL_MASK 806 #define WM8400_LR4BVOL_MASK 0x0038 /* LR4BVOL - [5:3] */
794 #define WM8400_LR4BVOL_SHIFT 807 #define WM8400_LR4BVOL_SHIFT 3 /* LR4BVOL - [5:3] */
795 #define WM8400_LR4BVOL_WIDTH 808 #define WM8400_LR4BVOL_WIDTH 3 /* LR4BVOL - [5:3] */
796 #define WM8400_LL4BVOL_MASK 809 #define WM8400_LL4BVOL_MASK 0x0007 /* LL4BVOL - [2:0] */
797 #define WM8400_LL4BVOL_SHIFT 810 #define WM8400_LL4BVOL_SHIFT 0 /* LL4BVOL - [2:0] */
798 #define WM8400_LL4BVOL_WIDTH 811 #define WM8400_LL4BVOL_WIDTH 3 /* LL4BVOL - [2:0] */
799 812
800 /* 813 /*
801 * R44 (0x2C) - Input Mixer6 814 * R44 (0x2C) - Input Mixer6
802 */ 815 */
803 #define WM8400_RI2BVOL_MASK 816 #define WM8400_RI2BVOL_MASK 0x01C0 /* RI2BVOL - [8:6] */
804 #define WM8400_RI2BVOL_SHIFT 817 #define WM8400_RI2BVOL_SHIFT 6 /* RI2BVOL - [8:6] */
805 #define WM8400_RI2BVOL_WIDTH 818 #define WM8400_RI2BVOL_WIDTH 3 /* RI2BVOL - [8:6] */
806 #define WM8400_RL4BVOL_MASK 819 #define WM8400_RL4BVOL_MASK 0x0038 /* RL4BVOL - [5:3] */
807 #define WM8400_RL4BVOL_SHIFT 820 #define WM8400_RL4BVOL_SHIFT 3 /* RL4BVOL - [5:3] */
808 #define WM8400_RL4BVOL_WIDTH 821 #define WM8400_RL4BVOL_WIDTH 3 /* RL4BVOL - [5:3] */
809 #define WM8400_RR4BVOL_MASK 822 #define WM8400_RR4BVOL_MASK 0x0007 /* RR4BVOL - [2:0] */
810 #define WM8400_RR4BVOL_SHIFT 823 #define WM8400_RR4BVOL_SHIFT 0 /* RR4BVOL - [2:0] */
811 #define WM8400_RR4BVOL_WIDTH 824 #define WM8400_RR4BVOL_WIDTH 3 /* RR4BVOL - [2:0] */
812 825
813 /* 826 /*
814 * R45 (0x2D) - Output Mixer1 827 * R45 (0x2D) - Output Mixer1
815 */ 828 */
816 #define WM8400_LRBLO 829 #define WM8400_LRBLO 0x0080 /* LRBLO */
817 #define WM8400_LRBLO_MASK 830 #define WM8400_LRBLO_MASK 0x0080 /* LRBLO */
818 #define WM8400_LRBLO_SHIFT 831 #define WM8400_LRBLO_SHIFT 7 /* LRBLO */
819 #define WM8400_LRBLO_WIDTH 832 #define WM8400_LRBLO_WIDTH 1 /* LRBLO */
820 #define WM8400_LLBLO 833 #define WM8400_LLBLO 0x0040 /* LLBLO */
821 #define WM8400_LLBLO_MASK 834 #define WM8400_LLBLO_MASK 0x0040 /* LLBLO */
822 #define WM8400_LLBLO_SHIFT 835 #define WM8400_LLBLO_SHIFT 6 /* LLBLO */
823 #define WM8400_LLBLO_WIDTH 836 #define WM8400_LLBLO_WIDTH 1 /* LLBLO */
824 #define WM8400_LRI3LO 837 #define WM8400_LRI3LO 0x0020 /* LRI3LO */
825 #define WM8400_LRI3LO_MASK 838 #define WM8400_LRI3LO_MASK 0x0020 /* LRI3LO */
826 #define WM8400_LRI3LO_SHIFT 839 #define WM8400_LRI3LO_SHIFT 5 /* LRI3LO */
827 #define WM8400_LRI3LO_WIDTH 840 #define WM8400_LRI3LO_WIDTH 1 /* LRI3LO */
828 #define WM8400_LLI3LO 841 #define WM8400_LLI3LO 0x0010 /* LLI3LO */
829 #define WM8400_LLI3LO_MASK 842 #define WM8400_LLI3LO_MASK 0x0010 /* LLI3LO */
830 #define WM8400_LLI3LO_SHIFT 843 #define WM8400_LLI3LO_SHIFT 4 /* LLI3LO */
831 #define WM8400_LLI3LO_WIDTH 844 #define WM8400_LLI3LO_WIDTH 1 /* LLI3LO */
832 #define WM8400_LR12LO 845 #define WM8400_LR12LO 0x0008 /* LR12LO */
833 #define WM8400_LR12LO_MASK 846 #define WM8400_LR12LO_MASK 0x0008 /* LR12LO */
834 #define WM8400_LR12LO_SHIFT 847 #define WM8400_LR12LO_SHIFT 3 /* LR12LO */
835 #define WM8400_LR12LO_WIDTH 848 #define WM8400_LR12LO_WIDTH 1 /* LR12LO */
836 #define WM8400_LL12LO 849 #define WM8400_LL12LO 0x0004 /* LL12LO */
837 #define WM8400_LL12LO_MASK 850 #define WM8400_LL12LO_MASK 0x0004 /* LL12LO */
838 #define WM8400_LL12LO_SHIFT 851 #define WM8400_LL12LO_SHIFT 2 /* LL12LO */
839 #define WM8400_LL12LO_WIDTH 852 #define WM8400_LL12LO_WIDTH 1 /* LL12LO */
840 #define WM8400_LDLO 853 #define WM8400_LDLO 0x0001 /* LDLO */
841 #define WM8400_LDLO_MASK 854 #define WM8400_LDLO_MASK 0x0001 /* LDLO */
842 #define WM8400_LDLO_SHIFT 855 #define WM8400_LDLO_SHIFT 0 /* LDLO */
843 #define WM8400_LDLO_WIDTH 856 #define WM8400_LDLO_WIDTH 1 /* LDLO */
844 857
845 /* 858 /*
846 * R46 (0x2E) - Output Mixer2 859 * R46 (0x2E) - Output Mixer2
847 */ 860 */
848 #define WM8400_RLBRO 861 #define WM8400_RLBRO 0x0080 /* RLBRO */
849 #define WM8400_RLBRO_MASK 862 #define WM8400_RLBRO_MASK 0x0080 /* RLBRO */
850 #define WM8400_RLBRO_SHIFT 863 #define WM8400_RLBRO_SHIFT 7 /* RLBRO */
851 #define WM8400_RLBRO_WIDTH 864 #define WM8400_RLBRO_WIDTH 1 /* RLBRO */
852 #define WM8400_RRBRO 865 #define WM8400_RRBRO 0x0040 /* RRBRO */
853 #define WM8400_RRBRO_MASK 866 #define WM8400_RRBRO_MASK 0x0040 /* RRBRO */
854 #define WM8400_RRBRO_SHIFT 867 #define WM8400_RRBRO_SHIFT 6 /* RRBRO */
855 #define WM8400_RRBRO_WIDTH 868 #define WM8400_RRBRO_WIDTH 1 /* RRBRO */
856 #define WM8400_RLI3RO 869 #define WM8400_RLI3RO 0x0020 /* RLI3RO */
857 #define WM8400_RLI3RO_MASK 870 #define WM8400_RLI3RO_MASK 0x0020 /* RLI3RO */
858 #define WM8400_RLI3RO_SHIFT 871 #define WM8400_RLI3RO_SHIFT 5 /* RLI3RO */
859 #define WM8400_RLI3RO_WIDTH 872 #define WM8400_RLI3RO_WIDTH 1 /* RLI3RO */
860 #define WM8400_RRI3RO 873 #define WM8400_RRI3RO 0x0010 /* RRI3RO */
861 #define WM8400_RRI3RO_MASK 874 #define WM8400_RRI3RO_MASK 0x0010 /* RRI3RO */
862 #define WM8400_RRI3RO_SHIFT 875 #define WM8400_RRI3RO_SHIFT 4 /* RRI3RO */
863 #define WM8400_RRI3RO_WIDTH 876 #define WM8400_RRI3RO_WIDTH 1 /* RRI3RO */
864 #define WM8400_RL12RO 877 #define WM8400_RL12RO 0x0008 /* RL12RO */
865 #define WM8400_RL12RO_MASK 878 #define WM8400_RL12RO_MASK 0x0008 /* RL12RO */
866 #define WM8400_RL12RO_SHIFT 879 #define WM8400_RL12RO_SHIFT 3 /* RL12RO */
867 #define WM8400_RL12RO_WIDTH 880 #define WM8400_RL12RO_WIDTH 1 /* RL12RO */
868 #define WM8400_RR12RO 881 #define WM8400_RR12RO 0x0004 /* RR12RO */
869 #define WM8400_RR12RO_MASK 882 #define WM8400_RR12RO_MASK 0x0004 /* RR12RO */
870 #define WM8400_RR12RO_SHIFT 883 #define WM8400_RR12RO_SHIFT 2 /* RR12RO */
871 #define WM8400_RR12RO_WIDTH 884 #define WM8400_RR12RO_WIDTH 1 /* RR12RO */
872 #define WM8400_RDRO 885 #define WM8400_RDRO 0x0001 /* RDRO */
873 #define WM8400_RDRO_MASK 886 #define WM8400_RDRO_MASK 0x0001 /* RDRO */
874 #define WM8400_RDRO_SHIFT 887 #define WM8400_RDRO_SHIFT 0 /* RDRO */
875 #define WM8400_RDRO_WIDTH 888 #define WM8400_RDRO_WIDTH 1 /* RDRO */
876 889
877 /* 890 /*
878 * R47 (0x2F) - Output Mixer3 891 * R47 (0x2F) - Output Mixer3
879 */ 892 */
880 #define WM8400_LLI3LOVOL_MASK 893 #define WM8400_LLI3LOVOL_MASK 0x01C0 /* LLI3LOVOL - [8:6] */
881 #define WM8400_LLI3LOVOL_SHIFT 894 #define WM8400_LLI3LOVOL_SHIFT 6 /* LLI3LOVOL - [8:6] */
882 #define WM8400_LLI3LOVOL_WIDTH 895 #define WM8400_LLI3LOVOL_WIDTH 3 /* LLI3LOVOL - [8:6] */
883 #define WM8400_LR12LOVOL_MASK 896 #define WM8400_LR12LOVOL_MASK 0x0038 /* LR12LOVOL - [5:3] */
884 #define WM8400_LR12LOVOL_SHIFT 897 #define WM8400_LR12LOVOL_SHIFT 3 /* LR12LOVOL - [5:3] */
885 #define WM8400_LR12LOVOL_WIDTH 898 #define WM8400_LR12LOVOL_WIDTH 3 /* LR12LOVOL - [5:3] */
886 #define WM8400_LL12LOVOL_MASK 899 #define WM8400_LL12LOVOL_MASK 0x0007 /* LL12LOVOL - [2:0] */
887 #define WM8400_LL12LOVOL_SHIFT 900 #define WM8400_LL12LOVOL_SHIFT 0 /* LL12LOVOL - [2:0] */
888 #define WM8400_LL12LOVOL_WIDTH 901 #define WM8400_LL12LOVOL_WIDTH 3 /* LL12LOVOL - [2:0] */
889 902
890 /* 903 /*
891 * R48 (0x30) - Output Mixer4 904 * R48 (0x30) - Output Mixer4
892 */ 905 */
893 #define WM8400_RRI3ROVOL_MASK 906 #define WM8400_RRI3ROVOL_MASK 0x01C0 /* RRI3ROVOL - [8:6] */
894 #define WM8400_RRI3ROVOL_SHIFT 907 #define WM8400_RRI3ROVOL_SHIFT 6 /* RRI3ROVOL - [8:6] */
895 #define WM8400_RRI3ROVOL_WIDTH 908 #define WM8400_RRI3ROVOL_WIDTH 3 /* RRI3ROVOL - [8:6] */
896 #define WM8400_RL12ROVOL_MASK 909 #define WM8400_RL12ROVOL_MASK 0x0038 /* RL12ROVOL - [5:3] */
897 #define WM8400_RL12ROVOL_SHIFT 910 #define WM8400_RL12ROVOL_SHIFT 3 /* RL12ROVOL - [5:3] */
898 #define WM8400_RL12ROVOL_WIDTH 911 #define WM8400_RL12ROVOL_WIDTH 3 /* RL12ROVOL - [5:3] */
899 #define WM8400_RR12ROVOL_MASK 912 #define WM8400_RR12ROVOL_MASK 0x0007 /* RR12ROVOL - [2:0] */
900 #define WM8400_RR12ROVOL_SHIFT 913 #define WM8400_RR12ROVOL_SHIFT 0 /* RR12ROVOL - [2:0] */
901 #define WM8400_RR12ROVOL_WIDTH 914 #define WM8400_RR12ROVOL_WIDTH 3 /* RR12ROVOL - [2:0] */
902 915
903 /* 916 /*
904 * R49 (0x31) - Output Mixer5 917 * R49 (0x31) - Output Mixer5
905 */ 918 */
906 #define WM8400_LRI3LOVOL_MASK 919 #define WM8400_LRI3LOVOL_MASK 0x01C0 /* LRI3LOVOL - [8:6] */
907 #define WM8400_LRI3LOVOL_SHIFT 920 #define WM8400_LRI3LOVOL_SHIFT 6 /* LRI3LOVOL - [8:6] */
908 #define WM8400_LRI3LOVOL_WIDTH 921 #define WM8400_LRI3LOVOL_WIDTH 3 /* LRI3LOVOL - [8:6] */
909 #define WM8400_LRBLOVOL_MASK 922 #define WM8400_LRBLOVOL_MASK 0x0038 /* LRBLOVOL - [5:3] */
910 #define WM8400_LRBLOVOL_SHIFT 923 #define WM8400_LRBLOVOL_SHIFT 3 /* LRBLOVOL - [5:3] */
911 #define WM8400_LRBLOVOL_WIDTH 924 #define WM8400_LRBLOVOL_WIDTH 3 /* LRBLOVOL - [5:3] */
912 #define WM8400_LLBLOVOL_MASK 925 #define WM8400_LLBLOVOL_MASK 0x0007 /* LLBLOVOL - [2:0] */
913 #define WM8400_LLBLOVOL_SHIFT 926 #define WM8400_LLBLOVOL_SHIFT 0 /* LLBLOVOL - [2:0] */
914 #define WM8400_LLBLOVOL_WIDTH 927 #define WM8400_LLBLOVOL_WIDTH 3 /* LLBLOVOL - [2:0] */
915 928
916 /* 929 /*
917 * R50 (0x32) - Output Mixer6 930 * R50 (0x32) - Output Mixer6
918 */ 931 */
919 #define WM8400_RLI3ROVOL_MASK 932 #define WM8400_RLI3ROVOL_MASK 0x01C0 /* RLI3ROVOL - [8:6] */
920 #define WM8400_RLI3ROVOL_SHIFT 933 #define WM8400_RLI3ROVOL_SHIFT 6 /* RLI3ROVOL - [8:6] */
921 #define WM8400_RLI3ROVOL_WIDTH 934 #define WM8400_RLI3ROVOL_WIDTH 3 /* RLI3ROVOL - [8:6] */
922 #define WM8400_RLBROVOL_MASK 935 #define WM8400_RLBROVOL_MASK 0x0038 /* RLBROVOL - [5:3] */
923 #define WM8400_RLBROVOL_SHIFT 936 #define WM8400_RLBROVOL_SHIFT 3 /* RLBROVOL - [5:3] */
924 #define WM8400_RLBROVOL_WIDTH 937 #define WM8400_RLBROVOL_WIDTH 3 /* RLBROVOL - [5:3] */
925 #define WM8400_RRBROVOL_MASK 938 #define WM8400_RRBROVOL_MASK 0x0007 /* RRBROVOL - [2:0] */
926 #define WM8400_RRBROVOL_SHIFT 939 #define WM8400_RRBROVOL_SHIFT 0 /* RRBROVOL - [2:0] */
927 #define WM8400_RRBROVOL_WIDTH 940 #define WM8400_RRBROVOL_WIDTH 3 /* RRBROVOL - [2:0] */
928 941
929 /* 942 /*
930 * R51 (0x33) - Out3/4 Mixer 943 * R51 (0x33) - Out3/4 Mixer
931 */ 944 */
932 #define WM8400_VSEL_MASK 945 #define WM8400_VSEL_MASK 0x0180 /* VSEL - [8:7] */
933 #define WM8400_VSEL_SHIFT 946 #define WM8400_VSEL_SHIFT 7 /* VSEL - [8:7] */
934 #define WM8400_VSEL_WIDTH 947 #define WM8400_VSEL_WIDTH 2 /* VSEL - [8:7] */
935 #define WM8400_LI4O3 948 #define WM8400_LI4O3 0x0020 /* LI4O3 */
936 #define WM8400_LI4O3_MASK 949 #define WM8400_LI4O3_MASK 0x0020 /* LI4O3 */
937 #define WM8400_LI4O3_SHIFT 950 #define WM8400_LI4O3_SHIFT 5 /* LI4O3 */
938 #define WM8400_LI4O3_WIDTH 951 #define WM8400_LI4O3_WIDTH 1 /* LI4O3 */
939 #define WM8400_LPGAO3 952 #define WM8400_LPGAO3 0x0010 /* LPGAO3 */
940 #define WM8400_LPGAO3_MASK 953 #define WM8400_LPGAO3_MASK 0x0010 /* LPGAO3 */
941 #define WM8400_LPGAO3_SHIFT 954 #define WM8400_LPGAO3_SHIFT 4 /* LPGAO3 */
942 #define WM8400_LPGAO3_WIDTH 955 #define WM8400_LPGAO3_WIDTH 1 /* LPGAO3 */
943 #define WM8400_RI4O4 956 #define WM8400_RI4O4 0x0002 /* RI4O4 */
944 #define WM8400_RI4O4_MASK 957 #define WM8400_RI4O4_MASK 0x0002 /* RI4O4 */
945 #define WM8400_RI4O4_SHIFT 958 #define WM8400_RI4O4_SHIFT 1 /* RI4O4 */
946 #define WM8400_RI4O4_WIDTH 959 #define WM8400_RI4O4_WIDTH 1 /* RI4O4 */
947 #define WM8400_RPGAO4 960 #define WM8400_RPGAO4 0x0001 /* RPGAO4 */
948 #define WM8400_RPGAO4_MASK 961 #define WM8400_RPGAO4_MASK 0x0001 /* RPGAO4 */
949 #define WM8400_RPGAO4_SHIFT 962 #define WM8400_RPGAO4_SHIFT 0 /* RPGAO4 */
950 #define WM8400_RPGAO4_WIDTH 963 #define WM8400_RPGAO4_WIDTH 1 /* RPGAO4 */
951 964
952 /* 965 /*
953 * R52 (0x34) - Line Mixer1 966 * R52 (0x34) - Line Mixer1
954 */ 967 */
955 #define WM8400_LLOPGALON 968 #define WM8400_LLOPGALON 0x0040 /* LLOPGALON */
956 #define WM8400_LLOPGALON_MASK 969 #define WM8400_LLOPGALON_MASK 0x0040 /* LLOPGALON */
957 #define WM8400_LLOPGALON_SHIFT 970 #define WM8400_LLOPGALON_SHIFT 6 /* LLOPGALON */
958 #define WM8400_LLOPGALON_WIDTH 971 #define WM8400_LLOPGALON_WIDTH 1 /* LLOPGALON */
959 #define WM8400_LROPGALON 972 #define WM8400_LROPGALON 0x0020 /* LROPGALON */
960 #define WM8400_LROPGALON_MASK 973 #define WM8400_LROPGALON_MASK 0x0020 /* LROPGALON */
961 #define WM8400_LROPGALON_SHIFT 974 #define WM8400_LROPGALON_SHIFT 5 /* LROPGALON */
962 #define WM8400_LROPGALON_WIDTH 975 #define WM8400_LROPGALON_WIDTH 1 /* LROPGALON */
963 #define WM8400_LOPLON 976 #define WM8400_LOPLON 0x0010 /* LOPLON */
964 #define WM8400_LOPLON_MASK 977 #define WM8400_LOPLON_MASK 0x0010 /* LOPLON */
965 #define WM8400_LOPLON_SHIFT 978 #define WM8400_LOPLON_SHIFT 4 /* LOPLON */
966 #define WM8400_LOPLON_WIDTH 979 #define WM8400_LOPLON_WIDTH 1 /* LOPLON */
967 #define WM8400_LR12LOP 980 #define WM8400_LR12LOP 0x0004 /* LR12LOP */
968 #define WM8400_LR12LOP_MASK 981 #define WM8400_LR12LOP_MASK 0x0004 /* LR12LOP */
969 #define WM8400_LR12LOP_SHIFT 982 #define WM8400_LR12LOP_SHIFT 2 /* LR12LOP */
970 #define WM8400_LR12LOP_WIDTH 983 #define WM8400_LR12LOP_WIDTH 1 /* LR12LOP */
971 #define WM8400_LL12LOP 984 #define WM8400_LL12LOP 0x0002 /* LL12LOP */
972 #define WM8400_LL12LOP_MASK 985 #define WM8400_LL12LOP_MASK 0x0002 /* LL12LOP */
973 #define WM8400_LL12LOP_SHIFT 986 #define WM8400_LL12LOP_SHIFT 1 /* LL12LOP */
974 #define WM8400_LL12LOP_WIDTH 987 #define WM8400_LL12LOP_WIDTH 1 /* LL12LOP */
975 #define WM8400_LLOPGALOP 988 #define WM8400_LLOPGALOP 0x0001 /* LLOPGALOP */
976 #define WM8400_LLOPGALOP_MASK 989 #define WM8400_LLOPGALOP_MASK 0x0001 /* LLOPGALOP */
977 #define WM8400_LLOPGALOP_SHIFT 990 #define WM8400_LLOPGALOP_SHIFT 0 /* LLOPGALOP */
978 #define WM8400_LLOPGALOP_WIDTH 991 #define WM8400_LLOPGALOP_WIDTH 1 /* LLOPGALOP */
979 992
980 /* 993 /*
981 * R53 (0x35) - Line Mixer2 994 * R53 (0x35) - Line Mixer2
982 */ 995 */
983 #define WM8400_RROPGARON 996 #define WM8400_RROPGARON 0x0040 /* RROPGARON */
984 #define WM8400_RROPGARON_MASK 997 #define WM8400_RROPGARON_MASK 0x0040 /* RROPGARON */
985 #define WM8400_RROPGARON_SHIFT 998 #define WM8400_RROPGARON_SHIFT 6 /* RROPGARON */
986 #define WM8400_RROPGARON_WIDTH 999 #define WM8400_RROPGARON_WIDTH 1 /* RROPGARON */
987 #define WM8400_RLOPGARON 1000 #define WM8400_RLOPGARON 0x0020 /* RLOPGARON */
988 #define WM8400_RLOPGARON_MASK 1001 #define WM8400_RLOPGARON_MASK 0x0020 /* RLOPGARON */
989 #define WM8400_RLOPGARON_SHIFT 1002 #define WM8400_RLOPGARON_SHIFT 5 /* RLOPGARON */
990 #define WM8400_RLOPGARON_WIDTH 1003 #define WM8400_RLOPGARON_WIDTH 1 /* RLOPGARON */
991 #define WM8400_ROPRON 1004 #define WM8400_ROPRON 0x0010 /* ROPRON */
992 #define WM8400_ROPRON_MASK 1005 #define WM8400_ROPRON_MASK 0x0010 /* ROPRON */
993 #define WM8400_ROPRON_SHIFT 1006 #define WM8400_ROPRON_SHIFT 4 /* ROPRON */
994 #define WM8400_ROPRON_WIDTH 1007 #define WM8400_ROPRON_WIDTH 1 /* ROPRON */
995 #define WM8400_RL12ROP 1008 #define WM8400_RL12ROP 0x0004 /* RL12ROP */
996 #define WM8400_RL12ROP_MASK 1009 #define WM8400_RL12ROP_MASK 0x0004 /* RL12ROP */
997 #define WM8400_RL12ROP_SHIFT 1010 #define WM8400_RL12ROP_SHIFT 2 /* RL12ROP */
998 #define WM8400_RL12ROP_WIDTH 1011 #define WM8400_RL12ROP_WIDTH 1 /* RL12ROP */
999 #define WM8400_RR12ROP 1012 #define WM8400_RR12ROP 0x0002 /* RR12ROP */
1000 #define WM8400_RR12ROP_MASK 1013 #define WM8400_RR12ROP_MASK 0x0002 /* RR12ROP */
1001 #define WM8400_RR12ROP_SHIFT 1014 #define WM8400_RR12ROP_SHIFT 1 /* RR12ROP */
1002 #define WM8400_RR12ROP_WIDTH 1015 #define WM8400_RR12ROP_WIDTH 1 /* RR12ROP */
1003 #define WM8400_RROPGAROP 1016 #define WM8400_RROPGAROP 0x0001 /* RROPGAROP */
1004 #define WM8400_RROPGAROP_MASK 1017 #define WM8400_RROPGAROP_MASK 0x0001 /* RROPGAROP */
1005 #define WM8400_RROPGAROP_SHIFT 1018 #define WM8400_RROPGAROP_SHIFT 0 /* RROPGAROP */
1006 #define WM8400_RROPGAROP_WIDTH 1019 #define WM8400_RROPGAROP_WIDTH 1 /* RROPGAROP */
1007 1020
1008 /* 1021 /*
1009 * R54 (0x36) - Speaker Mixer 1022 * R54 (0x36) - Speaker Mixer
1010 */ 1023 */
1011 #define WM8400_LB2SPK 1024 #define WM8400_LB2SPK 0x0080 /* LB2SPK */
1012 #define WM8400_LB2SPK_MASK 1025 #define WM8400_LB2SPK_MASK 0x0080 /* LB2SPK */
1013 #define WM8400_LB2SPK_SHIFT 1026 #define WM8400_LB2SPK_SHIFT 7 /* LB2SPK */
1014 #define WM8400_LB2SPK_WIDTH 1027 #define WM8400_LB2SPK_WIDTH 1 /* LB2SPK */
1015 #define WM8400_RB2SPK 1028 #define WM8400_RB2SPK 0x0040 /* RB2SPK */
1016 #define WM8400_RB2SPK_MASK 1029 #define WM8400_RB2SPK_MASK 0x0040 /* RB2SPK */
1017 #define WM8400_RB2SPK_SHIFT 1030 #define WM8400_RB2SPK_SHIFT 6 /* RB2SPK */
1018 #define WM8400_RB2SPK_WIDTH 1031 #define WM8400_RB2SPK_WIDTH 1 /* RB2SPK */
1019 #define WM8400_LI2SPK 1032 #define WM8400_LI2SPK 0x0020 /* LI2SPK */
1020 #define WM8400_LI2SPK_MASK 1033 #define WM8400_LI2SPK_MASK 0x0020 /* LI2SPK */
1021 #define WM8400_LI2SPK_SHIFT 1034 #define WM8400_LI2SPK_SHIFT 5 /* LI2SPK */
1022 #define WM8400_LI2SPK_WIDTH 1035 #define WM8400_LI2SPK_WIDTH 1 /* LI2SPK */
1023 #define WM8400_RI2SPK 1036 #define WM8400_RI2SPK 0x0010 /* RI2SPK */
1024 #define WM8400_RI2SPK_MASK 1037 #define WM8400_RI2SPK_MASK 0x0010 /* RI2SPK */
1025 #define WM8400_RI2SPK_SHIFT 1038 #define WM8400_RI2SPK_SHIFT 4 /* RI2SPK */
1026 #define WM8400_RI2SPK_WIDTH 1039 #define WM8400_RI2SPK_WIDTH 1 /* RI2SPK */
1027 #define WM8400_LOPGASPK 1040 #define WM8400_LOPGASPK 0x0008 /* LOPGASPK */
1028 #define WM8400_LOPGASPK_MASK 1041 #define WM8400_LOPGASPK_MASK 0x0008 /* LOPGASPK */
1029 #define WM8400_LOPGASPK_SHIFT 1042 #define WM8400_LOPGASPK_SHIFT 3 /* LOPGASPK */
1030 #define WM8400_LOPGASPK_WIDTH 1043 #define WM8400_LOPGASPK_WIDTH 1 /* LOPGASPK */
1031 #define WM8400_ROPGASPK 1044 #define WM8400_ROPGASPK 0x0004 /* ROPGASPK */
1032 #define WM8400_ROPGASPK_MASK 1045 #define WM8400_ROPGASPK_MASK 0x0004 /* ROPGASPK */
1033 #define WM8400_ROPGASPK_SHIFT 1046 #define WM8400_ROPGASPK_SHIFT 2 /* ROPGASPK */
1034 #define WM8400_ROPGASPK_WIDTH 1047 #define WM8400_ROPGASPK_WIDTH 1 /* ROPGASPK */
1035 #define WM8400_LDSPK 1048 #define WM8400_LDSPK 0x0002 /* LDSPK */
1036 #define WM8400_LDSPK_MASK 1049 #define WM8400_LDSPK_MASK 0x0002 /* LDSPK */
1037 #define WM8400_LDSPK_SHIFT 1050 #define WM8400_LDSPK_SHIFT 1 /* LDSPK */
1038 #define WM8400_LDSPK_WIDTH 1051 #define WM8400_LDSPK_WIDTH 1 /* LDSPK */
1039 #define WM8400_RDSPK 1052 #define WM8400_RDSPK 0x0001 /* RDSPK */
1040 #define WM8400_RDSPK_MASK 1053 #define WM8400_RDSPK_MASK 0x0001 /* RDSPK */
1041 #define WM8400_RDSPK_SHIFT 1054 #define WM8400_RDSPK_SHIFT 0 /* RDSPK */
1042 #define WM8400_RDSPK_WIDTH 1055 #define WM8400_RDSPK_WIDTH 1 /* RDSPK */
1043 1056
1044 /* 1057 /*
1045 * R55 (0x37) - Additional Control 1058 * R55 (0x37) - Additional Control
1046 */ 1059 */
1047 #define WM8400_VROI 1060 #define WM8400_VROI 0x0001 /* VROI */
1048 #define WM8400_VROI_MASK 1061 #define WM8400_VROI_MASK 0x0001 /* VROI */
1049 #define WM8400_VROI_SHIFT 1062 #define WM8400_VROI_SHIFT 0 /* VROI */
1050 #define WM8400_VROI_WIDTH 1063 #define WM8400_VROI_WIDTH 1 /* VROI */
1051 1064
1052 /* 1065 /*
1053 * R56 (0x38) - AntiPOP1 1066 * R56 (0x38) - AntiPOP1
1054 */ 1067 */
1055 #define WM8400_DIS_LLINE 1068 #define WM8400_DIS_LLINE 0x0020 /* DIS_LLINE */
1056 #define WM8400_DIS_LLINE_MASK 1069 #define WM8400_DIS_LLINE_MASK 0x0020 /* DIS_LLINE */
1057 #define WM8400_DIS_LLINE_SHIFT 1070 #define WM8400_DIS_LLINE_SHIFT 5 /* DIS_LLINE */
1058 #define WM8400_DIS_LLINE_WIDTH 1071 #define WM8400_DIS_LLINE_WIDTH 1 /* DIS_LLINE */
1059 #define WM8400_DIS_RLINE 1072 #define WM8400_DIS_RLINE 0x0010 /* DIS_RLINE */
1060 #define WM8400_DIS_RLINE_MASK 1073 #define WM8400_DIS_RLINE_MASK 0x0010 /* DIS_RLINE */
1061 #define WM8400_DIS_RLINE_SHIFT 1074 #define WM8400_DIS_RLINE_SHIFT 4 /* DIS_RLINE */
1062 #define WM8400_DIS_RLINE_WIDTH 1075 #define WM8400_DIS_RLINE_WIDTH 1 /* DIS_RLINE */
1063 #define WM8400_DIS_OUT3 1076 #define WM8400_DIS_OUT3 0x0008 /* DIS_OUT3 */
1064 #define WM8400_DIS_OUT3_MASK 1077 #define WM8400_DIS_OUT3_MASK 0x0008 /* DIS_OUT3 */
1065 #define WM8400_DIS_OUT3_SHIFT 1078 #define WM8400_DIS_OUT3_SHIFT 3 /* DIS_OUT3 */
1066 #define WM8400_DIS_OUT3_WIDTH 1079 #define WM8400_DIS_OUT3_WIDTH 1 /* DIS_OUT3 */
1067 #define WM8400_DIS_OUT4 1080 #define WM8400_DIS_OUT4 0x0004 /* DIS_OUT4 */
1068 #define WM8400_DIS_OUT4_MASK 1081 #define WM8400_DIS_OUT4_MASK 0x0004 /* DIS_OUT4 */
1069 #define WM8400_DIS_OUT4_SHIFT 1082 #define WM8400_DIS_OUT4_SHIFT 2 /* DIS_OUT4 */
1070 #define WM8400_DIS_OUT4_WIDTH 1083 #define WM8400_DIS_OUT4_WIDTH 1 /* DIS_OUT4 */
1071 #define WM8400_DIS_LOUT 1084 #define WM8400_DIS_LOUT 0x0002 /* DIS_LOUT */
1072 #define WM8400_DIS_LOUT_MASK 1085 #define WM8400_DIS_LOUT_MASK 0x0002 /* DIS_LOUT */
1073 #define WM8400_DIS_LOUT_SHIFT 1086 #define WM8400_DIS_LOUT_SHIFT 1 /* DIS_LOUT */
1074 #define WM8400_DIS_LOUT_WIDTH 1087 #define WM8400_DIS_LOUT_WIDTH 1 /* DIS_LOUT */
1075 #define WM8400_DIS_ROUT 1088 #define WM8400_DIS_ROUT 0x0001 /* DIS_ROUT */
1076 #define WM8400_DIS_ROUT_MASK 1089 #define WM8400_DIS_ROUT_MASK 0x0001 /* DIS_ROUT */
1077 #define WM8400_DIS_ROUT_SHIFT 1090 #define WM8400_DIS_ROUT_SHIFT 0 /* DIS_ROUT */
1078 #define WM8400_DIS_ROUT_WIDTH 1091 #define WM8400_DIS_ROUT_WIDTH 1 /* DIS_ROUT */
1079 1092
1080 /* 1093 /*
1081 * R57 (0x39) - AntiPOP2 1094 * R57 (0x39) - AntiPOP2
1082 */ 1095 */
1083 #define WM8400_SOFTST 1096 #define WM8400_SOFTST 0x0040 /* SOFTST */
1084 #define WM8400_SOFTST_MASK 1097 #define WM8400_SOFTST_MASK 0x0040 /* SOFTST */
1085 #define WM8400_SOFTST_SHIFT 1098 #define WM8400_SOFTST_SHIFT 6 /* SOFTST */
1086 #define WM8400_SOFTST_WIDTH 1099 #define WM8400_SOFTST_WIDTH 1 /* SOFTST */
1087 #define WM8400_BUFIOEN 1100 #define WM8400_BUFIOEN 0x0008 /* BUFIOEN */
1088 #define WM8400_BUFIOEN_MASK 1101 #define WM8400_BUFIOEN_MASK 0x0008 /* BUFIOEN */
1089 #define WM8400_BUFIOEN_SHIFT 1102 #define WM8400_BUFIOEN_SHIFT 3 /* BUFIOEN */
1090 #define WM8400_BUFIOEN_WIDTH 1103 #define WM8400_BUFIOEN_WIDTH 1 /* BUFIOEN */
1091 #define WM8400_BUFDCOPEN 1104 #define WM8400_BUFDCOPEN 0x0004 /* BUFDCOPEN */
1092 #define WM8400_BUFDCOPEN_MASK 1105 #define WM8400_BUFDCOPEN_MASK 0x0004 /* BUFDCOPEN */
1093 #define WM8400_BUFDCOPEN_SHIFT 1106 #define WM8400_BUFDCOPEN_SHIFT 2 /* BUFDCOPEN */
1094 #define WM8400_BUFDCOPEN_WIDTH 1107 #define WM8400_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */
1095 #define WM8400_POBCTRL 1108 #define WM8400_POBCTRL 0x0002 /* POBCTRL */
1096 #define WM8400_POBCTRL_MASK 1109 #define WM8400_POBCTRL_MASK 0x0002 /* POBCTRL */
1097 #define WM8400_POBCTRL_SHIFT 1110 #define WM8400_POBCTRL_SHIFT 1 /* POBCTRL */
1098 #define WM8400_POBCTRL_WIDTH 1111 #define WM8400_POBCTRL_WIDTH 1 /* POBCTRL */
1099 #define WM8400_VMIDTOG 1112 #define WM8400_VMIDTOG 0x0001 /* VMIDTOG */
1100 #define WM8400_VMIDTOG_MASK 1113 #define WM8400_VMIDTOG_MASK 0x0001 /* VMIDTOG */
1101 #define WM8400_VMIDTOG_SHIFT 1114 #define WM8400_VMIDTOG_SHIFT 0 /* VMIDTOG */
1102 #define WM8400_VMIDTOG_WIDTH 1115 #define WM8400_VMIDTOG_WIDTH 1 /* VMIDTOG */
1103 1116
1104 /* 1117 /*
1105 * R58 (0x3A) - MICBIAS 1118 * R58 (0x3A) - MICBIAS
1106 */ 1119 */
1107 #define WM8400_MCDSCTH_MASK 1120 #define WM8400_MCDSCTH_MASK 0x00C0 /* MCDSCTH - [7:6] */
1108 #define WM8400_MCDSCTH_SHIFT 1121 #define WM8400_MCDSCTH_SHIFT 6 /* MCDSCTH - [7:6] */
1109 #define WM8400_MCDSCTH_WIDTH 1122 #define WM8400_MCDSCTH_WIDTH 2 /* MCDSCTH - [7:6] */
1110 #define WM8400_MCDTHR_MASK 1123 #define WM8400_MCDTHR_MASK 0x0038 /* MCDTHR - [5:3] */
1111 #define WM8400_MCDTHR_SHIFT 1124 #define WM8400_MCDTHR_SHIFT 3 /* MCDTHR - [5:3] */
1112 #define WM8400_MCDTHR_WIDTH 1125 #define WM8400_MCDTHR_WIDTH 3 /* MCDTHR - [5:3] */
1113 #define WM8400_MCD 1126 #define WM8400_MCD 0x0004 /* MCD */
1114 #define WM8400_MCD_MASK 1127 #define WM8400_MCD_MASK 0x0004 /* MCD */
1115 #define WM8400_MCD_SHIFT 1128 #define WM8400_MCD_SHIFT 2 /* MCD */
1116 #define WM8400_MCD_WIDTH 1129 #define WM8400_MCD_WIDTH 1 /* MCD */
1117 #define WM8400_MBSEL 1130 #define WM8400_MBSEL 0x0001 /* MBSEL */
1118 #define WM8400_MBSEL_MASK 1131 #define WM8400_MBSEL_MASK 0x0001 /* MBSEL */
1119 #define WM8400_MBSEL_SHIFT 1132 #define WM8400_MBSEL_SHIFT 0 /* MBSEL */
1120 #define WM8400_MBSEL_WIDTH 1133 #define WM8400_MBSEL_WIDTH 1 /* MBSEL */
1121 1134
1122 /* 1135 /*
1123 * R60 (0x3C) - FLL Control 1 1136 * R60 (0x3C) - FLL Control 1
1124 */ 1137 */
1125 #define WM8400_FLL_REF_FREQ 1138 #define WM8400_FLL_REF_FREQ 0x1000 /* FLL_REF_FREQ */
1126 #define WM8400_FLL_REF_FREQ_MASK 1139 #define WM8400_FLL_REF_FREQ_MASK 0x1000 /* FLL_REF_FREQ */
1127 #define WM8400_FLL_REF_FREQ_SHIFT 1140 #define WM8400_FLL_REF_FREQ_SHIFT 12 /* FLL_REF_FREQ */
1128 #define WM8400_FLL_REF_FREQ_WIDTH 1141 #define WM8400_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */
1129 #define WM8400_FLL_CLK_SRC_MASK 1142 #define WM8400_FLL_CLK_SRC_MASK 0x0C00 /* FLL_CLK_SRC - [11:10] */
1130 #define WM8400_FLL_CLK_SRC_SHIFT 1143 #define WM8400_FLL_CLK_SRC_SHIFT 10 /* FLL_CLK_SRC - [11:10] */
1131 #define WM8400_FLL_CLK_SRC_WIDTH 1144 #define WM8400_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [11:10] */
1132 #define WM8400_FLL_FRAC 1145 #define WM8400_FLL_FRAC 0x0200 /* FLL_FRAC */
1133 #define WM8400_FLL_FRAC_MASK 1146 #define WM8400_FLL_FRAC_MASK 0x0200 /* FLL_FRAC */
1134 #define WM8400_FLL_FRAC_SHIFT 1147 #define WM8400_FLL_FRAC_SHIFT 9 /* FLL_FRAC */
1135 #define WM8400_FLL_FRAC_WIDTH 1148 #define WM8400_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
1136 #define WM8400_FLL_OSC_ENA 1149 #define WM8400_FLL_OSC_ENA 0x0100 /* FLL_OSC_ENA */
1137 #define WM8400_FLL_OSC_ENA_MASK 1150 #define WM8400_FLL_OSC_ENA_MASK 0x0100 /* FLL_OSC_ENA */
1138 #define WM8400_FLL_OSC_ENA_SHIFT 1151 #define WM8400_FLL_OSC_ENA_SHIFT 8 /* FLL_OSC_ENA */
1139 #define WM8400_FLL_OSC_ENA_WIDTH 1152 #define WM8400_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
1140 #define WM8400_FLL_CTRL_RATE_MASK 1153 #define WM8400_FLL_CTRL_RATE_MASK 0x00E0 /* FLL_CTRL_RATE - [7:5] */
1141 #define WM8400_FLL_CTRL_RATE_SHIFT 1154 #define WM8400_FLL_CTRL_RATE_SHIFT 5 /* FLL_CTRL_RATE - [7:5] */
1142 #define WM8400_FLL_CTRL_RATE_WIDTH 1155 #define WM8400_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [7:5] */
1143 #define WM8400_FLL_FRATIO_MASK 1156 #define WM8400_FLL_FRATIO_MASK 0x001F /* FLL_FRATIO - [4:0] */
1144 #define WM8400_FLL_FRATIO_SHIFT 1157 #define WM8400_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [4:0] */
1145 #define WM8400_FLL_FRATIO_WIDTH 1158 #define WM8400_FLL_FRATIO_WIDTH 5 /* FLL_FRATIO - [4:0] */
1146 1159
1147 /* 1160 /*
1148 * R61 (0x3D) - FLL Control 2 1161 * R61 (0x3D) - FLL Control 2
1149 */ 1162 */
1150 #define WM8400_FLL_K_MASK 1163 #define WM8400_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
1151 #define WM8400_FLL_K_SHIFT 1164 #define WM8400_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
1152 #define WM8400_FLL_K_WIDTH 1165 #define WM8400_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
1153 1166
1154 /* 1167 /*
1155 * R62 (0x3E) - FLL Control 3 1168 * R62 (0x3E) - FLL Control 3
1156 */ 1169 */
1157 #define WM8400_FLL_N_MASK 1170 #define WM8400_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */
1158 #define WM8400_FLL_N_SHIFT 1171 #define WM8400_FLL_N_SHIFT 0 /* FLL_N - [9:0] */
1159 #define WM8400_FLL_N_WIDTH 1172 #define WM8400_FLL_N_WIDTH 10 /* FLL_N - [9:0] */
1160 1173
1161 /* 1174 /*
1162 * R63 (0x3F) - FLL Control 4 1175 * R63 (0x3F) - FLL Control 4
1163 */ 1176 */
1164 #define WM8400_FLL_TRK_GAIN_MASK 1177 #define WM8400_FLL_TRK_GAIN_MASK 0x0078 /* FLL_TRK_GAIN - [6:3] */
1165 #define WM8400_FLL_TRK_GAIN_SHIFT 1178 #define WM8400_FLL_TRK_GAIN_SHIFT 3 /* FLL_TRK_GAIN - [6:3] */
1166 #define WM8400_FLL_TRK_GAIN_WIDTH 1179 #define WM8400_FLL_TRK_GAIN_WIDTH 4 /* FLL_TRK_GAIN - [6:3] */
1167 #define WM8400_FLL_OUTDIV_MASK 1180 #define WM8400_FLL_OUTDIV_MASK 0x0007 /* FLL_OUTDIV - [2:0] */
1168 #define WM8400_FLL_OUTDIV_SHIFT 1181 #define WM8400_FLL_OUTDIV_SHIFT 0 /* FLL_OUTDIV - [2:0] */
1169 #define WM8400_FLL_OUTDIV_WIDTH 1182 #define WM8400_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [2:0] */
1170 1183
1171 struct wm8400; 1184 struct wm8400;
1172 void wm8400_reset_codec_reg_cache(struct wm84 1185 void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400);
1173 1186
1174 #endif 1187 #endif
1175 1188
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