1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1
2 /*
3 * wm8400 private definitions.
4 *
5 * Copyright 2008 Wolfson Microelectronics plc
6 */
7
8 #ifndef __LINUX_MFD_WM8400_PRIV_H
9 #define __LINUX_MFD_WM8400_PRIV_H
10
11 #include <linux/mfd/wm8400.h>
12 #include <linux/mutex.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15
16 #define WM8400_REGISTER_COUNT 0x55
17
18 struct wm8400 {
19 struct device *dev;
20 struct regmap *regmap;
21
22 struct platform_device regulators[6];
23 };
24
25 /*
26 * Register values.
27 */
28 #define WM8400_RESET_ID
29 #define WM8400_ID
30 #define WM8400_POWER_MANAGEMENT_1
31 #define WM8400_POWER_MANAGEMENT_2
32 #define WM8400_POWER_MANAGEMENT_3
33 #define WM8400_AUDIO_INTERFACE_1
34 #define WM8400_AUDIO_INTERFACE_2
35 #define WM8400_CLOCKING_1
36 #define WM8400_CLOCKING_2
37 #define WM8400_AUDIO_INTERFACE_3
38 #define WM8400_AUDIO_INTERFACE_4
39 #define WM8400_DAC_CTRL
40 #define WM8400_LEFT_DAC_DIGITAL_VOLUME
41 #define WM8400_RIGHT_DAC_DIGITAL_VOLUME
42 #define WM8400_DIGITAL_SIDE_TONE
43 #define WM8400_ADC_CTRL
44 #define WM8400_LEFT_ADC_DIGITAL_VOLUME
45 #define WM8400_RIGHT_ADC_DIGITAL_VOLUME
46 #define WM8400_GPIO_CTRL_1
47 #define WM8400_GPIO1_GPIO2
48 #define WM8400_GPIO3_GPIO4
49 #define WM8400_GPIO5_GPIO6
50 #define WM8400_GPIOCTRL_2
51 #define WM8400_GPIO_POL
52 #define WM8400_LEFT_LINE_INPUT_1_2_VOLUME
53 #define WM8400_LEFT_LINE_INPUT_3_4_VOLUME
54 #define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME
55 #define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME
56 #define WM8400_LEFT_OUTPUT_VOLUME
57 #define WM8400_RIGHT_OUTPUT_VOLUME
58 #define WM8400_LINE_OUTPUTS_VOLUME
59 #define WM8400_OUT3_4_VOLUME
60 #define WM8400_LEFT_OPGA_VOLUME
61 #define WM8400_RIGHT_OPGA_VOLUME
62 #define WM8400_SPEAKER_VOLUME
63 #define WM8400_CLASSD1
64 #define WM8400_CLASSD3
65 #define WM8400_INPUT_MIXER1
66 #define WM8400_INPUT_MIXER2
67 #define WM8400_INPUT_MIXER3
68 #define WM8400_INPUT_MIXER4
69 #define WM8400_INPUT_MIXER5
70 #define WM8400_INPUT_MIXER6
71 #define WM8400_OUTPUT_MIXER1
72 #define WM8400_OUTPUT_MIXER2
73 #define WM8400_OUTPUT_MIXER3
74 #define WM8400_OUTPUT_MIXER4
75 #define WM8400_OUTPUT_MIXER5
76 #define WM8400_OUTPUT_MIXER6
77 #define WM8400_OUT3_4_MIXER
78 #define WM8400_LINE_MIXER1
79 #define WM8400_LINE_MIXER2
80 #define WM8400_SPEAKER_MIXER
81 #define WM8400_ADDITIONAL_CONTROL
82 #define WM8400_ANTIPOP1
83 #define WM8400_ANTIPOP2
84 #define WM8400_MICBIAS
85 #define WM8400_FLL_CONTROL_1
86 #define WM8400_FLL_CONTROL_2
87 #define WM8400_FLL_CONTROL_3
88 #define WM8400_FLL_CONTROL_4
89 #define WM8400_LDO1_CONTROL
90 #define WM8400_LDO2_CONTROL
91 #define WM8400_LDO3_CONTROL
92 #define WM8400_LDO4_CONTROL
93 #define WM8400_DCDC1_CONTROL_1
94 #define WM8400_DCDC1_CONTROL_2
95 #define WM8400_DCDC2_CONTROL_1
96 #define WM8400_DCDC2_CONTROL_2
97 #define WM8400_INTERFACE
98 #define WM8400_PM_GENERAL
99 #define WM8400_PM_SHUTDOWN_CONTROL
100 #define WM8400_INTERRUPT_STATUS_1
101 #define WM8400_INTERRUPT_STATUS_1_MASK
102 #define WM8400_INTERRUPT_LEVELS
103 #define WM8400_SHUTDOWN_REASON
104 #define WM8400_LINE_CIRCUITS
105
106 /*
107 * Field Definitions.
108 */
109
110 /*
111 * R0 (0x00) - Reset/ID
112 */
113 #define WM8400_SW_RESET_CHIP_ID_MASK
114 #define WM8400_SW_RESET_CHIP_ID_SHIFT
115 #define WM8400_SW_RESET_CHIP_ID_WIDTH
116
117 /*
118 * R1 (0x01) - ID
119 */
120 #define WM8400_CHIP_REV_MASK
121 #define WM8400_CHIP_REV_SHIFT
122 #define WM8400_CHIP_REV_WIDTH
123
124 /*
125 * R18 (0x12) - GPIO CTRL 1
126 */
127 #define WM8400_IRQ
128 #define WM8400_IRQ_MASK
129 #define WM8400_IRQ_SHIFT
130 #define WM8400_IRQ_WIDTH
131 #define WM8400_TEMPOK
132 #define WM8400_TEMPOK_MASK
133 #define WM8400_TEMPOK_SHIFT
134 #define WM8400_TEMPOK_WIDTH
135 #define WM8400_MIC1SHRT
136 #define WM8400_MIC1SHRT_MASK
137 #define WM8400_MIC1SHRT_SHIFT
138 #define WM8400_MIC1SHRT_WIDTH
139 #define WM8400_MIC1DET
140 #define WM8400_MIC1DET_MASK
141 #define WM8400_MIC1DET_SHIFT
142 #define WM8400_MIC1DET_WIDTH
143 #define WM8400_FLL_LCK
144 #define WM8400_FLL_LCK_MASK
145 #define WM8400_FLL_LCK_SHIFT
146 #define WM8400_FLL_LCK_WIDTH
147 #define WM8400_GPIO_STATUS_MASK
148 #define WM8400_GPIO_STATUS_SHIFT
149 #define WM8400_GPIO_STATUS_WIDTH
150
151 /*
152 * R19 (0x13) - GPIO1 & GPIO2
153 */
154 #define WM8400_GPIO2_DEB_ENA
155 #define WM8400_GPIO2_DEB_ENA_MASK
156 #define WM8400_GPIO2_DEB_ENA_SHIFT
157 #define WM8400_GPIO2_DEB_ENA_WIDTH
158 #define WM8400_GPIO2_IRQ_ENA
159 #define WM8400_GPIO2_IRQ_ENA_MASK
160 #define WM8400_GPIO2_IRQ_ENA_SHIFT
161 #define WM8400_GPIO2_IRQ_ENA_WIDTH
162 #define WM8400_GPIO2_PU
163 #define WM8400_GPIO2_PU_MASK
164 #define WM8400_GPIO2_PU_SHIFT
165 #define WM8400_GPIO2_PU_WIDTH
166 #define WM8400_GPIO2_PD
167 #define WM8400_GPIO2_PD_MASK
168 #define WM8400_GPIO2_PD_SHIFT
169 #define WM8400_GPIO2_PD_WIDTH
170 #define WM8400_GPIO2_SEL_MASK
171 #define WM8400_GPIO2_SEL_SHIFT
172 #define WM8400_GPIO2_SEL_WIDTH
173 #define WM8400_GPIO1_DEB_ENA
174 #define WM8400_GPIO1_DEB_ENA_MASK
175 #define WM8400_GPIO1_DEB_ENA_SHIFT
176 #define WM8400_GPIO1_DEB_ENA_WIDTH
177 #define WM8400_GPIO1_IRQ_ENA
178 #define WM8400_GPIO1_IRQ_ENA_MASK
179 #define WM8400_GPIO1_IRQ_ENA_SHIFT
180 #define WM8400_GPIO1_IRQ_ENA_WIDTH
181 #define WM8400_GPIO1_PU
182 #define WM8400_GPIO1_PU_MASK
183 #define WM8400_GPIO1_PU_SHIFT
184 #define WM8400_GPIO1_PU_WIDTH
185 #define WM8400_GPIO1_PD
186 #define WM8400_GPIO1_PD_MASK
187 #define WM8400_GPIO1_PD_SHIFT
188 #define WM8400_GPIO1_PD_WIDTH
189 #define WM8400_GPIO1_SEL_MASK
190 #define WM8400_GPIO1_SEL_SHIFT
191 #define WM8400_GPIO1_SEL_WIDTH
192
193 /*
194 * R20 (0x14) - GPIO3 & GPIO4
195 */
196 #define WM8400_GPIO4_DEB_ENA
197 #define WM8400_GPIO4_DEB_ENA_MASK
198 #define WM8400_GPIO4_DEB_ENA_SHIFT
199 #define WM8400_GPIO4_DEB_ENA_WIDTH
200 #define WM8400_GPIO4_IRQ_ENA
201 #define WM8400_GPIO4_IRQ_ENA_MASK
202 #define WM8400_GPIO4_IRQ_ENA_SHIFT
203 #define WM8400_GPIO4_IRQ_ENA_WIDTH
204 #define WM8400_GPIO4_PU
205 #define WM8400_GPIO4_PU_MASK
206 #define WM8400_GPIO4_PU_SHIFT
207 #define WM8400_GPIO4_PU_WIDTH
208 #define WM8400_GPIO4_PD
209 #define WM8400_GPIO4_PD_MASK
210 #define WM8400_GPIO4_PD_SHIFT
211 #define WM8400_GPIO4_PD_WIDTH
212 #define WM8400_GPIO4_SEL_MASK
213 #define WM8400_GPIO4_SEL_SHIFT
214 #define WM8400_GPIO4_SEL_WIDTH
215 #define WM8400_GPIO3_DEB_ENA
216 #define WM8400_GPIO3_DEB_ENA_MASK
217 #define WM8400_GPIO3_DEB_ENA_SHIFT
218 #define WM8400_GPIO3_DEB_ENA_WIDTH
219 #define WM8400_GPIO3_IRQ_ENA
220 #define WM8400_GPIO3_IRQ_ENA_MASK
221 #define WM8400_GPIO3_IRQ_ENA_SHIFT
222 #define WM8400_GPIO3_IRQ_ENA_WIDTH
223 #define WM8400_GPIO3_PU
224 #define WM8400_GPIO3_PU_MASK
225 #define WM8400_GPIO3_PU_SHIFT
226 #define WM8400_GPIO3_PU_WIDTH
227 #define WM8400_GPIO3_PD
228 #define WM8400_GPIO3_PD_MASK
229 #define WM8400_GPIO3_PD_SHIFT
230 #define WM8400_GPIO3_PD_WIDTH
231 #define WM8400_GPIO3_SEL_MASK
232 #define WM8400_GPIO3_SEL_SHIFT
233 #define WM8400_GPIO3_SEL_WIDTH
234
235 /*
236 * R21 (0x15) - GPIO5 & GPIO6
237 */
238 #define WM8400_GPIO6_DEB_ENA
239 #define WM8400_GPIO6_DEB_ENA_MASK
240 #define WM8400_GPIO6_DEB_ENA_SHIFT
241 #define WM8400_GPIO6_DEB_ENA_WIDTH
242 #define WM8400_GPIO6_IRQ_ENA
243 #define WM8400_GPIO6_IRQ_ENA_MASK
244 #define WM8400_GPIO6_IRQ_ENA_SHIFT
245 #define WM8400_GPIO6_IRQ_ENA_WIDTH
246 #define WM8400_GPIO6_PU
247 #define WM8400_GPIO6_PU_MASK
248 #define WM8400_GPIO6_PU_SHIFT
249 #define WM8400_GPIO6_PU_WIDTH
250 #define WM8400_GPIO6_PD
251 #define WM8400_GPIO6_PD_MASK
252 #define WM8400_GPIO6_PD_SHIFT
253 #define WM8400_GPIO6_PD_WIDTH
254 #define WM8400_GPIO6_SEL_MASK
255 #define WM8400_GPIO6_SEL_SHIFT
256 #define WM8400_GPIO6_SEL_WIDTH
257 #define WM8400_GPIO5_DEB_ENA
258 #define WM8400_GPIO5_DEB_ENA_MASK
259 #define WM8400_GPIO5_DEB_ENA_SHIFT
260 #define WM8400_GPIO5_DEB_ENA_WIDTH
261 #define WM8400_GPIO5_IRQ_ENA
262 #define WM8400_GPIO5_IRQ_ENA_MASK
263 #define WM8400_GPIO5_IRQ_ENA_SHIFT
264 #define WM8400_GPIO5_IRQ_ENA_WIDTH
265 #define WM8400_GPIO5_PU
266 #define WM8400_GPIO5_PU_MASK
267 #define WM8400_GPIO5_PU_SHIFT
268 #define WM8400_GPIO5_PU_WIDTH
269 #define WM8400_GPIO5_PD
270 #define WM8400_GPIO5_PD_MASK
271 #define WM8400_GPIO5_PD_SHIFT
272 #define WM8400_GPIO5_PD_WIDTH
273 #define WM8400_GPIO5_SEL_MASK
274 #define WM8400_GPIO5_SEL_SHIFT
275 #define WM8400_GPIO5_SEL_WIDTH
276
277 /*
278 * R22 (0x16) - GPIOCTRL 2
279 */
280 #define WM8400_TEMPOK_IRQ_ENA
281 #define WM8400_TEMPOK_IRQ_ENA_MASK
282 #define WM8400_TEMPOK_IRQ_ENA_SHIFT
283 #define WM8400_TEMPOK_IRQ_ENA_WIDTH
284 #define WM8400_MIC1SHRT_IRQ_ENA
285 #define WM8400_MIC1SHRT_IRQ_ENA_MASK
286 #define WM8400_MIC1SHRT_IRQ_ENA_SHIFT
287 #define WM8400_MIC1SHRT_IRQ_ENA_WIDTH
288 #define WM8400_MIC1DET_IRQ_ENA
289 #define WM8400_MIC1DET_IRQ_ENA_MASK
290 #define WM8400_MIC1DET_IRQ_ENA_SHIFT
291 #define WM8400_MIC1DET_IRQ_ENA_WIDTH
292 #define WM8400_FLL_LCK_IRQ_ENA
293 #define WM8400_FLL_LCK_IRQ_ENA_MASK
294 #define WM8400_FLL_LCK_IRQ_ENA_SHIFT
295 #define WM8400_FLL_LCK_IRQ_ENA_WIDTH
296 #define WM8400_GPI8_DEB_ENA
297 #define WM8400_GPI8_DEB_ENA_MASK
298 #define WM8400_GPI8_DEB_ENA_SHIFT
299 #define WM8400_GPI8_DEB_ENA_WIDTH
300 #define WM8400_GPI8_IRQ_ENA
301 #define WM8400_GPI8_IRQ_ENA_MASK
302 #define WM8400_GPI8_IRQ_ENA_SHIFT
303 #define WM8400_GPI8_IRQ_ENA_WIDTH
304 #define WM8400_GPI8_ENA
305 #define WM8400_GPI8_ENA_MASK
306 #define WM8400_GPI8_ENA_SHIFT
307 #define WM8400_GPI8_ENA_WIDTH
308 #define WM8400_GPI7_DEB_ENA
309 #define WM8400_GPI7_DEB_ENA_MASK
310 #define WM8400_GPI7_DEB_ENA_SHIFT
311 #define WM8400_GPI7_DEB_ENA_WIDTH
312 #define WM8400_GPI7_IRQ_ENA
313 #define WM8400_GPI7_IRQ_ENA_MASK
314 #define WM8400_GPI7_IRQ_ENA_SHIFT
315 #define WM8400_GPI7_IRQ_ENA_WIDTH
316 #define WM8400_GPI7_ENA
317 #define WM8400_GPI7_ENA_MASK
318 #define WM8400_GPI7_ENA_SHIFT
319 #define WM8400_GPI7_ENA_WIDTH
320
321 /*
322 * R23 (0x17) - GPIO_POL
323 */
324 #define WM8400_IRQ_INV
325 #define WM8400_IRQ_INV_MASK
326 #define WM8400_IRQ_INV_SHIFT
327 #define WM8400_IRQ_INV_WIDTH
328 #define WM8400_TEMPOK_POL
329 #define WM8400_TEMPOK_POL_MASK
330 #define WM8400_TEMPOK_POL_SHIFT
331 #define WM8400_TEMPOK_POL_WIDTH
332 #define WM8400_MIC1SHRT_POL
333 #define WM8400_MIC1SHRT_POL_MASK
334 #define WM8400_MIC1SHRT_POL_SHIFT
335 #define WM8400_MIC1SHRT_POL_WIDTH
336 #define WM8400_MIC1DET_POL
337 #define WM8400_MIC1DET_POL_MASK
338 #define WM8400_MIC1DET_POL_SHIFT
339 #define WM8400_MIC1DET_POL_WIDTH
340 #define WM8400_FLL_LCK_POL
341 #define WM8400_FLL_LCK_POL_MASK
342 #define WM8400_FLL_LCK_POL_SHIFT
343 #define WM8400_FLL_LCK_POL_WIDTH
344 #define WM8400_GPIO_POL_MASK
345 #define WM8400_GPIO_POL_SHIFT
346 #define WM8400_GPIO_POL_WIDTH
347
348 /*
349 * R65 (0x41) - LDO 1 Control
350 */
351 #define WM8400_LDO1_ENA
352 #define WM8400_LDO1_ENA_MASK
353 #define WM8400_LDO1_ENA_SHIFT
354 #define WM8400_LDO1_ENA_WIDTH
355 #define WM8400_LDO1_SWI
356 #define WM8400_LDO1_SWI_MASK
357 #define WM8400_LDO1_SWI_SHIFT
358 #define WM8400_LDO1_SWI_WIDTH
359 #define WM8400_LDO1_OPFLT
360 #define WM8400_LDO1_OPFLT_MASK
361 #define WM8400_LDO1_OPFLT_SHIFT
362 #define WM8400_LDO1_OPFLT_WIDTH
363 #define WM8400_LDO1_ERRACT
364 #define WM8400_LDO1_ERRACT_MASK
365 #define WM8400_LDO1_ERRACT_SHIFT
366 #define WM8400_LDO1_ERRACT_WIDTH
367 #define WM8400_LDO1_HIB_MODE
368 #define WM8400_LDO1_HIB_MODE_MASK
369 #define WM8400_LDO1_HIB_MODE_SHIFT
370 #define WM8400_LDO1_HIB_MODE_WIDTH
371 #define WM8400_LDO1_VIMG_MASK
372 #define WM8400_LDO1_VIMG_SHIFT
373 #define WM8400_LDO1_VIMG_WIDTH
374 #define WM8400_LDO1_VSEL_MASK
375 #define WM8400_LDO1_VSEL_SHIFT
376 #define WM8400_LDO1_VSEL_WIDTH
377
378 /*
379 * R66 (0x42) - LDO 2 Control
380 */
381 #define WM8400_LDO2_ENA
382 #define WM8400_LDO2_ENA_MASK
383 #define WM8400_LDO2_ENA_SHIFT
384 #define WM8400_LDO2_ENA_WIDTH
385 #define WM8400_LDO2_SWI
386 #define WM8400_LDO2_SWI_MASK
387 #define WM8400_LDO2_SWI_SHIFT
388 #define WM8400_LDO2_SWI_WIDTH
389 #define WM8400_LDO2_OPFLT
390 #define WM8400_LDO2_OPFLT_MASK
391 #define WM8400_LDO2_OPFLT_SHIFT
392 #define WM8400_LDO2_OPFLT_WIDTH
393 #define WM8400_LDO2_ERRACT
394 #define WM8400_LDO2_ERRACT_MASK
395 #define WM8400_LDO2_ERRACT_SHIFT
396 #define WM8400_LDO2_ERRACT_WIDTH
397 #define WM8400_LDO2_HIB_MODE
398 #define WM8400_LDO2_HIB_MODE_MASK
399 #define WM8400_LDO2_HIB_MODE_SHIFT
400 #define WM8400_LDO2_HIB_MODE_WIDTH
401 #define WM8400_LDO2_VIMG_MASK
402 #define WM8400_LDO2_VIMG_SHIFT
403 #define WM8400_LDO2_VIMG_WIDTH
404 #define WM8400_LDO2_VSEL_MASK
405 #define WM8400_LDO2_VSEL_SHIFT
406 #define WM8400_LDO2_VSEL_WIDTH
407
408 /*
409 * R67 (0x43) - LDO 3 Control
410 */
411 #define WM8400_LDO3_ENA
412 #define WM8400_LDO3_ENA_MASK
413 #define WM8400_LDO3_ENA_SHIFT
414 #define WM8400_LDO3_ENA_WIDTH
415 #define WM8400_LDO3_SWI
416 #define WM8400_LDO3_SWI_MASK
417 #define WM8400_LDO3_SWI_SHIFT
418 #define WM8400_LDO3_SWI_WIDTH
419 #define WM8400_LDO3_OPFLT
420 #define WM8400_LDO3_OPFLT_MASK
421 #define WM8400_LDO3_OPFLT_SHIFT
422 #define WM8400_LDO3_OPFLT_WIDTH
423 #define WM8400_LDO3_ERRACT
424 #define WM8400_LDO3_ERRACT_MASK
425 #define WM8400_LDO3_ERRACT_SHIFT
426 #define WM8400_LDO3_ERRACT_WIDTH
427 #define WM8400_LDO3_HIB_MODE
428 #define WM8400_LDO3_HIB_MODE_MASK
429 #define WM8400_LDO3_HIB_MODE_SHIFT
430 #define WM8400_LDO3_HIB_MODE_WIDTH
431 #define WM8400_LDO3_VIMG_MASK
432 #define WM8400_LDO3_VIMG_SHIFT
433 #define WM8400_LDO3_VIMG_WIDTH
434 #define WM8400_LDO3_VSEL_MASK
435 #define WM8400_LDO3_VSEL_SHIFT
436 #define WM8400_LDO3_VSEL_WIDTH
437
438 /*
439 * R68 (0x44) - LDO 4 Control
440 */
441 #define WM8400_LDO4_ENA
442 #define WM8400_LDO4_ENA_MASK
443 #define WM8400_LDO4_ENA_SHIFT
444 #define WM8400_LDO4_ENA_WIDTH
445 #define WM8400_LDO4_SWI
446 #define WM8400_LDO4_SWI_MASK
447 #define WM8400_LDO4_SWI_SHIFT
448 #define WM8400_LDO4_SWI_WIDTH
449 #define WM8400_LDO4_OPFLT
450 #define WM8400_LDO4_OPFLT_MASK
451 #define WM8400_LDO4_OPFLT_SHIFT
452 #define WM8400_LDO4_OPFLT_WIDTH
453 #define WM8400_LDO4_ERRACT
454 #define WM8400_LDO4_ERRACT_MASK
455 #define WM8400_LDO4_ERRACT_SHIFT
456 #define WM8400_LDO4_ERRACT_WIDTH
457 #define WM8400_LDO4_HIB_MODE
458 #define WM8400_LDO4_HIB_MODE_MASK
459 #define WM8400_LDO4_HIB_MODE_SHIFT
460 #define WM8400_LDO4_HIB_MODE_WIDTH
461 #define WM8400_LDO4_VIMG_MASK
462 #define WM8400_LDO4_VIMG_SHIFT
463 #define WM8400_LDO4_VIMG_WIDTH
464 #define WM8400_LDO4_VSEL_MASK
465 #define WM8400_LDO4_VSEL_SHIFT
466 #define WM8400_LDO4_VSEL_WIDTH
467
468 /*
469 * R70 (0x46) - DCDC1 Control 1
470 */
471 #define WM8400_DC1_ENA
472 #define WM8400_DC1_ENA_MASK
473 #define WM8400_DC1_ENA_SHIFT
474 #define WM8400_DC1_ENA_WIDTH
475 #define WM8400_DC1_ACTIVE
476 #define WM8400_DC1_ACTIVE_MASK
477 #define WM8400_DC1_ACTIVE_SHIFT
478 #define WM8400_DC1_ACTIVE_WIDTH
479 #define WM8400_DC1_SLEEP
480 #define WM8400_DC1_SLEEP_MASK
481 #define WM8400_DC1_SLEEP_SHIFT
482 #define WM8400_DC1_SLEEP_WIDTH
483 #define WM8400_DC1_OPFLT
484 #define WM8400_DC1_OPFLT_MASK
485 #define WM8400_DC1_OPFLT_SHIFT
486 #define WM8400_DC1_OPFLT_WIDTH
487 #define WM8400_DC1_ERRACT
488 #define WM8400_DC1_ERRACT_MASK
489 #define WM8400_DC1_ERRACT_SHIFT
490 #define WM8400_DC1_ERRACT_WIDTH
491 #define WM8400_DC1_HIB_MODE
492 #define WM8400_DC1_HIB_MODE_MASK
493 #define WM8400_DC1_HIB_MODE_SHIFT
494 #define WM8400_DC1_HIB_MODE_WIDTH
495 #define WM8400_DC1_SOFTST_MASK
496 #define WM8400_DC1_SOFTST_SHIFT
497 #define WM8400_DC1_SOFTST_WIDTH
498 #define WM8400_DC1_OV_PROT
499 #define WM8400_DC1_OV_PROT_MASK
500 #define WM8400_DC1_OV_PROT_SHIFT
501 #define WM8400_DC1_OV_PROT_WIDTH
502 #define WM8400_DC1_VSEL_MASK
503 #define WM8400_DC1_VSEL_SHIFT
504 #define WM8400_DC1_VSEL_WIDTH
505
506 /*
507 * R71 (0x47) - DCDC1 Control 2
508 */
509 #define WM8400_DC1_FRC_PWM
510 #define WM8400_DC1_FRC_PWM_MASK
511 #define WM8400_DC1_FRC_PWM_SHIFT
512 #define WM8400_DC1_FRC_PWM_WIDTH
513 #define WM8400_DC1_STBY_LIM_MASK
514 #define WM8400_DC1_STBY_LIM_SHIFT
515 #define WM8400_DC1_STBY_LIM_WIDTH
516 #define WM8400_DC1_ACT_LIM
517 #define WM8400_DC1_ACT_LIM_MASK
518 #define WM8400_DC1_ACT_LIM_SHIFT
519 #define WM8400_DC1_ACT_LIM_WIDTH
520 #define WM8400_DC1_VIMG_MASK
521 #define WM8400_DC1_VIMG_SHIFT
522 #define WM8400_DC1_VIMG_WIDTH
523
524 /*
525 * R72 (0x48) - DCDC2 Control 1
526 */
527 #define WM8400_DC2_ENA
528 #define WM8400_DC2_ENA_MASK
529 #define WM8400_DC2_ENA_SHIFT
530 #define WM8400_DC2_ENA_WIDTH
531 #define WM8400_DC2_ACTIVE
532 #define WM8400_DC2_ACTIVE_MASK
533 #define WM8400_DC2_ACTIVE_SHIFT
534 #define WM8400_DC2_ACTIVE_WIDTH
535 #define WM8400_DC2_SLEEP
536 #define WM8400_DC2_SLEEP_MASK
537 #define WM8400_DC2_SLEEP_SHIFT
538 #define WM8400_DC2_SLEEP_WIDTH
539 #define WM8400_DC2_OPFLT
540 #define WM8400_DC2_OPFLT_MASK
541 #define WM8400_DC2_OPFLT_SHIFT
542 #define WM8400_DC2_OPFLT_WIDTH
543 #define WM8400_DC2_ERRACT
544 #define WM8400_DC2_ERRACT_MASK
545 #define WM8400_DC2_ERRACT_SHIFT
546 #define WM8400_DC2_ERRACT_WIDTH
547 #define WM8400_DC2_HIB_MODE
548 #define WM8400_DC2_HIB_MODE_MASK
549 #define WM8400_DC2_HIB_MODE_SHIFT
550 #define WM8400_DC2_HIB_MODE_WIDTH
551 #define WM8400_DC2_SOFTST_MASK
552 #define WM8400_DC2_SOFTST_SHIFT
553 #define WM8400_DC2_SOFTST_WIDTH
554 #define WM8400_DC2_OV_PROT
555 #define WM8400_DC2_OV_PROT_MASK
556 #define WM8400_DC2_OV_PROT_SHIFT
557 #define WM8400_DC2_OV_PROT_WIDTH
558 #define WM8400_DC2_VSEL_MASK
559 #define WM8400_DC2_VSEL_SHIFT
560 #define WM8400_DC2_VSEL_WIDTH
561
562 /*
563 * R73 (0x49) - DCDC2 Control 2
564 */
565 #define WM8400_DC2_FRC_PWM
566 #define WM8400_DC2_FRC_PWM_MASK
567 #define WM8400_DC2_FRC_PWM_SHIFT
568 #define WM8400_DC2_FRC_PWM_WIDTH
569 #define WM8400_DC2_STBY_LIM_MASK
570 #define WM8400_DC2_STBY_LIM_SHIFT
571 #define WM8400_DC2_STBY_LIM_WIDTH
572 #define WM8400_DC2_ACT_LIM
573 #define WM8400_DC2_ACT_LIM_MASK
574 #define WM8400_DC2_ACT_LIM_SHIFT
575 #define WM8400_DC2_ACT_LIM_WIDTH
576 #define WM8400_DC2_VIMG_MASK
577 #define WM8400_DC2_VIMG_SHIFT
578 #define WM8400_DC2_VIMG_WIDTH
579
580 /*
581 * R75 (0x4B) - Interface
582 */
583 #define WM8400_AUTOINC
584 #define WM8400_AUTOINC_MASK
585 #define WM8400_AUTOINC_SHIFT
586 #define WM8400_AUTOINC_WIDTH
587 #define WM8400_ARA_ENA
588 #define WM8400_ARA_ENA_MASK
589 #define WM8400_ARA_ENA_SHIFT
590 #define WM8400_ARA_ENA_WIDTH
591 #define WM8400_SPI_CFG
592 #define WM8400_SPI_CFG_MASK
593 #define WM8400_SPI_CFG_SHIFT
594 #define WM8400_SPI_CFG_WIDTH
595
596 /*
597 * R76 (0x4C) - PM GENERAL
598 */
599 #define WM8400_CODEC_SOFTST
600 #define WM8400_CODEC_SOFTST_MASK
601 #define WM8400_CODEC_SOFTST_SHIFT
602 #define WM8400_CODEC_SOFTST_WIDTH
603 #define WM8400_CODEC_SOFTSD
604 #define WM8400_CODEC_SOFTSD_MASK
605 #define WM8400_CODEC_SOFTSD_SHIFT
606 #define WM8400_CODEC_SOFTSD_WIDTH
607 #define WM8400_CHIP_SOFTSD
608 #define WM8400_CHIP_SOFTSD_MASK
609 #define WM8400_CHIP_SOFTSD_SHIFT
610 #define WM8400_CHIP_SOFTSD_WIDTH
611 #define WM8400_DSLEEP1_POL
612 #define WM8400_DSLEEP1_POL_MASK
613 #define WM8400_DSLEEP1_POL_SHIFT
614 #define WM8400_DSLEEP1_POL_WIDTH
615 #define WM8400_DSLEEP2_POL
616 #define WM8400_DSLEEP2_POL_MASK
617 #define WM8400_DSLEEP2_POL_SHIFT
618 #define WM8400_DSLEEP2_POL_WIDTH
619 #define WM8400_PWR_STATE_MASK
620 #define WM8400_PWR_STATE_SHIFT
621 #define WM8400_PWR_STATE_WIDTH
622
623 /*
624 * R78 (0x4E) - PM Shutdown Control
625 */
626 #define WM8400_CHIP_GT150_ERRACT
627 #define WM8400_CHIP_GT150_ERRACT_MASK
628 #define WM8400_CHIP_GT150_ERRACT_SHIFT
629 #define WM8400_CHIP_GT150_ERRACT_WIDTH
630 #define WM8400_CHIP_GT115_ERRACT
631 #define WM8400_CHIP_GT115_ERRACT_MASK
632 #define WM8400_CHIP_GT115_ERRACT_SHIFT
633 #define WM8400_CHIP_GT115_ERRACT_WIDTH
634 #define WM8400_LINE_CMP_ERRACT
635 #define WM8400_LINE_CMP_ERRACT_MASK
636 #define WM8400_LINE_CMP_ERRACT_SHIFT
637 #define WM8400_LINE_CMP_ERRACT_WIDTH
638 #define WM8400_UVLO_ERRACT
639 #define WM8400_UVLO_ERRACT_MASK
640 #define WM8400_UVLO_ERRACT_SHIFT
641 #define WM8400_UVLO_ERRACT_WIDTH
642
643 /*
644 * R79 (0x4F) - Interrupt Status 1
645 */
646 #define WM8400_MICD_CINT
647 #define WM8400_MICD_CINT_MASK
648 #define WM8400_MICD_CINT_SHIFT
649 #define WM8400_MICD_CINT_WIDTH
650 #define WM8400_MICSCD_CINT
651 #define WM8400_MICSCD_CINT_MASK
652 #define WM8400_MICSCD_CINT_SHIFT
653 #define WM8400_MICSCD_CINT_WIDTH
654 #define WM8400_JDL_CINT
655 #define WM8400_JDL_CINT_MASK
656 #define WM8400_JDL_CINT_SHIFT
657 #define WM8400_JDL_CINT_WIDTH
658 #define WM8400_JDR_CINT
659 #define WM8400_JDR_CINT_MASK
660 #define WM8400_JDR_CINT_SHIFT
661 #define WM8400_JDR_CINT_WIDTH
662 #define WM8400_CODEC_SEQ_END_EINT
663 #define WM8400_CODEC_SEQ_END_EINT_MASK
664 #define WM8400_CODEC_SEQ_END_EINT_SHIFT
665 #define WM8400_CODEC_SEQ_END_EINT_WIDTH
666 #define WM8400_CDEL_TO_EINT
667 #define WM8400_CDEL_TO_EINT_MASK
668 #define WM8400_CDEL_TO_EINT_SHIFT
669 #define WM8400_CDEL_TO_EINT_WIDTH
670 #define WM8400_CHIP_GT150_EINT
671 #define WM8400_CHIP_GT150_EINT_MASK
672 #define WM8400_CHIP_GT150_EINT_SHIFT
673 #define WM8400_CHIP_GT150_EINT_WIDTH
674 #define WM8400_CHIP_GT115_EINT
675 #define WM8400_CHIP_GT115_EINT_MASK
676 #define WM8400_CHIP_GT115_EINT_SHIFT
677 #define WM8400_CHIP_GT115_EINT_WIDTH
678 #define WM8400_LINE_CMP_EINT
679 #define WM8400_LINE_CMP_EINT_MASK
680 #define WM8400_LINE_CMP_EINT_SHIFT
681 #define WM8400_LINE_CMP_EINT_WIDTH
682 #define WM8400_UVLO_EINT
683 #define WM8400_UVLO_EINT_MASK
684 #define WM8400_UVLO_EINT_SHIFT
685 #define WM8400_UVLO_EINT_WIDTH
686 #define WM8400_DC2_UV_EINT
687 #define WM8400_DC2_UV_EINT_MASK
688 #define WM8400_DC2_UV_EINT_SHIFT
689 #define WM8400_DC2_UV_EINT_WIDTH
690 #define WM8400_DC1_UV_EINT
691 #define WM8400_DC1_UV_EINT_MASK
692 #define WM8400_DC1_UV_EINT_SHIFT
693 #define WM8400_DC1_UV_EINT_WIDTH
694 #define WM8400_LDO4_UV_EINT
695 #define WM8400_LDO4_UV_EINT_MASK
696 #define WM8400_LDO4_UV_EINT_SHIFT
697 #define WM8400_LDO4_UV_EINT_WIDTH
698 #define WM8400_LDO3_UV_EINT
699 #define WM8400_LDO3_UV_EINT_MASK
700 #define WM8400_LDO3_UV_EINT_SHIFT
701 #define WM8400_LDO3_UV_EINT_WIDTH
702 #define WM8400_LDO2_UV_EINT
703 #define WM8400_LDO2_UV_EINT_MASK
704 #define WM8400_LDO2_UV_EINT_SHIFT
705 #define WM8400_LDO2_UV_EINT_WIDTH
706 #define WM8400_LDO1_UV_EINT
707 #define WM8400_LDO1_UV_EINT_MASK
708 #define WM8400_LDO1_UV_EINT_SHIFT
709 #define WM8400_LDO1_UV_EINT_WIDTH
710
711 /*
712 * R80 (0x50) - Interrupt Status 1 Mask
713 */
714 #define WM8400_IM_MICD_CINT
715 #define WM8400_IM_MICD_CINT_MASK
716 #define WM8400_IM_MICD_CINT_SHIFT
717 #define WM8400_IM_MICD_CINT_WIDTH
718 #define WM8400_IM_MICSCD_CINT
719 #define WM8400_IM_MICSCD_CINT_MASK
720 #define WM8400_IM_MICSCD_CINT_SHIFT
721 #define WM8400_IM_MICSCD_CINT_WIDTH
722 #define WM8400_IM_JDL_CINT
723 #define WM8400_IM_JDL_CINT_MASK
724 #define WM8400_IM_JDL_CINT_SHIFT
725 #define WM8400_IM_JDL_CINT_WIDTH
726 #define WM8400_IM_JDR_CINT
727 #define WM8400_IM_JDR_CINT_MASK
728 #define WM8400_IM_JDR_CINT_SHIFT
729 #define WM8400_IM_JDR_CINT_WIDTH
730 #define WM8400_IM_CODEC_SEQ_END_EINT
731 #define WM8400_IM_CODEC_SEQ_END_EINT_MASK
732 #define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT
733 #define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH
734 #define WM8400_IM_CDEL_TO_EINT
735 #define WM8400_IM_CDEL_TO_EINT_MASK
736 #define WM8400_IM_CDEL_TO_EINT_SHIFT
737 #define WM8400_IM_CDEL_TO_EINT_WIDTH
738 #define WM8400_IM_CHIP_GT150_EINT
739 #define WM8400_IM_CHIP_GT150_EINT_MASK
740 #define WM8400_IM_CHIP_GT150_EINT_SHIFT
741 #define WM8400_IM_CHIP_GT150_EINT_WIDTH
742 #define WM8400_IM_CHIP_GT115_EINT
743 #define WM8400_IM_CHIP_GT115_EINT_MASK
744 #define WM8400_IM_CHIP_GT115_EINT_SHIFT
745 #define WM8400_IM_CHIP_GT115_EINT_WIDTH
746 #define WM8400_IM_LINE_CMP_EINT
747 #define WM8400_IM_LINE_CMP_EINT_MASK
748 #define WM8400_IM_LINE_CMP_EINT_SHIFT
749 #define WM8400_IM_LINE_CMP_EINT_WIDTH
750 #define WM8400_IM_UVLO_EINT
751 #define WM8400_IM_UVLO_EINT_MASK
752 #define WM8400_IM_UVLO_EINT_SHIFT
753 #define WM8400_IM_UVLO_EINT_WIDTH
754 #define WM8400_IM_DC2_UV_EINT
755 #define WM8400_IM_DC2_UV_EINT_MASK
756 #define WM8400_IM_DC2_UV_EINT_SHIFT
757 #define WM8400_IM_DC2_UV_EINT_WIDTH
758 #define WM8400_IM_DC1_UV_EINT
759 #define WM8400_IM_DC1_UV_EINT_MASK
760 #define WM8400_IM_DC1_UV_EINT_SHIFT
761 #define WM8400_IM_DC1_UV_EINT_WIDTH
762 #define WM8400_IM_LDO4_UV_EINT
763 #define WM8400_IM_LDO4_UV_EINT_MASK
764 #define WM8400_IM_LDO4_UV_EINT_SHIFT
765 #define WM8400_IM_LDO4_UV_EINT_WIDTH
766 #define WM8400_IM_LDO3_UV_EINT
767 #define WM8400_IM_LDO3_UV_EINT_MASK
768 #define WM8400_IM_LDO3_UV_EINT_SHIFT
769 #define WM8400_IM_LDO3_UV_EINT_WIDTH
770 #define WM8400_IM_LDO2_UV_EINT
771 #define WM8400_IM_LDO2_UV_EINT_MASK
772 #define WM8400_IM_LDO2_UV_EINT_SHIFT
773 #define WM8400_IM_LDO2_UV_EINT_WIDTH
774 #define WM8400_IM_LDO1_UV_EINT
775 #define WM8400_IM_LDO1_UV_EINT_MASK
776 #define WM8400_IM_LDO1_UV_EINT_SHIFT
777 #define WM8400_IM_LDO1_UV_EINT_WIDTH
778
779 /*
780 * R81 (0x51) - Interrupt Levels
781 */
782 #define WM8400_MICD_LVL
783 #define WM8400_MICD_LVL_MASK
784 #define WM8400_MICD_LVL_SHIFT
785 #define WM8400_MICD_LVL_WIDTH
786 #define WM8400_MICSCD_LVL
787 #define WM8400_MICSCD_LVL_MASK
788 #define WM8400_MICSCD_LVL_SHIFT
789 #define WM8400_MICSCD_LVL_WIDTH
790 #define WM8400_JDL_LVL
791 #define WM8400_JDL_LVL_MASK
792 #define WM8400_JDL_LVL_SHIFT
793 #define WM8400_JDL_LVL_WIDTH
794 #define WM8400_JDR_LVL
795 #define WM8400_JDR_LVL_MASK
796 #define WM8400_JDR_LVL_SHIFT
797 #define WM8400_JDR_LVL_WIDTH
798 #define WM8400_CODEC_SEQ_END_LVL
799 #define WM8400_CODEC_SEQ_END_LVL_MASK
800 #define WM8400_CODEC_SEQ_END_LVL_SHIFT
801 #define WM8400_CODEC_SEQ_END_LVL_WIDTH
802 #define WM8400_CDEL_TO_LVL
803 #define WM8400_CDEL_TO_LVL_MASK
804 #define WM8400_CDEL_TO_LVL_SHIFT
805 #define WM8400_CDEL_TO_LVL_WIDTH
806 #define WM8400_CHIP_GT150_LVL
807 #define WM8400_CHIP_GT150_LVL_MASK
808 #define WM8400_CHIP_GT150_LVL_SHIFT
809 #define WM8400_CHIP_GT150_LVL_WIDTH
810 #define WM8400_CHIP_GT115_LVL
811 #define WM8400_CHIP_GT115_LVL_MASK
812 #define WM8400_CHIP_GT115_LVL_SHIFT
813 #define WM8400_CHIP_GT115_LVL_WIDTH
814 #define WM8400_LINE_CMP_LVL
815 #define WM8400_LINE_CMP_LVL_MASK
816 #define WM8400_LINE_CMP_LVL_SHIFT
817 #define WM8400_LINE_CMP_LVL_WIDTH
818 #define WM8400_UVLO_LVL
819 #define WM8400_UVLO_LVL_MASK
820 #define WM8400_UVLO_LVL_SHIFT
821 #define WM8400_UVLO_LVL_WIDTH
822 #define WM8400_DC2_UV_LVL
823 #define WM8400_DC2_UV_LVL_MASK
824 #define WM8400_DC2_UV_LVL_SHIFT
825 #define WM8400_DC2_UV_LVL_WIDTH
826 #define WM8400_DC1_UV_LVL
827 #define WM8400_DC1_UV_LVL_MASK
828 #define WM8400_DC1_UV_LVL_SHIFT
829 #define WM8400_DC1_UV_LVL_WIDTH
830 #define WM8400_LDO4_UV_LVL
831 #define WM8400_LDO4_UV_LVL_MASK
832 #define WM8400_LDO4_UV_LVL_SHIFT
833 #define WM8400_LDO4_UV_LVL_WIDTH
834 #define WM8400_LDO3_UV_LVL
835 #define WM8400_LDO3_UV_LVL_MASK
836 #define WM8400_LDO3_UV_LVL_SHIFT
837 #define WM8400_LDO3_UV_LVL_WIDTH
838 #define WM8400_LDO2_UV_LVL
839 #define WM8400_LDO2_UV_LVL_MASK
840 #define WM8400_LDO2_UV_LVL_SHIFT
841 #define WM8400_LDO2_UV_LVL_WIDTH
842 #define WM8400_LDO1_UV_LVL
843 #define WM8400_LDO1_UV_LVL_MASK
844 #define WM8400_LDO1_UV_LVL_SHIFT
845 #define WM8400_LDO1_UV_LVL_WIDTH
846
847 /*
848 * R82 (0x52) - Shutdown Reason
849 */
850 #define WM8400_SDR_CHIP_SOFTSD
851 #define WM8400_SDR_CHIP_SOFTSD_MASK
852 #define WM8400_SDR_CHIP_SOFTSD_SHIFT
853 #define WM8400_SDR_CHIP_SOFTSD_WIDTH
854 #define WM8400_SDR_NPDN
855 #define WM8400_SDR_NPDN_MASK
856 #define WM8400_SDR_NPDN_SHIFT
857 #define WM8400_SDR_NPDN_WIDTH
858 #define WM8400_SDR_CHIP_GT150
859 #define WM8400_SDR_CHIP_GT150_MASK
860 #define WM8400_SDR_CHIP_GT150_SHIFT
861 #define WM8400_SDR_CHIP_GT150_WIDTH
862 #define WM8400_SDR_CHIP_GT115
863 #define WM8400_SDR_CHIP_GT115_MASK
864 #define WM8400_SDR_CHIP_GT115_SHIFT
865 #define WM8400_SDR_CHIP_GT115_WIDTH
866 #define WM8400_SDR_LINE_CMP
867 #define WM8400_SDR_LINE_CMP_MASK
868 #define WM8400_SDR_LINE_CMP_SHIFT
869 #define WM8400_SDR_LINE_CMP_WIDTH
870 #define WM8400_SDR_UVLO
871 #define WM8400_SDR_UVLO_MASK
872 #define WM8400_SDR_UVLO_SHIFT
873 #define WM8400_SDR_UVLO_WIDTH
874 #define WM8400_SDR_DC2_UV
875 #define WM8400_SDR_DC2_UV_MASK
876 #define WM8400_SDR_DC2_UV_SHIFT
877 #define WM8400_SDR_DC2_UV_WIDTH
878 #define WM8400_SDR_DC1_UV
879 #define WM8400_SDR_DC1_UV_MASK
880 #define WM8400_SDR_DC1_UV_SHIFT
881 #define WM8400_SDR_DC1_UV_WIDTH
882 #define WM8400_SDR_LDO4_UV
883 #define WM8400_SDR_LDO4_UV_MASK
884 #define WM8400_SDR_LDO4_UV_SHIFT
885 #define WM8400_SDR_LDO4_UV_WIDTH
886 #define WM8400_SDR_LDO3_UV
887 #define WM8400_SDR_LDO3_UV_MASK
888 #define WM8400_SDR_LDO3_UV_SHIFT
889 #define WM8400_SDR_LDO3_UV_WIDTH
890 #define WM8400_SDR_LDO2_UV
891 #define WM8400_SDR_LDO2_UV_MASK
892 #define WM8400_SDR_LDO2_UV_SHIFT
893 #define WM8400_SDR_LDO2_UV_WIDTH
894 #define WM8400_SDR_LDO1_UV
895 #define WM8400_SDR_LDO1_UV_MASK
896 #define WM8400_SDR_LDO1_UV_SHIFT
897 #define WM8400_SDR_LDO1_UV_WIDTH
898
899 /*
900 * R84 (0x54) - Line Circuits
901 */
902 #define WM8400_BG_LINE_COMP
903 #define WM8400_BG_LINE_COMP_MASK
904 #define WM8400_BG_LINE_COMP_SHIFT
905 #define WM8400_BG_LINE_COMP_WIDTH
906 #define WM8400_LINE_CMP_VTHI_MASK
907 #define WM8400_LINE_CMP_VTHI_SHIFT
908 #define WM8400_LINE_CMP_VTHI_WIDTH
909 #define WM8400_LINE_CMP_VTHD_MASK
910 #define WM8400_LINE_CMP_VTHD_SHIFT
911 #define WM8400_LINE_CMP_VTHD_WIDTH
912
913 #endif
914
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