1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 2 /* 3 * Copyright (C) 2015 Microchip Technology 4 */ 5 6 #ifndef _MICROCHIPPHY_H 7 #define _MICROCHIPPHY_H 8 9 #define LAN88XX_INT_MASK 10 #define LAN88XX_INT_MASK_MDINTPIN_EN_ 11 #define LAN88XX_INT_MASK_SPEED_CHANGE_ 12 #define LAN88XX_INT_MASK_LINK_CHANGE_ 13 #define LAN88XX_INT_MASK_FDX_CHANGE_ 14 #define LAN88XX_INT_MASK_AUTONEG_ERR_ 15 #define LAN88XX_INT_MASK_AUTONEG_DONE_ 16 #define LAN88XX_INT_MASK_POE_DETECT_ 17 #define LAN88XX_INT_MASK_SYMBOL_ERR_ 18 #define LAN88XX_INT_MASK_FAST_LINK_FAIL_ 19 #define LAN88XX_INT_MASK_WOL_EVENT_ 20 #define LAN88XX_INT_MASK_EXTENDED_INT_ 21 #define LAN88XX_INT_MASK_RESERVED_ 22 #define LAN88XX_INT_MASK_FALSE_CARRIER_ 23 #define LAN88XX_INT_MASK_LINK_SPEED_DS_ 24 #define LAN88XX_INT_MASK_MASTER_SLAVE_DONE_ 25 #define LAN88XX_INT_MASK_RX__ER_ 26 27 #define LAN88XX_INT_STS 28 #define LAN88XX_INT_STS_INT_ACTIVE_ 29 #define LAN88XX_INT_STS_SPEED_CHANGE_ 30 #define LAN88XX_INT_STS_LINK_CHANGE_ 31 #define LAN88XX_INT_STS_FDX_CHANGE_ 32 #define LAN88XX_INT_STS_AUTONEG_ERR_ 33 #define LAN88XX_INT_STS_AUTONEG_DONE_ 34 #define LAN88XX_INT_STS_POE_DETECT_ 35 #define LAN88XX_INT_STS_SYMBOL_ERR_ 36 #define LAN88XX_INT_STS_FAST_LINK_FAIL_ 37 #define LAN88XX_INT_STS_WOL_EVENT_ 38 #define LAN88XX_INT_STS_EXTENDED_INT_ 39 #define LAN88XX_INT_STS_RESERVED_ 40 #define LAN88XX_INT_STS_FALSE_CARRIER_ 41 #define LAN88XX_INT_STS_LINK_SPEED_DS_ 42 #define LAN88XX_INT_STS_MASTER_SLAVE_DONE_ 43 #define LAN88XX_INT_STS_RX_ER_ 44 45 #define LAN88XX_EXT_PAGE_ACCESS 46 #define LAN88XX_EXT_PAGE_SPACE_0 47 #define LAN88XX_EXT_PAGE_SPACE_1 48 #define LAN88XX_EXT_PAGE_SPACE_2 49 50 /* Extended Register Page 1 space */ 51 #define LAN88XX_EXT_MODE_CTRL 52 #define LAN88XX_EXT_MODE_CTRL_MDIX_MASK_ 53 #define LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_ 54 #define LAN88XX_EXT_MODE_CTRL_MDI_ 55 #define LAN88XX_EXT_MODE_CTRL_MDI_X_ 56 57 /* MMD 3 Registers */ 58 #define LAN88XX_MMD3_CHIP_ID 59 #define LAN88XX_MMD3_CHIP_REV 60 61 /* Registers specific to the LAN7800/LAN7850 e 62 #define LAN78XX_PHY_LED_MODE_SELECT 63 64 /* DSP registers */ 65 #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG 66 #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_ 67 #define LAN88XX_EXT_PAGE_ACCESS_TR 68 #define LAN88XX_EXT_PAGE_TR_CR 69 #define LAN88XX_EXT_PAGE_TR_LOW_DATA 70 #define LAN88XX_EXT_PAGE_TR_HIGH_DATA 71 72 #endif /* _MICROCHIPPHY_H */ 73
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