1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-O 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2018 Mellanox Technologies. * 2 /* Copyright (c) 2018 Mellanox Technologies. */
3 3
4 #ifndef MLX5_CORE_EQ_H 4 #ifndef MLX5_CORE_EQ_H
5 #define MLX5_CORE_EQ_H 5 #define MLX5_CORE_EQ_H
6 6
>> 7 enum {
>> 8 MLX5_EQ_PAGEREQ_IDX = 0,
>> 9 MLX5_EQ_CMD_IDX = 1,
>> 10 MLX5_EQ_ASYNC_IDX = 2,
>> 11 /* reserved to be used by mlx5_core ulps (mlx5e/mlx5_ib) */
>> 12 MLX5_EQ_PFAULT_IDX = 3,
>> 13 MLX5_EQ_MAX_ASYNC_EQS,
>> 14 /* completion eqs vector indices start here */
>> 15 MLX5_EQ_VEC_COMP_BASE = MLX5_EQ_MAX_ASYNC_EQS,
>> 16 };
>> 17
7 #define MLX5_NUM_CMD_EQE (32) 18 #define MLX5_NUM_CMD_EQE (32)
8 #define MLX5_NUM_ASYNC_EQE (0x1000) 19 #define MLX5_NUM_ASYNC_EQE (0x1000)
9 #define MLX5_NUM_SPARE_EQE (0x80) 20 #define MLX5_NUM_SPARE_EQE (0x80)
10 21
11 struct mlx5_eq; 22 struct mlx5_eq;
12 struct mlx5_irq; <<
13 struct mlx5_core_dev; 23 struct mlx5_core_dev;
14 24
15 struct mlx5_eq_param { 25 struct mlx5_eq_param {
>> 26 u8 index;
16 int nent; 27 int nent;
17 u64 mask[4]; !! 28 u64 mask;
18 struct mlx5_irq *irq; !! 29 void *context;
>> 30 irq_handler_t handler;
19 }; 31 };
20 32
21 struct mlx5_eq * 33 struct mlx5_eq *
22 mlx5_eq_create_generic(struct mlx5_core_dev *d !! 34 mlx5_eq_create_generic(struct mlx5_core_dev *dev, const char *name,
>> 35 struct mlx5_eq_param *param);
23 int 36 int
24 mlx5_eq_destroy_generic(struct mlx5_core_dev * 37 mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
25 int mlx5_eq_enable(struct mlx5_core_dev *dev, <<
26 struct notifier_block *nb); <<
27 void mlx5_eq_disable(struct mlx5_core_dev *dev <<
28 struct notifier_block *nb <<
29 38
30 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_e 39 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc);
31 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 40 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm);
32 41
33 /* The HCA will think the queue has overflowed 42 /* The HCA will think the queue has overflowed if we
34 * don't tell it we've been processing events. 43 * don't tell it we've been processing events. We
35 * create EQs with MLX5_NUM_SPARE_EQE extra en 44 * create EQs with MLX5_NUM_SPARE_EQE extra entries,
36 * so we must update our consumer index at 45 * so we must update our consumer index at
37 * least that often. 46 * least that often.
38 * 47 *
39 * mlx5_eq_update_cc must be called on every E 48 * mlx5_eq_update_cc must be called on every EQE @EQ irq handler
40 */ 49 */
41 static inline u32 mlx5_eq_update_cc(struct mlx 50 static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc)
42 { 51 {
43 if (unlikely(cc >= MLX5_NUM_SPARE_EQE) 52 if (unlikely(cc >= MLX5_NUM_SPARE_EQE)) {
44 mlx5_eq_update_ci(eq, cc, 0); 53 mlx5_eq_update_ci(eq, cc, 0);
45 cc = 0; 54 cc = 0;
46 } 55 }
47 return cc; 56 return cc;
48 } 57 }
49 58
50 struct mlx5_nb { 59 struct mlx5_nb {
51 struct notifier_block nb; 60 struct notifier_block nb;
52 u8 event_type; 61 u8 event_type;
53 }; 62 };
54 63
55 #define mlx5_nb_cof(ptr, type, member) \ 64 #define mlx5_nb_cof(ptr, type, member) \
56 (container_of(container_of(ptr, struct 65 (container_of(container_of(ptr, struct mlx5_nb, nb), type, member))
57 66
58 #define MLX5_NB_INIT(name, handler, event) do 67 #define MLX5_NB_INIT(name, handler, event) do { \
59 (name)->nb.notifier_call = handler; 68 (name)->nb.notifier_call = handler; \
60 (name)->event_type = MLX5_EVENT_TYPE_# 69 (name)->event_type = MLX5_EVENT_TYPE_##event; \
61 } while (0) 70 } while (0)
62 71
63 #endif /* MLX5_CORE_EQ_H */ 72 #endif /* MLX5_CORE_EQ_H */
64 73
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