1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-O 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2020 Mellanox Technologies Lt 2 /* Copyright (c) 2020 Mellanox Technologies Ltd. */
3 3
4 #ifndef __MLX5_IFC_VDPA_H_ 4 #ifndef __MLX5_IFC_VDPA_H_
5 #define __MLX5_IFC_VDPA_H_ 5 #define __MLX5_IFC_VDPA_H_
6 6
7 enum { 7 enum {
8 MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE 8 MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE = 0x0,
9 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE 9 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE = 0x1,
10 MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE 10 MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE = 0x2,
11 }; 11 };
12 12
13 enum { 13 enum {
14 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYP !! 14 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_SPLIT = 0x1, // do I check this caps?
15 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYP !! 15 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_PACKED = 0x2,
16 }; 16 };
17 17
18 enum { 18 enum {
19 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE !! 19 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT = 0,
20 BIT(MLX5_VIRTIO_EMULATION_VIRT !! 20 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED = 1,
21 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE <<
22 BIT(MLX5_VIRTIO_EMULATION_VIRT <<
23 }; 21 };
24 22
25 struct mlx5_ifc_virtio_q_bits { 23 struct mlx5_ifc_virtio_q_bits {
26 u8 virtio_q_type[0x8]; 24 u8 virtio_q_type[0x8];
27 u8 reserved_at_8[0x5]; 25 u8 reserved_at_8[0x5];
28 u8 event_mode[0x3]; 26 u8 event_mode[0x3];
29 u8 queue_index[0x10]; 27 u8 queue_index[0x10];
30 28
31 u8 full_emulation[0x1]; 29 u8 full_emulation[0x1];
32 u8 virtio_version_1_0[0x1]; 30 u8 virtio_version_1_0[0x1];
33 u8 reserved_at_22[0x2]; 31 u8 reserved_at_22[0x2];
34 u8 offload_type[0x4]; 32 u8 offload_type[0x4];
35 u8 event_qpn_or_msix[0x18]; 33 u8 event_qpn_or_msix[0x18];
36 34
37 u8 doorbell_stride_index[0x10]; 35 u8 doorbell_stride_index[0x10];
38 u8 queue_size[0x10]; 36 u8 queue_size[0x10];
39 37
40 u8 device_emulation_id[0x20]; 38 u8 device_emulation_id[0x20];
41 39
42 u8 desc_addr[0x40]; 40 u8 desc_addr[0x40];
43 41
44 u8 used_addr[0x40]; 42 u8 used_addr[0x40];
45 43
46 u8 available_addr[0x40]; 44 u8 available_addr[0x40];
47 45
48 u8 virtio_q_mkey[0x20]; 46 u8 virtio_q_mkey[0x20];
49 47
50 u8 max_tunnel_desc[0x10]; 48 u8 max_tunnel_desc[0x10];
51 u8 reserved_at_170[0x8]; 49 u8 reserved_at_170[0x8];
52 u8 error_type[0x8]; 50 u8 error_type[0x8];
53 51
54 u8 umem_1_id[0x20]; 52 u8 umem_1_id[0x20];
55 53
56 u8 umem_1_size[0x20]; 54 u8 umem_1_size[0x20];
57 55
58 u8 umem_1_offset[0x40]; 56 u8 umem_1_offset[0x40];
59 57
60 u8 umem_2_id[0x20]; 58 u8 umem_2_id[0x20];
61 59
62 u8 umem_2_size[0x20]; 60 u8 umem_2_size[0x20];
63 61
64 u8 umem_2_offset[0x40]; 62 u8 umem_2_offset[0x40];
65 63
66 u8 umem_3_id[0x20]; 64 u8 umem_3_id[0x20];
67 65
68 u8 umem_3_size[0x20]; 66 u8 umem_3_size[0x20];
69 67
70 u8 umem_3_offset[0x40]; 68 u8 umem_3_offset[0x40];
71 69
72 u8 counter_set_id[0x20]; 70 u8 counter_set_id[0x20];
73 71
74 u8 reserved_at_320[0x8]; 72 u8 reserved_at_320[0x8];
75 u8 pd[0x18]; 73 u8 pd[0x18];
76 74
77 u8 reserved_at_340[0x20]; !! 75 u8 reserved_at_340[0xc0];
78 <<
79 u8 desc_group_mkey[0x20]; <<
80 <<
81 u8 reserved_at_380[0x80]; <<
82 }; 76 };
83 77
84 struct mlx5_ifc_virtio_net_q_object_bits { 78 struct mlx5_ifc_virtio_net_q_object_bits {
85 u8 modify_field_select[0x40]; 79 u8 modify_field_select[0x40];
86 80
87 u8 reserved_at_40[0x20]; 81 u8 reserved_at_40[0x20];
88 82
89 u8 vhca_id[0x10]; 83 u8 vhca_id[0x10];
90 u8 reserved_at_70[0x10]; 84 u8 reserved_at_70[0x10];
91 85
92 u8 queue_feature_bit_mask_12_3[0xa] 86 u8 queue_feature_bit_mask_12_3[0xa];
93 u8 dirty_bitmap_dump_enable[0x1]; 87 u8 dirty_bitmap_dump_enable[0x1];
94 u8 vhost_log_page[0x5]; 88 u8 vhost_log_page[0x5];
95 u8 reserved_at_90[0xc]; 89 u8 reserved_at_90[0xc];
96 u8 state[0x4]; 90 u8 state[0x4];
97 91
98 u8 reserved_at_a0[0x5]; 92 u8 reserved_at_a0[0x5];
99 u8 queue_feature_bit_mask_2_0[0x3]; 93 u8 queue_feature_bit_mask_2_0[0x3];
100 u8 tisn_or_qpn[0x18]; 94 u8 tisn_or_qpn[0x18];
101 95
102 u8 dirty_bitmap_mkey[0x20]; 96 u8 dirty_bitmap_mkey[0x20];
103 97
104 u8 dirty_bitmap_size[0x20]; 98 u8 dirty_bitmap_size[0x20];
105 99
106 u8 dirty_bitmap_addr[0x40]; 100 u8 dirty_bitmap_addr[0x40];
107 101
108 u8 hw_available_index[0x10]; 102 u8 hw_available_index[0x10];
109 u8 hw_used_index[0x10]; 103 u8 hw_used_index[0x10];
110 104
111 u8 reserved_at_160[0xa0]; 105 u8 reserved_at_160[0xa0];
112 106
113 struct mlx5_ifc_virtio_q_bits virtio_q 107 struct mlx5_ifc_virtio_q_bits virtio_q_context;
114 }; 108 };
115 109
116 struct mlx5_ifc_create_virtio_net_q_in_bits { 110 struct mlx5_ifc_create_virtio_net_q_in_bits {
117 struct mlx5_ifc_general_obj_in_cmd_hdr 111 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
118 112
119 struct mlx5_ifc_virtio_net_q_object_bi 113 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
120 }; 114 };
121 115
122 struct mlx5_ifc_create_virtio_net_q_out_bits { 116 struct mlx5_ifc_create_virtio_net_q_out_bits {
123 struct mlx5_ifc_general_obj_out_cmd_hd 117 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
124 }; 118 };
125 119
126 struct mlx5_ifc_destroy_virtio_net_q_in_bits { 120 struct mlx5_ifc_destroy_virtio_net_q_in_bits {
127 struct mlx5_ifc_general_obj_in_cmd_hdr 121 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_out_cmd_hdr;
128 }; 122 };
129 123
130 struct mlx5_ifc_destroy_virtio_net_q_out_bits 124 struct mlx5_ifc_destroy_virtio_net_q_out_bits {
131 struct mlx5_ifc_general_obj_out_cmd_hd 125 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
132 }; 126 };
133 127
134 struct mlx5_ifc_query_virtio_net_q_in_bits { 128 struct mlx5_ifc_query_virtio_net_q_in_bits {
135 struct mlx5_ifc_general_obj_in_cmd_hdr 129 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
136 }; 130 };
137 131
138 struct mlx5_ifc_query_virtio_net_q_out_bits { 132 struct mlx5_ifc_query_virtio_net_q_out_bits {
139 struct mlx5_ifc_general_obj_out_cmd_hd 133 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
140 134
141 struct mlx5_ifc_virtio_net_q_object_bi 135 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
142 }; 136 };
143 137
144 enum { 138 enum {
145 MLX5_VIRTQ_MODIFY_MASK_STATE 139 MLX5_VIRTQ_MODIFY_MASK_STATE = (u64)1 << 0,
146 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_PA 140 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_PARAMS = (u64)1 << 3,
147 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_DU 141 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_DUMP_ENABLE = (u64)1 << 4,
148 MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_ADDRS <<
149 MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_AVAIL_ <<
150 MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_USED_I <<
151 MLX5_VIRTQ_MODIFY_MASK_QUEUE_VIRTIO_VE <<
152 MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_MKEY <<
153 MLX5_VIRTQ_MODIFY_MASK_QUEUE_FEATURES <<
154 MLX5_VIRTQ_MODIFY_MASK_DESC_GROUP_MKEY <<
155 }; 142 };
156 143
157 enum { 144 enum {
158 MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT 145 MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT = 0x0,
159 MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY 146 MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY = 0x1,
160 MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND 147 MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND = 0x2,
161 MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR 148 MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR = 0x3,
162 }; 149 };
163 150
164 /* This indicates that the object was not crea <<
165 * been desroyed. It is very safe to assume th <<
166 * have so many states <<
167 */ <<
168 enum { <<
169 MLX5_VIRTIO_NET_Q_OBJECT_NONE = 0xffff <<
170 }; <<
171 <<
172 enum { 151 enum {
173 MLX5_RQTC_LIST_Q_TYPE_RQ = 152 MLX5_RQTC_LIST_Q_TYPE_RQ = 0x0,
174 MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 153 MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 0x1,
175 }; 154 };
176 155
177 struct mlx5_ifc_modify_virtio_net_q_in_bits { 156 struct mlx5_ifc_modify_virtio_net_q_in_bits {
178 struct mlx5_ifc_general_obj_in_cmd_hdr 157 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
179 158
180 struct mlx5_ifc_virtio_net_q_object_bi 159 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
181 }; 160 };
182 161
183 struct mlx5_ifc_modify_virtio_net_q_out_bits { 162 struct mlx5_ifc_modify_virtio_net_q_out_bits {
184 struct mlx5_ifc_general_obj_out_cmd_hd 163 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
185 }; <<
186 <<
187 struct mlx5_ifc_virtio_q_counters_bits { <<
188 u8 modify_field_select[0x40]; <<
189 u8 reserved_at_40[0x40]; <<
190 u8 received_desc[0x40]; <<
191 u8 completed_desc[0x40]; <<
192 u8 error_cqes[0x20]; <<
193 u8 bad_desc_errors[0x20]; <<
194 u8 exceed_max_chain[0x20]; <<
195 u8 invalid_buffer[0x20]; <<
196 u8 reserved_at_180[0x280]; <<
197 }; <<
198 <<
199 struct mlx5_ifc_create_virtio_q_counters_in_bi <<
200 struct mlx5_ifc_general_obj_in_cmd_hdr <<
201 struct mlx5_ifc_virtio_q_counters_bits <<
202 }; <<
203 <<
204 struct mlx5_ifc_create_virtio_q_counters_out_b <<
205 struct mlx5_ifc_general_obj_in_cmd_hdr <<
206 struct mlx5_ifc_virtio_q_counters_bits <<
207 }; <<
208 <<
209 struct mlx5_ifc_destroy_virtio_q_counters_in_b <<
210 struct mlx5_ifc_general_obj_in_cmd_hdr <<
211 }; <<
212 <<
213 struct mlx5_ifc_destroy_virtio_q_counters_out_ <<
214 struct mlx5_ifc_general_obj_out_cmd_hd <<
215 }; <<
216 <<
217 struct mlx5_ifc_query_virtio_q_counters_in_bit <<
218 struct mlx5_ifc_general_obj_in_cmd_hdr <<
219 }; <<
220 <<
221 struct mlx5_ifc_query_virtio_q_counters_out_bi <<
222 struct mlx5_ifc_general_obj_in_cmd_hdr <<
223 struct mlx5_ifc_virtio_q_counters_bits <<
224 }; 164 };
225 165
226 #endif /* __MLX5_IFC_VDPA_H_ */ 166 #endif /* __MLX5_IFC_VDPA_H_ */
227 167
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