1 /* 1 /*
2 * Copyright (c) 2013-2015, Mellanox Technolog 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 * 3 *
4 * This software is available to you under a c 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed un 5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, ava 6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this sourc 7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below: 8 * OpenIB.org BSD license below:
9 * 9 *
10 * Redistribution and use in source and bi 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted pro 11 * without modification, are permitted provided that the following
12 * conditions are met: 12 * conditions are met:
13 * 13 *
14 * - Redistributions of source code must 14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of condi 15 * copyright notice, this list of conditions and the following
16 * disclaimer. 16 * disclaimer.
17 * 17 *
18 * - Redistributions in binary form must 18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of condi 19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/ 20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution. 21 * provided with the distribution.
22 * 22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMIT 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR P 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTH 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER L 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARIS 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 */ 31 */
32 32
33 #ifndef MLX5_QP_H 33 #ifndef MLX5_QP_H
34 #define MLX5_QP_H 34 #define MLX5_QP_H
35 35
36 #include <linux/mlx5/device.h> 36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h> 37 #include <linux/mlx5/driver.h>
38 38
39 #define MLX5_TERMINATE_SCATTER_LIST_LKEY cpu_t !! 39 #define MLX5_INVALID_LKEY 0x100
40 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV ( !! 40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE <<
42 #define MLX5_DIF_SIZE 8 41 #define MLX5_DIF_SIZE 8
43 #define MLX5_STRIDE_BLOCK_OP 0x400 42 #define MLX5_STRIDE_BLOCK_OP 0x400
44 #define MLX5_CPY_GRD_MASK 0xc0 43 #define MLX5_CPY_GRD_MASK 0xc0
45 #define MLX5_CPY_APP_MASK 0x30 44 #define MLX5_CPY_APP_MASK 0x30
46 #define MLX5_CPY_REF_MASK 0x0f 45 #define MLX5_CPY_REF_MASK 0x0f
47 #define MLX5_BSF_INC_REFTAG (1 << 6) 46 #define MLX5_BSF_INC_REFTAG (1 << 6)
48 #define MLX5_BSF_INL_VALID (1 << 15) 47 #define MLX5_BSF_INL_VALID (1 << 15)
49 #define MLX5_BSF_REFRESH_DIF (1 << 14) 48 #define MLX5_BSF_REFRESH_DIF (1 << 14)
50 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
51 #define MLX5_BSF_APPTAG_ESCAPE 0x1 50 #define MLX5_BSF_APPTAG_ESCAPE 0x1
52 #define MLX5_BSF_APPREF_ESCAPE 0x2 51 #define MLX5_BSF_APPREF_ESCAPE 0x2
53 52
>> 53 #define MLX5_QPN_BITS 24
>> 54 #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1)
>> 55
54 enum mlx5_qp_optpar { 56 enum mlx5_qp_optpar {
55 MLX5_QP_OPTPAR_ALT_ADDR_PATH 57 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
56 MLX5_QP_OPTPAR_RRE 58 MLX5_QP_OPTPAR_RRE = 1 << 1,
57 MLX5_QP_OPTPAR_RAE 59 MLX5_QP_OPTPAR_RAE = 1 << 2,
58 MLX5_QP_OPTPAR_RWE 60 MLX5_QP_OPTPAR_RWE = 1 << 3,
59 MLX5_QP_OPTPAR_PKEY_INDEX 61 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
60 MLX5_QP_OPTPAR_Q_KEY 62 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
61 MLX5_QP_OPTPAR_RNR_TIMEOUT 63 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH 64 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
63 MLX5_QP_OPTPAR_SRA_MAX 65 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
64 MLX5_QP_OPTPAR_RRA_MAX 66 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
65 MLX5_QP_OPTPAR_PM_STATE 67 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
66 MLX5_QP_OPTPAR_RETRY_COUNT 68 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
67 MLX5_QP_OPTPAR_RNR_RETRY 69 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
68 MLX5_QP_OPTPAR_ACK_TIMEOUT 70 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
69 MLX5_QP_OPTPAR_LAG_TX_AFF <<
70 MLX5_QP_OPTPAR_PRI_PORT 71 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
71 MLX5_QP_OPTPAR_SRQN 72 MLX5_QP_OPTPAR_SRQN = 1 << 18,
72 MLX5_QP_OPTPAR_CQN_RCV 73 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
73 MLX5_QP_OPTPAR_DC_HS 74 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
74 MLX5_QP_OPTPAR_DC_KEY 75 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
75 MLX5_QP_OPTPAR_COUNTER_SET_ID <<
76 }; 76 };
77 77
78 enum mlx5_qp_state { 78 enum mlx5_qp_state {
79 MLX5_QP_STATE_RST 79 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT 80 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR 81 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS 82 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER 83 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD 84 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR 85 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING 86 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED 87 MLX5_QP_STATE_SUSPENDED = 9,
88 MLX5_QP_NUM_STATE, !! 88 MLX5_QP_NUM_STATE
89 MLX5_QP_STATE, <<
90 MLX5_QP_STATE_BAD, <<
91 }; <<
92 <<
93 enum { <<
94 MLX5_SQ_STATE_NA = MLX5_SQC_STA <<
95 MLX5_SQ_NUM_STATE = MLX5_SQ_STAT <<
96 MLX5_RQ_STATE_NA = MLX5_RQC_STA <<
97 MLX5_RQ_NUM_STATE = MLX5_RQ_STAT <<
98 }; 89 };
99 90
100 enum { 91 enum {
101 MLX5_QP_ST_RC 92 MLX5_QP_ST_RC = 0x0,
102 MLX5_QP_ST_UC 93 MLX5_QP_ST_UC = 0x1,
103 MLX5_QP_ST_UD 94 MLX5_QP_ST_UD = 0x2,
104 MLX5_QP_ST_XRC 95 MLX5_QP_ST_XRC = 0x3,
105 MLX5_QP_ST_MLX 96 MLX5_QP_ST_MLX = 0x4,
106 MLX5_QP_ST_DCI 97 MLX5_QP_ST_DCI = 0x5,
107 MLX5_QP_ST_DCT 98 MLX5_QP_ST_DCT = 0x6,
108 MLX5_QP_ST_QP0 99 MLX5_QP_ST_QP0 = 0x7,
109 MLX5_QP_ST_QP1 100 MLX5_QP_ST_QP1 = 0x8,
110 MLX5_QP_ST_RAW_ETHERTYPE 101 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
111 MLX5_QP_ST_RAW_IPV6 102 MLX5_QP_ST_RAW_IPV6 = 0xa,
112 MLX5_QP_ST_SNIFFER 103 MLX5_QP_ST_SNIFFER = 0xb,
113 MLX5_QP_ST_SYNC_UMR 104 MLX5_QP_ST_SYNC_UMR = 0xe,
114 MLX5_QP_ST_PTP_1588 105 MLX5_QP_ST_PTP_1588 = 0xd,
115 MLX5_QP_ST_REG_UMR 106 MLX5_QP_ST_REG_UMR = 0xc,
116 MLX5_QP_ST_MAX 107 MLX5_QP_ST_MAX
117 }; 108 };
118 109
119 enum { 110 enum {
120 MLX5_QP_PM_MIGRATED 111 MLX5_QP_PM_MIGRATED = 0x3,
121 MLX5_QP_PM_ARMED 112 MLX5_QP_PM_ARMED = 0x0,
122 MLX5_QP_PM_REARM 113 MLX5_QP_PM_REARM = 0x1
123 }; 114 };
124 115
125 enum { 116 enum {
126 MLX5_NON_ZERO_RQ = 0x0, !! 117 MLX5_NON_ZERO_RQ = 0 << 24,
127 MLX5_SRQ_RQ = 0x1, !! 118 MLX5_SRQ_RQ = 1 << 24,
128 MLX5_CRQ_RQ = 0x2, !! 119 MLX5_CRQ_RQ = 2 << 24,
129 MLX5_ZERO_LEN_RQ = 0x3 !! 120 MLX5_ZERO_LEN_RQ = 3 << 24
130 }; 121 };
131 122
132 /* TODO REM */ <<
133 enum { 123 enum {
134 /* params1 */ 124 /* params1 */
135 MLX5_QP_BIT_SRE 125 MLX5_QP_BIT_SRE = 1 << 15,
136 MLX5_QP_BIT_SWE 126 MLX5_QP_BIT_SWE = 1 << 14,
137 MLX5_QP_BIT_SAE 127 MLX5_QP_BIT_SAE = 1 << 13,
138 /* params2 */ 128 /* params2 */
139 MLX5_QP_BIT_RRE 129 MLX5_QP_BIT_RRE = 1 << 15,
140 MLX5_QP_BIT_RWE 130 MLX5_QP_BIT_RWE = 1 << 14,
141 MLX5_QP_BIT_RAE 131 MLX5_QP_BIT_RAE = 1 << 13,
142 MLX5_QP_BIT_RIC 132 MLX5_QP_BIT_RIC = 1 << 4,
143 MLX5_QP_BIT_CC_SLAVE_RECV <<
144 MLX5_QP_BIT_CC_SLAVE_SEND <<
145 MLX5_QP_BIT_CC_MASTER <<
146 }; 133 };
147 134
148 enum { 135 enum {
149 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 136 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
150 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 137 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
151 MLX5_WQE_CTRL_SOLICITED = 1 << 138 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
152 MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = <<
153 }; 139 };
154 140
155 enum { 141 enum {
156 MLX5_SEND_WQE_DS = 16, 142 MLX5_SEND_WQE_DS = 16,
157 MLX5_SEND_WQE_BB = 64, 143 MLX5_SEND_WQE_BB = 64,
158 }; 144 };
159 145
160 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE 146 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
161 147
162 enum { 148 enum {
163 MLX5_SEND_WQE_MAX_WQEBBS = 16, 149 MLX5_SEND_WQE_MAX_WQEBBS = 16,
164 }; 150 };
165 151
166 #define MLX5_SEND_WQE_MAX_SIZE (MLX5_SEND_WQE_ <<
167 <<
168 enum { 152 enum {
169 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 153 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
170 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 154 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
171 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 155 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
172 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 156 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
173 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 157 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
174 }; 158 };
175 159
176 enum { 160 enum {
177 MLX5_FENCE_MODE_NONE 161 MLX5_FENCE_MODE_NONE = 0 << 5,
178 MLX5_FENCE_MODE_INITIATOR_SMALL 162 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
179 MLX5_FENCE_MODE_FENCE 163 MLX5_FENCE_MODE_FENCE = 2 << 5,
180 MLX5_FENCE_MODE_STRONG_ORDERING 164 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
181 MLX5_FENCE_MODE_SMALL_AND_FENCE 165 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
182 }; 166 };
183 167
184 enum { 168 enum {
>> 169 MLX5_QP_LAT_SENSITIVE = 1 << 28,
>> 170 MLX5_QP_BLOCK_MCAST = 1 << 30,
>> 171 MLX5_QP_ENABLE_SIG = 1 << 31,
>> 172 };
>> 173
>> 174 enum {
185 MLX5_RCV_DBR = 0, 175 MLX5_RCV_DBR = 0,
186 MLX5_SND_DBR = 1, 176 MLX5_SND_DBR = 1,
187 }; 177 };
188 178
189 enum { 179 enum {
190 MLX5_FLAGS_INLINE = 1<<7, 180 MLX5_FLAGS_INLINE = 1<<7,
191 MLX5_FLAGS_CHECK_FREE = 1<<5, 181 MLX5_FLAGS_CHECK_FREE = 1<<5,
192 }; 182 };
193 183
194 struct mlx5_wqe_fmr_seg { 184 struct mlx5_wqe_fmr_seg {
195 __be32 flags; 185 __be32 flags;
196 __be32 mem_key; 186 __be32 mem_key;
197 __be64 buf_list; 187 __be64 buf_list;
198 __be64 start_addr; 188 __be64 start_addr;
199 __be64 reg_len; 189 __be64 reg_len;
200 __be32 offset; 190 __be32 offset;
201 __be32 page_size; 191 __be32 page_size;
202 u32 reserved[2]; 192 u32 reserved[2];
203 }; 193 };
204 194
205 struct mlx5_wqe_ctrl_seg { 195 struct mlx5_wqe_ctrl_seg {
206 __be32 opmod_idx_opco 196 __be32 opmod_idx_opcode;
207 __be32 qpn_ds; 197 __be32 qpn_ds;
208 <<
209 struct_group(trailer, <<
210 <<
211 u8 signature; 198 u8 signature;
212 u8 rsvd[2]; 199 u8 rsvd[2];
213 u8 fm_ce_se; 200 u8 fm_ce_se;
214 union { !! 201 __be32 imm;
215 __be32 general_id; <<
216 __be32 imm; <<
217 __be32 umr_mkey; <<
218 __be32 tis_tir_num; <<
219 }; <<
220 <<
221 ); /* end of trailer group */ <<
222 }; 202 };
223 203
224 #define MLX5_WQE_CTRL_DS_MASK 0x3f 204 #define MLX5_WQE_CTRL_DS_MASK 0x3f
225 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 205 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
226 #define MLX5_WQE_CTRL_QPN_SHIFT 8 206 #define MLX5_WQE_CTRL_QPN_SHIFT 8
227 #define MLX5_WQE_DS_UNITS 16 207 #define MLX5_WQE_DS_UNITS 16
228 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 208 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
229 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff0 209 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
230 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 210 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
231 211
232 enum { 212 enum {
233 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 213 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
234 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 214 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
235 MLX5_ETH_WQE_L3_CSUM = 1 << 215 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
236 MLX5_ETH_WQE_L4_CSUM = 1 << 216 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
237 }; 217 };
238 218
239 enum { <<
240 MLX5_ETH_WQE_SVLAN = 1 << <<
241 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSO <<
242 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSO <<
243 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSO <<
244 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSO <<
245 MLX5_ETH_WQE_INSERT_TRAILER = 1 << <<
246 MLX5_ETH_WQE_INSERT_VLAN = 1 << <<
247 }; <<
248 <<
249 enum { <<
250 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << <<
251 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << <<
252 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << <<
253 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << <<
254 }; <<
255 <<
256 enum { <<
257 MLX5_ETH_WQE_FT_META_IPSEC = BIT(0), <<
258 MLX5_ETH_WQE_FT_META_MACSEC = BIT(1), <<
259 }; <<
260 <<
261 struct mlx5_wqe_eth_seg { 219 struct mlx5_wqe_eth_seg {
262 u8 swp_outer_l4_offset; !! 220 u8 rsvd0[4];
263 u8 swp_outer_l3_offset; <<
264 u8 swp_inner_l4_offset; <<
265 u8 swp_inner_l3_offset; <<
266 u8 cs_flags; 221 u8 cs_flags;
267 u8 swp_flags; !! 222 u8 rsvd1;
268 __be16 mss; 223 __be16 mss;
269 __be32 flow_table_metadata; !! 224 __be32 rsvd2;
270 union { !! 225 __be16 inline_hdr_sz;
271 struct { !! 226 u8 inline_hdr_start[2];
272 __be16 sz; <<
273 union { <<
274 u8 start[2 <<
275 DECLARE_FLEX_A <<
276 }; <<
277 } inline_hdr; <<
278 struct { <<
279 __be16 type; <<
280 __be16 vlan_tci; <<
281 } insert; <<
282 __be32 trailer; <<
283 }; <<
284 }; 227 };
285 228
286 struct mlx5_wqe_xrc_seg { 229 struct mlx5_wqe_xrc_seg {
287 __be32 xrc_srqn; 230 __be32 xrc_srqn;
288 u8 rsvd[12]; 231 u8 rsvd[12];
289 }; 232 };
290 233
291 struct mlx5_wqe_masked_atomic_seg { 234 struct mlx5_wqe_masked_atomic_seg {
292 __be64 swap_add; 235 __be64 swap_add;
293 __be64 compare; 236 __be64 compare;
294 __be64 swap_add_mask; 237 __be64 swap_add_mask;
295 __be64 compare_mask; 238 __be64 compare_mask;
296 }; 239 };
297 240
298 struct mlx5_base_av { <<
299 union { <<
300 struct { <<
301 __be32 qkey; <<
302 __be32 reserved; <<
303 } qkey; <<
304 __be64 dc_key; <<
305 } key; <<
306 __be32 dqp_dct; <<
307 u8 stat_rate_sl; <<
308 u8 fl_mlid; <<
309 union { <<
310 __be16 rlid; <<
311 __be16 udp_sport; <<
312 }; <<
313 }; <<
314 <<
315 struct mlx5_av { 241 struct mlx5_av {
316 union { 242 union {
317 struct { 243 struct {
318 __be32 qkey; 244 __be32 qkey;
319 __be32 reserved; 245 __be32 reserved;
320 } qkey; 246 } qkey;
321 __be64 dc_key; 247 __be64 dc_key;
322 } key; 248 } key;
323 __be32 dqp_dct; 249 __be32 dqp_dct;
324 u8 stat_rate_sl; 250 u8 stat_rate_sl;
325 u8 fl_mlid; 251 u8 fl_mlid;
326 union { !! 252 __be16 rlid;
327 __be16 rlid; !! 253 u8 reserved0[10];
328 __be16 udp_sport; <<
329 }; <<
330 u8 reserved0[4]; <<
331 u8 rmac[6]; <<
332 u8 tclass; 254 u8 tclass;
333 u8 hop_limit; 255 u8 hop_limit;
334 __be32 grh_gid_fl; 256 __be32 grh_gid_fl;
335 u8 rgid[16]; 257 u8 rgid[16];
336 }; 258 };
337 259
338 struct mlx5_ib_ah { <<
339 struct ib_ah ibah; <<
340 struct mlx5_av av; <<
341 u8 xmit_port; <<
342 }; <<
343 <<
344 static inline struct mlx5_ib_ah *to_mah(struct <<
345 { <<
346 return container_of(ibah, struct mlx5_ <<
347 } <<
348 <<
349 struct mlx5_wqe_datagram_seg { 260 struct mlx5_wqe_datagram_seg {
350 struct mlx5_av av; 261 struct mlx5_av av;
351 }; 262 };
352 263
353 struct mlx5_wqe_raddr_seg { 264 struct mlx5_wqe_raddr_seg {
354 __be64 raddr; 265 __be64 raddr;
355 __be32 rkey; 266 __be32 rkey;
356 u32 reserved; 267 u32 reserved;
357 }; 268 };
358 269
359 struct mlx5_wqe_atomic_seg { 270 struct mlx5_wqe_atomic_seg {
360 __be64 swap_add; 271 __be64 swap_add;
361 __be64 compare; 272 __be64 compare;
362 }; 273 };
363 274
364 struct mlx5_wqe_data_seg { 275 struct mlx5_wqe_data_seg {
365 __be32 byte_count; 276 __be32 byte_count;
366 __be32 lkey; 277 __be32 lkey;
367 __be64 addr; 278 __be64 addr;
368 }; 279 };
369 280
370 struct mlx5_wqe_umr_ctrl_seg { 281 struct mlx5_wqe_umr_ctrl_seg {
371 u8 flags; 282 u8 flags;
372 u8 rsvd0[3]; 283 u8 rsvd0[3];
373 __be16 xlt_octowords; !! 284 __be16 klm_octowords;
374 union { !! 285 __be16 bsf_octowords;
375 __be16 xlt_offset; <<
376 __be16 bsf_octowords; <<
377 }; <<
378 __be64 mkey_mask; 286 __be64 mkey_mask;
379 __be32 xlt_offset_47_16; !! 287 u8 rsvd1[32];
380 u8 rsvd1[28]; <<
381 }; 288 };
382 289
383 struct mlx5_seg_set_psv { 290 struct mlx5_seg_set_psv {
384 __be32 psv_num; 291 __be32 psv_num;
385 __be16 syndrome; 292 __be16 syndrome;
386 __be16 status; 293 __be16 status;
387 __be32 transient_sig; 294 __be32 transient_sig;
388 __be32 ref_tag; 295 __be32 ref_tag;
389 }; 296 };
390 297
391 struct mlx5_seg_get_psv { 298 struct mlx5_seg_get_psv {
392 u8 rsvd[19]; 299 u8 rsvd[19];
393 u8 num_psv; 300 u8 num_psv;
394 __be32 l_key; 301 __be32 l_key;
395 __be64 va; 302 __be64 va;
396 __be32 psv_index[4]; 303 __be32 psv_index[4];
397 }; 304 };
398 305
399 struct mlx5_seg_check_psv { 306 struct mlx5_seg_check_psv {
400 u8 rsvd0[2]; 307 u8 rsvd0[2];
401 __be16 err_coalescing_op; 308 __be16 err_coalescing_op;
402 u8 rsvd1[2]; 309 u8 rsvd1[2];
403 __be16 xport_err_op; 310 __be16 xport_err_op;
404 u8 rsvd2[2]; 311 u8 rsvd2[2];
405 __be16 xport_err_mask; 312 __be16 xport_err_mask;
406 u8 rsvd3[7]; 313 u8 rsvd3[7];
407 u8 num_psv; 314 u8 num_psv;
408 __be32 l_key; 315 __be32 l_key;
409 __be64 va; 316 __be64 va;
410 __be32 psv_index[4]; 317 __be32 psv_index[4];
411 }; 318 };
412 319
413 struct mlx5_rwqe_sig { 320 struct mlx5_rwqe_sig {
414 u8 rsvd0[4]; 321 u8 rsvd0[4];
415 u8 signature; 322 u8 signature;
416 u8 rsvd1[11]; 323 u8 rsvd1[11];
417 }; 324 };
418 325
419 struct mlx5_wqe_signature_seg { 326 struct mlx5_wqe_signature_seg {
420 u8 rsvd0[4]; 327 u8 rsvd0[4];
421 u8 signature; 328 u8 signature;
422 u8 rsvd1[11]; 329 u8 rsvd1[11];
423 }; 330 };
424 331
425 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x 332 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
426 333
427 struct mlx5_wqe_inline_seg { 334 struct mlx5_wqe_inline_seg {
428 __be32 byte_count; 335 __be32 byte_count;
429 __be32 data[]; <<
430 }; 336 };
431 337
432 enum mlx5_sig_type { 338 enum mlx5_sig_type {
433 MLX5_DIF_CRC = 0x1, 339 MLX5_DIF_CRC = 0x1,
434 MLX5_DIF_IPCS = 0x2, 340 MLX5_DIF_IPCS = 0x2,
435 }; 341 };
436 342
437 struct mlx5_bsf_inl { 343 struct mlx5_bsf_inl {
438 __be16 vld_refresh; 344 __be16 vld_refresh;
439 __be16 dif_apptag; 345 __be16 dif_apptag;
440 __be32 dif_reftag; 346 __be32 dif_reftag;
441 u8 sig_type; 347 u8 sig_type;
442 u8 rp_inv_seed; 348 u8 rp_inv_seed;
443 u8 rsvd[3]; 349 u8 rsvd[3];
444 u8 dif_inc_ref_guard_chec 350 u8 dif_inc_ref_guard_check;
445 __be16 dif_app_bitmask_check; 351 __be16 dif_app_bitmask_check;
446 }; 352 };
447 353
448 struct mlx5_bsf { 354 struct mlx5_bsf {
449 struct mlx5_bsf_basic { 355 struct mlx5_bsf_basic {
450 u8 bsf_size_sbs; 356 u8 bsf_size_sbs;
451 u8 check_byte_mas 357 u8 check_byte_mask;
452 union { 358 union {
453 u8 copy_byte_mask 359 u8 copy_byte_mask;
454 u8 bs_selector; 360 u8 bs_selector;
455 u8 rsvd_wflags; 361 u8 rsvd_wflags;
456 } wire; 362 } wire;
457 union { 363 union {
458 u8 bs_selector; 364 u8 bs_selector;
459 u8 rsvd_mflags; 365 u8 rsvd_mflags;
460 } mem; 366 } mem;
461 __be32 raw_data_size; 367 __be32 raw_data_size;
462 __be32 w_bfs_psv; 368 __be32 w_bfs_psv;
463 __be32 m_bfs_psv; 369 __be32 m_bfs_psv;
464 } basic; 370 } basic;
465 struct mlx5_bsf_ext { 371 struct mlx5_bsf_ext {
466 __be32 t_init_gen_pro 372 __be32 t_init_gen_pro_size;
467 __be32 rsvd_epi_size; 373 __be32 rsvd_epi_size;
468 __be32 w_tfs_psv; 374 __be32 w_tfs_psv;
469 __be32 m_tfs_psv; 375 __be32 m_tfs_psv;
470 } ext; 376 } ext;
471 struct mlx5_bsf_inl w_inl; 377 struct mlx5_bsf_inl w_inl;
472 struct mlx5_bsf_inl m_inl; 378 struct mlx5_bsf_inl m_inl;
473 }; 379 };
474 380
475 struct mlx5_mtt { <<
476 __be64 ptag; <<
477 }; <<
478 <<
479 struct mlx5_klm { 381 struct mlx5_klm {
480 __be32 bcount; 382 __be32 bcount;
481 __be32 key; 383 __be32 key;
482 __be64 va; 384 __be64 va;
483 }; 385 };
484 386
485 struct mlx5_ksm { <<
486 __be32 reserved; <<
487 __be32 key; <<
488 __be64 va; <<
489 }; <<
490 <<
491 struct mlx5_stride_block_entry { 387 struct mlx5_stride_block_entry {
492 __be16 stride; 388 __be16 stride;
493 __be16 bcount; 389 __be16 bcount;
494 __be32 key; 390 __be32 key;
495 __be64 va; 391 __be64 va;
496 }; 392 };
497 393
498 struct mlx5_stride_block_ctrl_seg { 394 struct mlx5_stride_block_ctrl_seg {
499 __be32 bcount_per_cycle; 395 __be32 bcount_per_cycle;
500 __be32 op; 396 __be32 op;
501 __be32 repeat_count; 397 __be32 repeat_count;
502 u16 rsvd; 398 u16 rsvd;
503 __be16 num_entries; 399 __be16 num_entries;
504 }; 400 };
505 401
506 struct mlx5_wqe_flow_update_ctrl_seg { !! 402 enum mlx5_pagefault_flags {
507 __be32 flow_idx_update; !! 403 MLX5_PFAULT_REQUESTOR = 1 << 0,
508 __be32 dest_handle; !! 404 MLX5_PFAULT_WRITE = 1 << 1,
509 u8 reserved0[40]; !! 405 MLX5_PFAULT_RDMA = 1 << 2,
510 }; 406 };
511 407
512 struct mlx5_wqe_header_modify_argument_update_ !! 408 /* Contains the details of a pagefault. */
513 u8 argument_list[64]; !! 409 struct mlx5_pagefault {
>> 410 u32 bytes_committed;
>> 411 u8 event_subtype;
>> 412 enum mlx5_pagefault_flags flags;
>> 413 union {
>> 414 /* Initiator or send message responder pagefault details. */
>> 415 struct {
>> 416 /* Received packet size, only valid for responders. */
>> 417 u32 packet_size;
>> 418 /*
>> 419 * WQE index. Refers to either the send queue or
>> 420 * receive queue, according to event_subtype.
>> 421 */
>> 422 u16 wqe_index;
>> 423 } wqe;
>> 424 /* RDMA responder pagefault details */
>> 425 struct {
>> 426 u32 r_key;
>> 427 /*
>> 428 * Received packet size, minimal size page fault
>> 429 * resolution required for forward progress.
>> 430 */
>> 431 u32 packet_size;
>> 432 u32 rdma_op_len;
>> 433 u64 rdma_va;
>> 434 } rdma;
>> 435 };
514 }; 436 };
515 437
516 struct mlx5_core_qp { 438 struct mlx5_core_qp {
517 struct mlx5_core_rsc_common common 439 struct mlx5_core_rsc_common common; /* must be first */
518 void (*event) (struct mlx5_c 440 void (*event) (struct mlx5_core_qp *, int);
>> 441 void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *);
519 int qpn; 442 int qpn;
520 struct mlx5_rsc_debug *dbg; 443 struct mlx5_rsc_debug *dbg;
521 int pid; 444 int pid;
522 u16 uid; <<
523 }; 445 };
524 446
525 struct mlx5_core_dct { !! 447 struct mlx5_qp_path {
526 struct mlx5_core_qp mqp; !! 448 u8 fl;
527 struct completion drained; !! 449 u8 rsvd3;
>> 450 u8 free_ar;
>> 451 u8 pkey_index;
>> 452 u8 rsvd0;
>> 453 u8 grh_mlid;
>> 454 __be16 rlid;
>> 455 u8 ackto_lt;
>> 456 u8 mgid_index;
>> 457 u8 static_rate;
>> 458 u8 hop_limit;
>> 459 __be32 tclass_flowlabel;
>> 460 u8 rgid[16];
>> 461 u8 rsvd1[4];
>> 462 u8 sl;
>> 463 u8 port;
>> 464 u8 rsvd2[6];
528 }; 465 };
529 466
>> 467 struct mlx5_qp_context {
>> 468 __be32 flags;
>> 469 __be32 flags_pd;
>> 470 u8 mtu_msgmax;
>> 471 u8 rq_size_stride;
>> 472 __be16 sq_crq_size;
>> 473 __be32 qp_counter_set_usr_page;
>> 474 __be32 wire_qpn;
>> 475 __be32 log_pg_sz_remote_qpn;
>> 476 struct mlx5_qp_path pri_path;
>> 477 struct mlx5_qp_path alt_path;
>> 478 __be32 params1;
>> 479 u8 reserved2[4];
>> 480 __be32 next_send_psn;
>> 481 __be32 cqn_send;
>> 482 u8 reserved3[8];
>> 483 __be32 last_acked_psn;
>> 484 __be32 ssn;
>> 485 __be32 params2;
>> 486 __be32 rnr_nextrecvpsn;
>> 487 __be32 xrcd;
>> 488 __be32 cqn_recv;
>> 489 __be64 db_rec_addr;
>> 490 __be32 qkey;
>> 491 __be32 rq_type_srqn;
>> 492 __be32 rmsn;
>> 493 __be16 hw_sq_wqe_counter;
>> 494 __be16 sw_sq_wqe_counter;
>> 495 __be16 hw_rcyclic_byte_counter;
>> 496 __be16 hw_rq_counter;
>> 497 __be16 sw_rcyclic_byte_counter;
>> 498 __be16 sw_rq_counter;
>> 499 u8 rsvd0[5];
>> 500 u8 cgs;
>> 501 u8 cs_req;
>> 502 u8 cs_res;
>> 503 __be64 dc_access_key;
>> 504 u8 rsvd1[24];
>> 505 };
>> 506
>> 507 struct mlx5_create_qp_mbox_in {
>> 508 struct mlx5_inbox_hdr hdr;
>> 509 __be32 input_qpn;
>> 510 u8 rsvd0[4];
>> 511 __be32 opt_param_mask;
>> 512 u8 rsvd1[4];
>> 513 struct mlx5_qp_context ctx;
>> 514 u8 rsvd3[16];
>> 515 __be64 pas[0];
>> 516 };
>> 517
>> 518 struct mlx5_create_qp_mbox_out {
>> 519 struct mlx5_outbox_hdr hdr;
>> 520 __be32 qpn;
>> 521 u8 rsvd0[4];
>> 522 };
>> 523
>> 524 struct mlx5_destroy_qp_mbox_in {
>> 525 struct mlx5_inbox_hdr hdr;
>> 526 __be32 qpn;
>> 527 u8 rsvd0[4];
>> 528 };
>> 529
>> 530 struct mlx5_destroy_qp_mbox_out {
>> 531 struct mlx5_outbox_hdr hdr;
>> 532 u8 rsvd0[8];
>> 533 };
>> 534
>> 535 struct mlx5_modify_qp_mbox_in {
>> 536 struct mlx5_inbox_hdr hdr;
>> 537 __be32 qpn;
>> 538 u8 rsvd0[4];
>> 539 __be32 optparam;
>> 540 u8 rsvd1[4];
>> 541 struct mlx5_qp_context ctx;
>> 542 u8 rsvd2[16];
>> 543 };
>> 544
>> 545 struct mlx5_modify_qp_mbox_out {
>> 546 struct mlx5_outbox_hdr hdr;
>> 547 u8 rsvd0[8];
>> 548 };
>> 549
>> 550 struct mlx5_query_qp_mbox_in {
>> 551 struct mlx5_inbox_hdr hdr;
>> 552 __be32 qpn;
>> 553 u8 rsvd[4];
>> 554 };
>> 555
>> 556 struct mlx5_query_qp_mbox_out {
>> 557 struct mlx5_outbox_hdr hdr;
>> 558 u8 rsvd1[8];
>> 559 __be32 optparam;
>> 560 u8 rsvd0[4];
>> 561 struct mlx5_qp_context ctx;
>> 562 u8 rsvd2[16];
>> 563 __be64 pas[0];
>> 564 };
>> 565
>> 566 struct mlx5_conf_sqp_mbox_in {
>> 567 struct mlx5_inbox_hdr hdr;
>> 568 __be32 qpn;
>> 569 u8 rsvd[3];
>> 570 u8 type;
>> 571 };
>> 572
>> 573 struct mlx5_conf_sqp_mbox_out {
>> 574 struct mlx5_outbox_hdr hdr;
>> 575 u8 rsvd[8];
>> 576 };
>> 577
>> 578 struct mlx5_alloc_xrcd_mbox_in {
>> 579 struct mlx5_inbox_hdr hdr;
>> 580 u8 rsvd[8];
>> 581 };
>> 582
>> 583 struct mlx5_alloc_xrcd_mbox_out {
>> 584 struct mlx5_outbox_hdr hdr;
>> 585 __be32 xrcdn;
>> 586 u8 rsvd[4];
>> 587 };
>> 588
>> 589 struct mlx5_dealloc_xrcd_mbox_in {
>> 590 struct mlx5_inbox_hdr hdr;
>> 591 __be32 xrcdn;
>> 592 u8 rsvd[4];
>> 593 };
>> 594
>> 595 struct mlx5_dealloc_xrcd_mbox_out {
>> 596 struct mlx5_outbox_hdr hdr;
>> 597 u8 rsvd[8];
>> 598 };
>> 599
>> 600 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
>> 601 {
>> 602 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
>> 603 }
>> 604
>> 605 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
>> 606 {
>> 607 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
>> 608 }
>> 609
>> 610 struct mlx5_page_fault_resume_mbox_in {
>> 611 struct mlx5_inbox_hdr hdr;
>> 612 __be32 flags_qpn;
>> 613 u8 reserved[4];
>> 614 };
>> 615
>> 616 struct mlx5_page_fault_resume_mbox_out {
>> 617 struct mlx5_outbox_hdr hdr;
>> 618 u8 rsvd[8];
>> 619 };
>> 620
>> 621 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
>> 622 struct mlx5_core_qp *qp,
>> 623 struct mlx5_create_qp_mbox_in *in,
>> 624 int inlen);
>> 625 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
>> 626 enum mlx5_qp_state new_state,
>> 627 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
>> 628 struct mlx5_core_qp *qp);
>> 629 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
>> 630 struct mlx5_core_qp *qp);
>> 631 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
>> 632 struct mlx5_query_qp_mbox_out *out, int outlen);
>> 633
>> 634 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
>> 635 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
>> 636 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
>> 637 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
530 int mlx5_debug_qp_add(struct mlx5_core_dev *de 638 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
531 void mlx5_debug_qp_remove(struct mlx5_core_dev 639 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
>> 640 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
>> 641 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn,
>> 642 u8 context, int error);
>> 643 #endif
532 644
533 static inline const char *mlx5_qp_type_str(int 645 static inline const char *mlx5_qp_type_str(int type)
534 { 646 {
535 switch (type) { 647 switch (type) {
536 case MLX5_QP_ST_RC: return "RC"; 648 case MLX5_QP_ST_RC: return "RC";
537 case MLX5_QP_ST_UC: return "C"; 649 case MLX5_QP_ST_UC: return "C";
538 case MLX5_QP_ST_UD: return "UD"; 650 case MLX5_QP_ST_UD: return "UD";
539 case MLX5_QP_ST_XRC: return "XRC"; 651 case MLX5_QP_ST_XRC: return "XRC";
540 case MLX5_QP_ST_MLX: return "MLX"; 652 case MLX5_QP_ST_MLX: return "MLX";
541 case MLX5_QP_ST_QP0: return "QP0"; 653 case MLX5_QP_ST_QP0: return "QP0";
542 case MLX5_QP_ST_QP1: return "QP1"; 654 case MLX5_QP_ST_QP1: return "QP1";
543 case MLX5_QP_ST_RAW_ETHERTYPE: return 655 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
544 case MLX5_QP_ST_RAW_IPV6: return "RAW_ 656 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
545 case MLX5_QP_ST_SNIFFER: return "SNIFF 657 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
546 case MLX5_QP_ST_SYNC_UMR: return "SYNC 658 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
547 case MLX5_QP_ST_PTP_1588: return "PTP_ 659 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
548 case MLX5_QP_ST_REG_UMR: return "REG_U 660 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
549 default: return "Invalid transport typ 661 default: return "Invalid transport type";
550 } 662 }
551 } 663 }
552 664
553 static inline const char *mlx5_qp_state_str(in 665 static inline const char *mlx5_qp_state_str(int state)
554 { 666 {
555 switch (state) { 667 switch (state) {
556 case MLX5_QP_STATE_RST: 668 case MLX5_QP_STATE_RST:
557 return "RST"; 669 return "RST";
558 case MLX5_QP_STATE_INIT: 670 case MLX5_QP_STATE_INIT:
559 return "INIT"; 671 return "INIT";
560 case MLX5_QP_STATE_RTR: 672 case MLX5_QP_STATE_RTR:
561 return "RTR"; 673 return "RTR";
562 case MLX5_QP_STATE_RTS: 674 case MLX5_QP_STATE_RTS:
563 return "RTS"; 675 return "RTS";
564 case MLX5_QP_STATE_SQER: 676 case MLX5_QP_STATE_SQER:
565 return "SQER"; 677 return "SQER";
566 case MLX5_QP_STATE_SQD: 678 case MLX5_QP_STATE_SQD:
567 return "SQD"; 679 return "SQD";
568 case MLX5_QP_STATE_ERR: 680 case MLX5_QP_STATE_ERR:
569 return "ERR"; 681 return "ERR";
570 case MLX5_QP_STATE_SQ_DRAINING: 682 case MLX5_QP_STATE_SQ_DRAINING:
571 return "SQ_DRAINING"; 683 return "SQ_DRAINING";
572 case MLX5_QP_STATE_SUSPENDED: 684 case MLX5_QP_STATE_SUSPENDED:
573 return "SUSPENDED"; 685 return "SUSPENDED";
574 default: return "Invalid QP state"; 686 default: return "Invalid QP state";
575 } 687 }
576 } <<
577 <<
578 static inline int mlx5_get_qp_default_ts(struc <<
579 { <<
580 u8 supported_ts_cap = mlx5_get_roce_st <<
581 MLX5_CAP_ROCE(de <<
582 MLX5_CAP_GEN(dev <<
583 <<
584 return supported_ts_cap ? MLX5_TIMESTA <<
585 MLX5_TIMESTAMP_FORMAT_FREE_RUNN <<
586 } 688 }
587 689
588 #endif /* MLX5_QP_H */ 690 #endif /* MLX5_QP_H */
589 691
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