1 /* 1 /*
2 * Copyright (c) 2013-2015, Mellanox Technolog 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 * 3 *
4 * This software is available to you under a c 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed un 5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, ava 6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this sourc 7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below: 8 * OpenIB.org BSD license below:
9 * 9 *
10 * Redistribution and use in source and bi 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted pro 11 * without modification, are permitted provided that the following
12 * conditions are met: 12 * conditions are met:
13 * 13 *
14 * - Redistributions of source code must 14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of condi 15 * copyright notice, this list of conditions and the following
16 * disclaimer. 16 * disclaimer.
17 * 17 *
18 * - Redistributions in binary form must 18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of condi 19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/ 20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution. 21 * provided with the distribution.
22 * 22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMIT 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR P 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTH 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER L 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARIS 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 */ 31 */
32 32
33 #ifndef MLX5_QP_H 33 #ifndef MLX5_QP_H
34 #define MLX5_QP_H 34 #define MLX5_QP_H
35 35
36 #include <linux/mlx5/device.h> 36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h> 37 #include <linux/mlx5/driver.h>
38 38
39 #define MLX5_TERMINATE_SCATTER_LIST_LKEY cpu_t !! 39 #define MLX5_INVALID_LKEY 0x100
40 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV ( !! 40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE <<
42 #define MLX5_DIF_SIZE 8 41 #define MLX5_DIF_SIZE 8
43 #define MLX5_STRIDE_BLOCK_OP 0x400 42 #define MLX5_STRIDE_BLOCK_OP 0x400
44 #define MLX5_CPY_GRD_MASK 0xc0 43 #define MLX5_CPY_GRD_MASK 0xc0
45 #define MLX5_CPY_APP_MASK 0x30 44 #define MLX5_CPY_APP_MASK 0x30
46 #define MLX5_CPY_REF_MASK 0x0f 45 #define MLX5_CPY_REF_MASK 0x0f
47 #define MLX5_BSF_INC_REFTAG (1 << 6) 46 #define MLX5_BSF_INC_REFTAG (1 << 6)
48 #define MLX5_BSF_INL_VALID (1 << 15) 47 #define MLX5_BSF_INL_VALID (1 << 15)
49 #define MLX5_BSF_REFRESH_DIF (1 << 14) 48 #define MLX5_BSF_REFRESH_DIF (1 << 14)
50 #define MLX5_BSF_REPEAT_BLOCK (1 << 7) 49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
51 #define MLX5_BSF_APPTAG_ESCAPE 0x1 50 #define MLX5_BSF_APPTAG_ESCAPE 0x1
52 #define MLX5_BSF_APPREF_ESCAPE 0x2 51 #define MLX5_BSF_APPREF_ESCAPE 0x2
53 52
54 enum mlx5_qp_optpar { 53 enum mlx5_qp_optpar {
55 MLX5_QP_OPTPAR_ALT_ADDR_PATH 54 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
56 MLX5_QP_OPTPAR_RRE 55 MLX5_QP_OPTPAR_RRE = 1 << 1,
57 MLX5_QP_OPTPAR_RAE 56 MLX5_QP_OPTPAR_RAE = 1 << 2,
58 MLX5_QP_OPTPAR_RWE 57 MLX5_QP_OPTPAR_RWE = 1 << 3,
59 MLX5_QP_OPTPAR_PKEY_INDEX 58 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
60 MLX5_QP_OPTPAR_Q_KEY 59 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
61 MLX5_QP_OPTPAR_RNR_TIMEOUT 60 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH 61 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
63 MLX5_QP_OPTPAR_SRA_MAX 62 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
64 MLX5_QP_OPTPAR_RRA_MAX 63 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
65 MLX5_QP_OPTPAR_PM_STATE 64 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
66 MLX5_QP_OPTPAR_RETRY_COUNT 65 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
67 MLX5_QP_OPTPAR_RNR_RETRY 66 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
68 MLX5_QP_OPTPAR_ACK_TIMEOUT 67 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
69 MLX5_QP_OPTPAR_LAG_TX_AFF <<
70 MLX5_QP_OPTPAR_PRI_PORT 68 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
71 MLX5_QP_OPTPAR_SRQN 69 MLX5_QP_OPTPAR_SRQN = 1 << 18,
72 MLX5_QP_OPTPAR_CQN_RCV 70 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
73 MLX5_QP_OPTPAR_DC_HS 71 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
74 MLX5_QP_OPTPAR_DC_KEY 72 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
75 MLX5_QP_OPTPAR_COUNTER_SET_ID <<
76 }; 73 };
77 74
78 enum mlx5_qp_state { 75 enum mlx5_qp_state {
79 MLX5_QP_STATE_RST 76 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT 77 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR 78 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS 79 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER 80 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD 81 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR 82 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING 83 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED 84 MLX5_QP_STATE_SUSPENDED = 9,
88 MLX5_QP_NUM_STATE, 85 MLX5_QP_NUM_STATE,
89 MLX5_QP_STATE, 86 MLX5_QP_STATE,
90 MLX5_QP_STATE_BAD, 87 MLX5_QP_STATE_BAD,
91 }; 88 };
92 89
93 enum { 90 enum {
94 MLX5_SQ_STATE_NA = MLX5_SQC_STA 91 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
95 MLX5_SQ_NUM_STATE = MLX5_SQ_STAT 92 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
96 MLX5_RQ_STATE_NA = MLX5_RQC_STA 93 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
97 MLX5_RQ_NUM_STATE = MLX5_RQ_STAT 94 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
98 }; 95 };
99 96
100 enum { 97 enum {
101 MLX5_QP_ST_RC 98 MLX5_QP_ST_RC = 0x0,
102 MLX5_QP_ST_UC 99 MLX5_QP_ST_UC = 0x1,
103 MLX5_QP_ST_UD 100 MLX5_QP_ST_UD = 0x2,
104 MLX5_QP_ST_XRC 101 MLX5_QP_ST_XRC = 0x3,
105 MLX5_QP_ST_MLX 102 MLX5_QP_ST_MLX = 0x4,
106 MLX5_QP_ST_DCI 103 MLX5_QP_ST_DCI = 0x5,
107 MLX5_QP_ST_DCT 104 MLX5_QP_ST_DCT = 0x6,
108 MLX5_QP_ST_QP0 105 MLX5_QP_ST_QP0 = 0x7,
109 MLX5_QP_ST_QP1 106 MLX5_QP_ST_QP1 = 0x8,
110 MLX5_QP_ST_RAW_ETHERTYPE 107 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
111 MLX5_QP_ST_RAW_IPV6 108 MLX5_QP_ST_RAW_IPV6 = 0xa,
112 MLX5_QP_ST_SNIFFER 109 MLX5_QP_ST_SNIFFER = 0xb,
113 MLX5_QP_ST_SYNC_UMR 110 MLX5_QP_ST_SYNC_UMR = 0xe,
114 MLX5_QP_ST_PTP_1588 111 MLX5_QP_ST_PTP_1588 = 0xd,
115 MLX5_QP_ST_REG_UMR 112 MLX5_QP_ST_REG_UMR = 0xc,
116 MLX5_QP_ST_MAX 113 MLX5_QP_ST_MAX
117 }; 114 };
118 115
119 enum { 116 enum {
120 MLX5_QP_PM_MIGRATED 117 MLX5_QP_PM_MIGRATED = 0x3,
121 MLX5_QP_PM_ARMED 118 MLX5_QP_PM_ARMED = 0x0,
122 MLX5_QP_PM_REARM 119 MLX5_QP_PM_REARM = 0x1
123 }; 120 };
124 121
125 enum { 122 enum {
126 MLX5_NON_ZERO_RQ = 0x0, 123 MLX5_NON_ZERO_RQ = 0x0,
127 MLX5_SRQ_RQ = 0x1, 124 MLX5_SRQ_RQ = 0x1,
128 MLX5_CRQ_RQ = 0x2, 125 MLX5_CRQ_RQ = 0x2,
129 MLX5_ZERO_LEN_RQ = 0x3 126 MLX5_ZERO_LEN_RQ = 0x3
130 }; 127 };
131 128
132 /* TODO REM */ 129 /* TODO REM */
133 enum { 130 enum {
134 /* params1 */ 131 /* params1 */
135 MLX5_QP_BIT_SRE 132 MLX5_QP_BIT_SRE = 1 << 15,
136 MLX5_QP_BIT_SWE 133 MLX5_QP_BIT_SWE = 1 << 14,
137 MLX5_QP_BIT_SAE 134 MLX5_QP_BIT_SAE = 1 << 13,
138 /* params2 */ 135 /* params2 */
139 MLX5_QP_BIT_RRE 136 MLX5_QP_BIT_RRE = 1 << 15,
140 MLX5_QP_BIT_RWE 137 MLX5_QP_BIT_RWE = 1 << 14,
141 MLX5_QP_BIT_RAE 138 MLX5_QP_BIT_RAE = 1 << 13,
142 MLX5_QP_BIT_RIC 139 MLX5_QP_BIT_RIC = 1 << 4,
143 MLX5_QP_BIT_CC_SLAVE_RECV 140 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
144 MLX5_QP_BIT_CC_SLAVE_SEND 141 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
145 MLX5_QP_BIT_CC_MASTER 142 MLX5_QP_BIT_CC_MASTER = 1 << 0
146 }; 143 };
147 144
148 enum { 145 enum {
149 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 146 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
150 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 147 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
151 MLX5_WQE_CTRL_SOLICITED = 1 << 148 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
152 MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = <<
153 }; 149 };
154 150
155 enum { 151 enum {
156 MLX5_SEND_WQE_DS = 16, 152 MLX5_SEND_WQE_DS = 16,
157 MLX5_SEND_WQE_BB = 64, 153 MLX5_SEND_WQE_BB = 64,
158 }; 154 };
159 155
160 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE 156 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
161 157
162 enum { 158 enum {
163 MLX5_SEND_WQE_MAX_WQEBBS = 16, 159 MLX5_SEND_WQE_MAX_WQEBBS = 16,
164 }; 160 };
165 161
166 #define MLX5_SEND_WQE_MAX_SIZE (MLX5_SEND_WQE_ <<
167 <<
168 enum { 162 enum {
169 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 163 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
170 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 164 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
171 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 165 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
172 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 166 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
173 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 167 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
174 }; 168 };
175 169
176 enum { 170 enum {
177 MLX5_FENCE_MODE_NONE 171 MLX5_FENCE_MODE_NONE = 0 << 5,
178 MLX5_FENCE_MODE_INITIATOR_SMALL 172 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
179 MLX5_FENCE_MODE_FENCE 173 MLX5_FENCE_MODE_FENCE = 2 << 5,
180 MLX5_FENCE_MODE_STRONG_ORDERING 174 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
181 MLX5_FENCE_MODE_SMALL_AND_FENCE 175 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
182 }; 176 };
183 177
184 enum { 178 enum {
185 MLX5_RCV_DBR = 0, 179 MLX5_RCV_DBR = 0,
186 MLX5_SND_DBR = 1, 180 MLX5_SND_DBR = 1,
187 }; 181 };
188 182
189 enum { 183 enum {
190 MLX5_FLAGS_INLINE = 1<<7, 184 MLX5_FLAGS_INLINE = 1<<7,
191 MLX5_FLAGS_CHECK_FREE = 1<<5, 185 MLX5_FLAGS_CHECK_FREE = 1<<5,
192 }; 186 };
193 187
194 struct mlx5_wqe_fmr_seg { 188 struct mlx5_wqe_fmr_seg {
195 __be32 flags; 189 __be32 flags;
196 __be32 mem_key; 190 __be32 mem_key;
197 __be64 buf_list; 191 __be64 buf_list;
198 __be64 start_addr; 192 __be64 start_addr;
199 __be64 reg_len; 193 __be64 reg_len;
200 __be32 offset; 194 __be32 offset;
201 __be32 page_size; 195 __be32 page_size;
202 u32 reserved[2]; 196 u32 reserved[2];
203 }; 197 };
204 198
205 struct mlx5_wqe_ctrl_seg { 199 struct mlx5_wqe_ctrl_seg {
206 __be32 opmod_idx_opco 200 __be32 opmod_idx_opcode;
207 __be32 qpn_ds; 201 __be32 qpn_ds;
208 <<
209 struct_group(trailer, <<
210 <<
211 u8 signature; 202 u8 signature;
212 u8 rsvd[2]; 203 u8 rsvd[2];
213 u8 fm_ce_se; 204 u8 fm_ce_se;
214 union { !! 205 __be32 imm;
215 __be32 general_id; <<
216 __be32 imm; <<
217 __be32 umr_mkey; <<
218 __be32 tis_tir_num; <<
219 }; <<
220 <<
221 ); /* end of trailer group */ <<
222 }; 206 };
223 207
224 #define MLX5_WQE_CTRL_DS_MASK 0x3f 208 #define MLX5_WQE_CTRL_DS_MASK 0x3f
225 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00 209 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
226 #define MLX5_WQE_CTRL_QPN_SHIFT 8 210 #define MLX5_WQE_CTRL_QPN_SHIFT 8
227 #define MLX5_WQE_DS_UNITS 16 211 #define MLX5_WQE_DS_UNITS 16
228 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff 212 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
229 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff0 213 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
230 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 214 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
231 215
232 enum { 216 enum {
233 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 217 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
234 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 218 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
235 MLX5_ETH_WQE_L3_CSUM = 1 << 219 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
236 MLX5_ETH_WQE_L4_CSUM = 1 << 220 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
237 }; 221 };
238 222
239 enum { 223 enum {
240 MLX5_ETH_WQE_SVLAN = 1 << 224 MLX5_ETH_WQE_SVLAN = 1 << 0,
241 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSO <<
242 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSO <<
243 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSO <<
244 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSO <<
245 MLX5_ETH_WQE_INSERT_TRAILER = 1 << <<
246 MLX5_ETH_WQE_INSERT_VLAN = 1 << 225 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15,
247 }; 226 };
248 227
249 enum { 228 enum {
250 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 229 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0,
251 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 230 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1,
252 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 231 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4,
253 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 232 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5,
254 }; 233 };
255 234
256 enum { <<
257 MLX5_ETH_WQE_FT_META_IPSEC = BIT(0), <<
258 MLX5_ETH_WQE_FT_META_MACSEC = BIT(1), <<
259 }; <<
260 <<
261 struct mlx5_wqe_eth_seg { 235 struct mlx5_wqe_eth_seg {
262 u8 swp_outer_l4_offset; 236 u8 swp_outer_l4_offset;
263 u8 swp_outer_l3_offset; 237 u8 swp_outer_l3_offset;
264 u8 swp_inner_l4_offset; 238 u8 swp_inner_l4_offset;
265 u8 swp_inner_l3_offset; 239 u8 swp_inner_l3_offset;
266 u8 cs_flags; 240 u8 cs_flags;
267 u8 swp_flags; 241 u8 swp_flags;
268 __be16 mss; 242 __be16 mss;
269 __be32 flow_table_metadata; !! 243 __be32 rsvd2;
270 union { 244 union {
271 struct { 245 struct {
272 __be16 sz; 246 __be16 sz;
273 union { !! 247 u8 start[2];
274 u8 start[2 <<
275 DECLARE_FLEX_A <<
276 }; <<
277 } inline_hdr; 248 } inline_hdr;
278 struct { 249 struct {
279 __be16 type; 250 __be16 type;
280 __be16 vlan_tci; 251 __be16 vlan_tci;
281 } insert; 252 } insert;
282 __be32 trailer; <<
283 }; 253 };
284 }; 254 };
285 255
286 struct mlx5_wqe_xrc_seg { 256 struct mlx5_wqe_xrc_seg {
287 __be32 xrc_srqn; 257 __be32 xrc_srqn;
288 u8 rsvd[12]; 258 u8 rsvd[12];
289 }; 259 };
290 260
291 struct mlx5_wqe_masked_atomic_seg { 261 struct mlx5_wqe_masked_atomic_seg {
292 __be64 swap_add; 262 __be64 swap_add;
293 __be64 compare; 263 __be64 compare;
294 __be64 swap_add_mask; 264 __be64 swap_add_mask;
295 __be64 compare_mask; 265 __be64 compare_mask;
296 }; 266 };
297 267
298 struct mlx5_base_av { 268 struct mlx5_base_av {
299 union { 269 union {
300 struct { 270 struct {
301 __be32 qkey; 271 __be32 qkey;
302 __be32 reserved; 272 __be32 reserved;
303 } qkey; 273 } qkey;
304 __be64 dc_key; 274 __be64 dc_key;
305 } key; 275 } key;
306 __be32 dqp_dct; 276 __be32 dqp_dct;
307 u8 stat_rate_sl; 277 u8 stat_rate_sl;
308 u8 fl_mlid; 278 u8 fl_mlid;
309 union { 279 union {
310 __be16 rlid; 280 __be16 rlid;
311 __be16 udp_sport; 281 __be16 udp_sport;
312 }; 282 };
313 }; 283 };
314 284
315 struct mlx5_av { 285 struct mlx5_av {
316 union { 286 union {
317 struct { 287 struct {
318 __be32 qkey; 288 __be32 qkey;
319 __be32 reserved; 289 __be32 reserved;
320 } qkey; 290 } qkey;
321 __be64 dc_key; 291 __be64 dc_key;
322 } key; 292 } key;
323 __be32 dqp_dct; 293 __be32 dqp_dct;
324 u8 stat_rate_sl; 294 u8 stat_rate_sl;
325 u8 fl_mlid; 295 u8 fl_mlid;
326 union { 296 union {
327 __be16 rlid; 297 __be16 rlid;
328 __be16 udp_sport; 298 __be16 udp_sport;
329 }; 299 };
330 u8 reserved0[4]; 300 u8 reserved0[4];
331 u8 rmac[6]; 301 u8 rmac[6];
332 u8 tclass; 302 u8 tclass;
333 u8 hop_limit; 303 u8 hop_limit;
334 __be32 grh_gid_fl; 304 __be32 grh_gid_fl;
335 u8 rgid[16]; 305 u8 rgid[16];
336 }; 306 };
337 307
338 struct mlx5_ib_ah { 308 struct mlx5_ib_ah {
339 struct ib_ah ibah; 309 struct ib_ah ibah;
340 struct mlx5_av av; 310 struct mlx5_av av;
341 u8 xmit_port; <<
342 }; 311 };
343 312
344 static inline struct mlx5_ib_ah *to_mah(struct 313 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
345 { 314 {
346 return container_of(ibah, struct mlx5_ 315 return container_of(ibah, struct mlx5_ib_ah, ibah);
347 } 316 }
348 317
349 struct mlx5_wqe_datagram_seg { 318 struct mlx5_wqe_datagram_seg {
350 struct mlx5_av av; 319 struct mlx5_av av;
351 }; 320 };
352 321
353 struct mlx5_wqe_raddr_seg { 322 struct mlx5_wqe_raddr_seg {
354 __be64 raddr; 323 __be64 raddr;
355 __be32 rkey; 324 __be32 rkey;
356 u32 reserved; 325 u32 reserved;
357 }; 326 };
358 327
359 struct mlx5_wqe_atomic_seg { 328 struct mlx5_wqe_atomic_seg {
360 __be64 swap_add; 329 __be64 swap_add;
361 __be64 compare; 330 __be64 compare;
362 }; 331 };
363 332
364 struct mlx5_wqe_data_seg { 333 struct mlx5_wqe_data_seg {
365 __be32 byte_count; 334 __be32 byte_count;
366 __be32 lkey; 335 __be32 lkey;
367 __be64 addr; 336 __be64 addr;
368 }; 337 };
369 338
370 struct mlx5_wqe_umr_ctrl_seg { 339 struct mlx5_wqe_umr_ctrl_seg {
371 u8 flags; 340 u8 flags;
372 u8 rsvd0[3]; 341 u8 rsvd0[3];
373 __be16 xlt_octowords; 342 __be16 xlt_octowords;
374 union { 343 union {
375 __be16 xlt_offset; 344 __be16 xlt_offset;
376 __be16 bsf_octowords; 345 __be16 bsf_octowords;
377 }; 346 };
378 __be64 mkey_mask; 347 __be64 mkey_mask;
379 __be32 xlt_offset_47_16; 348 __be32 xlt_offset_47_16;
380 u8 rsvd1[28]; 349 u8 rsvd1[28];
381 }; 350 };
382 351
383 struct mlx5_seg_set_psv { 352 struct mlx5_seg_set_psv {
384 __be32 psv_num; 353 __be32 psv_num;
385 __be16 syndrome; 354 __be16 syndrome;
386 __be16 status; 355 __be16 status;
387 __be32 transient_sig; 356 __be32 transient_sig;
388 __be32 ref_tag; 357 __be32 ref_tag;
389 }; 358 };
390 359
391 struct mlx5_seg_get_psv { 360 struct mlx5_seg_get_psv {
392 u8 rsvd[19]; 361 u8 rsvd[19];
393 u8 num_psv; 362 u8 num_psv;
394 __be32 l_key; 363 __be32 l_key;
395 __be64 va; 364 __be64 va;
396 __be32 psv_index[4]; 365 __be32 psv_index[4];
397 }; 366 };
398 367
399 struct mlx5_seg_check_psv { 368 struct mlx5_seg_check_psv {
400 u8 rsvd0[2]; 369 u8 rsvd0[2];
401 __be16 err_coalescing_op; 370 __be16 err_coalescing_op;
402 u8 rsvd1[2]; 371 u8 rsvd1[2];
403 __be16 xport_err_op; 372 __be16 xport_err_op;
404 u8 rsvd2[2]; 373 u8 rsvd2[2];
405 __be16 xport_err_mask; 374 __be16 xport_err_mask;
406 u8 rsvd3[7]; 375 u8 rsvd3[7];
407 u8 num_psv; 376 u8 num_psv;
408 __be32 l_key; 377 __be32 l_key;
409 __be64 va; 378 __be64 va;
410 __be32 psv_index[4]; 379 __be32 psv_index[4];
411 }; 380 };
412 381
413 struct mlx5_rwqe_sig { 382 struct mlx5_rwqe_sig {
414 u8 rsvd0[4]; 383 u8 rsvd0[4];
415 u8 signature; 384 u8 signature;
416 u8 rsvd1[11]; 385 u8 rsvd1[11];
417 }; 386 };
418 387
419 struct mlx5_wqe_signature_seg { 388 struct mlx5_wqe_signature_seg {
420 u8 rsvd0[4]; 389 u8 rsvd0[4];
421 u8 signature; 390 u8 signature;
422 u8 rsvd1[11]; 391 u8 rsvd1[11];
423 }; 392 };
424 393
425 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x 394 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
426 395
427 struct mlx5_wqe_inline_seg { 396 struct mlx5_wqe_inline_seg {
428 __be32 byte_count; 397 __be32 byte_count;
429 __be32 data[]; !! 398 __be32 data[0];
430 }; 399 };
431 400
432 enum mlx5_sig_type { 401 enum mlx5_sig_type {
433 MLX5_DIF_CRC = 0x1, 402 MLX5_DIF_CRC = 0x1,
434 MLX5_DIF_IPCS = 0x2, 403 MLX5_DIF_IPCS = 0x2,
435 }; 404 };
436 405
437 struct mlx5_bsf_inl { 406 struct mlx5_bsf_inl {
438 __be16 vld_refresh; 407 __be16 vld_refresh;
439 __be16 dif_apptag; 408 __be16 dif_apptag;
440 __be32 dif_reftag; 409 __be32 dif_reftag;
441 u8 sig_type; 410 u8 sig_type;
442 u8 rp_inv_seed; 411 u8 rp_inv_seed;
443 u8 rsvd[3]; 412 u8 rsvd[3];
444 u8 dif_inc_ref_guard_chec 413 u8 dif_inc_ref_guard_check;
445 __be16 dif_app_bitmask_check; 414 __be16 dif_app_bitmask_check;
446 }; 415 };
447 416
448 struct mlx5_bsf { 417 struct mlx5_bsf {
449 struct mlx5_bsf_basic { 418 struct mlx5_bsf_basic {
450 u8 bsf_size_sbs; 419 u8 bsf_size_sbs;
451 u8 check_byte_mas 420 u8 check_byte_mask;
452 union { 421 union {
453 u8 copy_byte_mask 422 u8 copy_byte_mask;
454 u8 bs_selector; 423 u8 bs_selector;
455 u8 rsvd_wflags; 424 u8 rsvd_wflags;
456 } wire; 425 } wire;
457 union { 426 union {
458 u8 bs_selector; 427 u8 bs_selector;
459 u8 rsvd_mflags; 428 u8 rsvd_mflags;
460 } mem; 429 } mem;
461 __be32 raw_data_size; 430 __be32 raw_data_size;
462 __be32 w_bfs_psv; 431 __be32 w_bfs_psv;
463 __be32 m_bfs_psv; 432 __be32 m_bfs_psv;
464 } basic; 433 } basic;
465 struct mlx5_bsf_ext { 434 struct mlx5_bsf_ext {
466 __be32 t_init_gen_pro 435 __be32 t_init_gen_pro_size;
467 __be32 rsvd_epi_size; 436 __be32 rsvd_epi_size;
468 __be32 w_tfs_psv; 437 __be32 w_tfs_psv;
469 __be32 m_tfs_psv; 438 __be32 m_tfs_psv;
470 } ext; 439 } ext;
471 struct mlx5_bsf_inl w_inl; 440 struct mlx5_bsf_inl w_inl;
472 struct mlx5_bsf_inl m_inl; 441 struct mlx5_bsf_inl m_inl;
473 }; 442 };
474 443
475 struct mlx5_mtt { 444 struct mlx5_mtt {
476 __be64 ptag; 445 __be64 ptag;
477 }; 446 };
478 447
479 struct mlx5_klm { 448 struct mlx5_klm {
480 __be32 bcount; 449 __be32 bcount;
481 __be32 key; 450 __be32 key;
482 __be64 va; 451 __be64 va;
483 }; 452 };
484 453
485 struct mlx5_ksm { <<
486 __be32 reserved; <<
487 __be32 key; <<
488 __be64 va; <<
489 }; <<
490 <<
491 struct mlx5_stride_block_entry { 454 struct mlx5_stride_block_entry {
492 __be16 stride; 455 __be16 stride;
493 __be16 bcount; 456 __be16 bcount;
494 __be32 key; 457 __be32 key;
495 __be64 va; 458 __be64 va;
496 }; 459 };
497 460
498 struct mlx5_stride_block_ctrl_seg { 461 struct mlx5_stride_block_ctrl_seg {
499 __be32 bcount_per_cycle; 462 __be32 bcount_per_cycle;
500 __be32 op; 463 __be32 op;
501 __be32 repeat_count; 464 __be32 repeat_count;
502 u16 rsvd; 465 u16 rsvd;
503 __be16 num_entries; 466 __be16 num_entries;
504 }; 467 };
505 468
506 struct mlx5_wqe_flow_update_ctrl_seg { <<
507 __be32 flow_idx_update; <<
508 __be32 dest_handle; <<
509 u8 reserved0[40]; <<
510 }; <<
511 <<
512 struct mlx5_wqe_header_modify_argument_update_ <<
513 u8 argument_list[64]; <<
514 }; <<
515 <<
516 struct mlx5_core_qp { 469 struct mlx5_core_qp {
517 struct mlx5_core_rsc_common common 470 struct mlx5_core_rsc_common common; /* must be first */
518 void (*event) (struct mlx5_c 471 void (*event) (struct mlx5_core_qp *, int);
519 int qpn; 472 int qpn;
520 struct mlx5_rsc_debug *dbg; 473 struct mlx5_rsc_debug *dbg;
521 int pid; 474 int pid;
522 u16 uid; 475 u16 uid;
523 }; 476 };
524 477
525 struct mlx5_core_dct { 478 struct mlx5_core_dct {
526 struct mlx5_core_qp mqp; 479 struct mlx5_core_qp mqp;
527 struct completion drained; 480 struct completion drained;
528 }; 481 };
529 482
>> 483 struct mlx5_qp_path {
>> 484 u8 fl_free_ar;
>> 485 u8 rsvd3;
>> 486 __be16 pkey_index;
>> 487 u8 rsvd0;
>> 488 u8 grh_mlid;
>> 489 __be16 rlid;
>> 490 u8 ackto_lt;
>> 491 u8 mgid_index;
>> 492 u8 static_rate;
>> 493 u8 hop_limit;
>> 494 __be32 tclass_flowlabel;
>> 495 union {
>> 496 u8 rgid[16];
>> 497 u8 rip[16];
>> 498 };
>> 499 u8 f_dscp_ecn_prio;
>> 500 u8 ecn_dscp;
>> 501 __be16 udp_sport;
>> 502 u8 dci_cfi_prio_sl;
>> 503 u8 port;
>> 504 u8 rmac[6];
>> 505 };
>> 506
>> 507 /* FIXME: use mlx5_ifc.h qpc */
>> 508 struct mlx5_qp_context {
>> 509 __be32 flags;
>> 510 __be32 flags_pd;
>> 511 u8 mtu_msgmax;
>> 512 u8 rq_size_stride;
>> 513 __be16 sq_crq_size;
>> 514 __be32 qp_counter_set_usr_page;
>> 515 __be32 wire_qpn;
>> 516 __be32 log_pg_sz_remote_qpn;
>> 517 struct mlx5_qp_path pri_path;
>> 518 struct mlx5_qp_path alt_path;
>> 519 __be32 params1;
>> 520 u8 reserved2[4];
>> 521 __be32 next_send_psn;
>> 522 __be32 cqn_send;
>> 523 __be32 deth_sqpn;
>> 524 u8 reserved3[4];
>> 525 __be32 last_acked_psn;
>> 526 __be32 ssn;
>> 527 __be32 params2;
>> 528 __be32 rnr_nextrecvpsn;
>> 529 __be32 xrcd;
>> 530 __be32 cqn_recv;
>> 531 __be64 db_rec_addr;
>> 532 __be32 qkey;
>> 533 __be32 rq_type_srqn;
>> 534 __be32 rmsn;
>> 535 __be16 hw_sq_wqe_counter;
>> 536 __be16 sw_sq_wqe_counter;
>> 537 __be16 hw_rcyclic_byte_counter;
>> 538 __be16 hw_rq_counter;
>> 539 __be16 sw_rcyclic_byte_counter;
>> 540 __be16 sw_rq_counter;
>> 541 u8 rsvd0[5];
>> 542 u8 cgs;
>> 543 u8 cs_req;
>> 544 u8 cs_res;
>> 545 __be64 dc_access_key;
>> 546 u8 rsvd1[24];
>> 547 };
>> 548
>> 549 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
>> 550 {
>> 551 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
>> 552 }
>> 553
>> 554 static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
>> 555 {
>> 556 return radix_tree_lookup(&dev->priv.mkey_table.tree, key);
>> 557 }
>> 558
>> 559 int mlx5_core_create_dct(struct mlx5_core_dev *dev,
>> 560 struct mlx5_core_dct *qp,
>> 561 u32 *in, int inlen,
>> 562 u32 *out, int outlen);
>> 563 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
>> 564 struct mlx5_core_qp *qp,
>> 565 u32 *in,
>> 566 int inlen);
>> 567 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode,
>> 568 u32 opt_param_mask, void *qpc,
>> 569 struct mlx5_core_qp *qp);
>> 570 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
>> 571 struct mlx5_core_qp *qp);
>> 572 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev,
>> 573 struct mlx5_core_dct *dct);
>> 574 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
>> 575 u32 *out, int outlen);
>> 576 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct,
>> 577 u32 *out, int outlen);
>> 578
>> 579 int mlx5_core_set_delay_drop(struct mlx5_core_dev *dev,
>> 580 u32 timeout_usec);
>> 581
>> 582 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
>> 583 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
>> 584 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
>> 585 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
530 int mlx5_debug_qp_add(struct mlx5_core_dev *de 586 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
531 void mlx5_debug_qp_remove(struct mlx5_core_dev 587 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
>> 588 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
>> 589 struct mlx5_core_qp *rq);
>> 590 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
>> 591 struct mlx5_core_qp *rq);
>> 592 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
>> 593 struct mlx5_core_qp *sq);
>> 594 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
>> 595 struct mlx5_core_qp *sq);
>> 596 int mlx5_core_alloc_q_counter(struct mlx5_core_dev *dev, u16 *counter_id);
>> 597 int mlx5_core_dealloc_q_counter(struct mlx5_core_dev *dev, u16 counter_id);
>> 598 int mlx5_core_query_q_counter(struct mlx5_core_dev *dev, u16 counter_id,
>> 599 int reset, void *out, int out_size);
>> 600
>> 601 struct mlx5_core_rsc_common *mlx5_core_res_hold(struct mlx5_core_dev *dev,
>> 602 int res_num,
>> 603 enum mlx5_res_type res_type);
>> 604 void mlx5_core_res_put(struct mlx5_core_rsc_common *res);
532 605
533 static inline const char *mlx5_qp_type_str(int 606 static inline const char *mlx5_qp_type_str(int type)
534 { 607 {
535 switch (type) { 608 switch (type) {
536 case MLX5_QP_ST_RC: return "RC"; 609 case MLX5_QP_ST_RC: return "RC";
537 case MLX5_QP_ST_UC: return "C"; 610 case MLX5_QP_ST_UC: return "C";
538 case MLX5_QP_ST_UD: return "UD"; 611 case MLX5_QP_ST_UD: return "UD";
539 case MLX5_QP_ST_XRC: return "XRC"; 612 case MLX5_QP_ST_XRC: return "XRC";
540 case MLX5_QP_ST_MLX: return "MLX"; 613 case MLX5_QP_ST_MLX: return "MLX";
541 case MLX5_QP_ST_QP0: return "QP0"; 614 case MLX5_QP_ST_QP0: return "QP0";
542 case MLX5_QP_ST_QP1: return "QP1"; 615 case MLX5_QP_ST_QP1: return "QP1";
543 case MLX5_QP_ST_RAW_ETHERTYPE: return 616 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
544 case MLX5_QP_ST_RAW_IPV6: return "RAW_ 617 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
545 case MLX5_QP_ST_SNIFFER: return "SNIFF 618 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
546 case MLX5_QP_ST_SYNC_UMR: return "SYNC 619 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
547 case MLX5_QP_ST_PTP_1588: return "PTP_ 620 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
548 case MLX5_QP_ST_REG_UMR: return "REG_U 621 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
549 default: return "Invalid transport typ 622 default: return "Invalid transport type";
550 } 623 }
551 } 624 }
552 625
553 static inline const char *mlx5_qp_state_str(in 626 static inline const char *mlx5_qp_state_str(int state)
554 { 627 {
555 switch (state) { 628 switch (state) {
556 case MLX5_QP_STATE_RST: 629 case MLX5_QP_STATE_RST:
557 return "RST"; 630 return "RST";
558 case MLX5_QP_STATE_INIT: 631 case MLX5_QP_STATE_INIT:
559 return "INIT"; 632 return "INIT";
560 case MLX5_QP_STATE_RTR: 633 case MLX5_QP_STATE_RTR:
561 return "RTR"; 634 return "RTR";
562 case MLX5_QP_STATE_RTS: 635 case MLX5_QP_STATE_RTS:
563 return "RTS"; 636 return "RTS";
564 case MLX5_QP_STATE_SQER: 637 case MLX5_QP_STATE_SQER:
565 return "SQER"; 638 return "SQER";
566 case MLX5_QP_STATE_SQD: 639 case MLX5_QP_STATE_SQD:
567 return "SQD"; 640 return "SQD";
568 case MLX5_QP_STATE_ERR: 641 case MLX5_QP_STATE_ERR:
569 return "ERR"; 642 return "ERR";
570 case MLX5_QP_STATE_SQ_DRAINING: 643 case MLX5_QP_STATE_SQ_DRAINING:
571 return "SQ_DRAINING"; 644 return "SQ_DRAINING";
572 case MLX5_QP_STATE_SUSPENDED: 645 case MLX5_QP_STATE_SUSPENDED:
573 return "SUSPENDED"; 646 return "SUSPENDED";
574 default: return "Invalid QP state"; 647 default: return "Invalid QP state";
575 } 648 }
576 } <<
577 <<
578 static inline int mlx5_get_qp_default_ts(struc <<
579 { <<
580 u8 supported_ts_cap = mlx5_get_roce_st <<
581 MLX5_CAP_ROCE(de <<
582 MLX5_CAP_GEN(dev <<
583 <<
584 return supported_ts_cap ? MLX5_TIMESTA <<
585 MLX5_TIMESTAMP_FORMAT_FREE_RUNN <<
586 } 649 }
587 650
588 #endif /* MLX5_QP_H */ 651 #endif /* MLX5_QP_H */
589 652
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