1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * linux/include/linux/mmc/host.h
4 *
5 * Host driver specific definitions.
6 */
7 #ifndef LINUX_MMC_HOST_H
8 #define LINUX_MMC_HOST_H
9
10 #include <linux/sched.h>
11 #include <linux/device.h>
12 #include <linux/fault-inject.h>
13 #include <linux/debugfs.h>
14
15 #include <linux/mmc/core.h>
16 #include <linux/mmc/card.h>
17 #include <linux/mmc/pm.h>
18 #include <linux/dma-direction.h>
19 #include <linux/blk-crypto-profile.h>
20
21 struct mmc_ios {
22 unsigned int clock;
23 unsigned short vdd;
24 unsigned int power_delay_ms;
25
26 /* vdd stores the bit number of the selected v
27
28 unsigned char bus_mode;
29
30 #define MMC_BUSMODE_OPENDRAIN 1
31 #define MMC_BUSMODE_PUSHPULL 2
32
33 unsigned char chip_select;
34
35 #define MMC_CS_DONTCARE 0
36 #define MMC_CS_HIGH 1
37 #define MMC_CS_LOW 2
38
39 unsigned char power_mode;
40
41 #define MMC_POWER_OFF 0
42 #define MMC_POWER_UP 1
43 #define MMC_POWER_ON 2
44 #define MMC_POWER_UNDEFINED 3
45
46 unsigned char bus_width;
47
48 #define MMC_BUS_WIDTH_1 0
49 #define MMC_BUS_WIDTH_4 2
50 #define MMC_BUS_WIDTH_8 3
51
52 unsigned char timing;
53
54 #define MMC_TIMING_LEGACY 0
55 #define MMC_TIMING_MMC_HS 1
56 #define MMC_TIMING_SD_HS 2
57 #define MMC_TIMING_UHS_SDR12 3
58 #define MMC_TIMING_UHS_SDR25 4
59 #define MMC_TIMING_UHS_SDR50 5
60 #define MMC_TIMING_UHS_SDR104 6
61 #define MMC_TIMING_UHS_DDR50 7
62 #define MMC_TIMING_MMC_DDR52 8
63 #define MMC_TIMING_MMC_HS200 9
64 #define MMC_TIMING_MMC_HS400 10
65 #define MMC_TIMING_SD_EXP 11
66 #define MMC_TIMING_SD_EXP_1_2V 12
67
68 unsigned char signal_voltage;
69
70 #define MMC_SIGNAL_VOLTAGE_330 0
71 #define MMC_SIGNAL_VOLTAGE_180 1
72 #define MMC_SIGNAL_VOLTAGE_120 2
73
74 unsigned char drv_type;
75
76 #define MMC_SET_DRIVER_TYPE_B 0
77 #define MMC_SET_DRIVER_TYPE_A 1
78 #define MMC_SET_DRIVER_TYPE_C 2
79 #define MMC_SET_DRIVER_TYPE_D 3
80
81 bool enhanced_strobe;
82 };
83
84 struct mmc_clk_phase {
85 bool valid;
86 u16 in_deg;
87 u16 out_deg;
88 };
89
90 #define MMC_NUM_CLK_PHASES (MMC_TIMING_MMC_HS4
91 struct mmc_clk_phase_map {
92 struct mmc_clk_phase phase[MMC_NUM_CLK
93 };
94
95 struct mmc_host;
96
97 enum mmc_err_stat {
98 MMC_ERR_CMD_TIMEOUT,
99 MMC_ERR_CMD_CRC,
100 MMC_ERR_DAT_TIMEOUT,
101 MMC_ERR_DAT_CRC,
102 MMC_ERR_AUTO_CMD,
103 MMC_ERR_ADMA,
104 MMC_ERR_TUNING,
105 MMC_ERR_CMDQ_RED,
106 MMC_ERR_CMDQ_GCE,
107 MMC_ERR_CMDQ_ICCE,
108 MMC_ERR_REQ_TIMEOUT,
109 MMC_ERR_CMDQ_REQ_TIMEOUT,
110 MMC_ERR_ICE_CFG,
111 MMC_ERR_CTRL_TIMEOUT,
112 MMC_ERR_UNEXPECTED_IRQ,
113 MMC_ERR_MAX,
114 };
115
116 struct mmc_host_ops {
117 /*
118 * It is optional for the host to impl
119 * order to support double buffering o
120 * request while another request is ac
121 * pre_req() must always be followed b
122 * To undo a call made to pre_req(), c
123 * a nonzero err condition.
124 */
125 void (*post_req)(struct mmc_host *h
126 int err);
127 void (*pre_req)(struct mmc_host *ho
128 void (*request)(struct mmc_host *ho
129 /* Submit one request to host in atomi
130 int (*request_atomic)(struct mmc_h
131 struct mmc_r
132
133 /*
134 * Avoid calling the next three functi
135 * path", since underlaying controller
136 * expensive and/or slow way. Also not
137 * sleep, so don't call them in the at
138 */
139
140 /*
141 * Notes to the set_ios callback:
142 * ios->clock might be 0. For some con
143 * as any other frequency works. Howev
144 * explicitly need to disable the cloc
145 * switching might fail because the SD
146 */
147 void (*set_ios)(struct mmc_host *ho
148
149 /*
150 * Return values for the get_ro callba
151 * 0 for a read/write card
152 * 1 for a read-only card
153 * -ENOSYS when not supported (equal
154 * or a negative errno value when so
155 */
156 int (*get_ro)(struct mmc_host *hos
157
158 /*
159 * Return values for the get_cd callba
160 * 0 for a absent card
161 * 1 for a present card
162 * -ENOSYS when not supported (equal
163 * or a negative errno value when so
164 */
165 int (*get_cd)(struct mmc_host *hos
166
167 void (*enable_sdio_irq)(struct mmc_
168 /* Mandatory callback when using MMC_C
169 void (*ack_sdio_irq)(struct mmc_hos
170
171 /* optional callback for HC quirks */
172 void (*init_card)(struct mmc_host *
173
174 int (*start_signal_voltage_switch)
175
176 /* Check if the card is pulling dat[0]
177 int (*card_busy)(struct mmc_host *
178
179 /* The tuning command opcode value is
180 int (*execute_tuning)(struct mmc_h
181
182 /* Prepare HS400 target operating freq
183 int (*prepare_hs400_tuning)(struct
184
185 /* Execute HS400 tuning depending host
186 int (*execute_hs400_tuning)(struct
187
188 /* Optional callback to prepare for SD
189 int (*prepare_sd_hs_tuning)(struct
190
191 /* Optional callback to execute SD hig
192 int (*execute_sd_hs_tuning)(struct
193
194 /* Prepare switch to DDR during the HS
195 int (*hs400_prepare_ddr)(struct mm
196
197 /* Prepare for switching from HS400 to
198 void (*hs400_downgrade)(struct mmc_
199
200 /* Complete selection of HS400 */
201 void (*hs400_complete)(struct mmc_h
202
203 /* Prepare enhanced strobe depending h
204 void (*hs400_enhanced_strobe)(struc
205 struc
206 int (*select_drive_strength)(struc
207 unsig
208 int c
209 /* Reset the eMMC card via RST_n */
210 void (*card_hw_reset)(struct mmc_ho
211 void (*card_event)(struct mmc_host
212
213 /*
214 * Optional callback to support contro
215 * I/O. Returns the number of supporte
216 */
217 int (*multi_io_quirk)(struct mmc_c
218 unsigned int
219
220 /* Initialize an SD express card, mand
221 int (*init_sd_express)(struct mmc_
222 };
223
224 struct mmc_cqe_ops {
225 /* Allocate resources, and make the CQ
226 int (*cqe_enable)(struct mmc_host
227 /* Free resources, and make the CQE no
228 void (*cqe_disable)(struct mmc_host
229 /*
230 * Issue a read, write or DCMD request
231 * effect of ->cqe_off().
232 */
233 int (*cqe_request)(struct mmc_host
234 /* Free resources (e.g. DMA mapping) a
235 void (*cqe_post_req)(struct mmc_hos
236 /*
237 * Prepare the CQE and host controller
238 * is no corresponding ->cqe_on(), ins
239 * to deal with that.
240 */
241 void (*cqe_off)(struct mmc_host *ho
242 /*
243 * Wait for all CQE tasks to complete.
244 * becomes necessary.
245 */
246 int (*cqe_wait_for_idle)(struct mm
247 /*
248 * Notify CQE that a request has timed
249 * completed or true if a timeout happ
250 * recovery is needed.
251 */
252 bool (*cqe_timeout)(struct mmc_host
253 bool *recovery_
254 /*
255 * Stop all CQE activity and prepare t
256 * accept recovery commands.
257 */
258 void (*cqe_recovery_start)(struct m
259 /*
260 * Clear the queue and call mmc_cqe_re
261 * Requests that errored will have the
262 * (data->error or cmd->error for DCMD
263 * will have zero data bytes transferr
264 */
265 void (*cqe_recovery_finish)(struct
266 };
267
268 /**
269 * struct mmc_slot - MMC slot functions
270 *
271 * @cd_irq: MMC/SD-card slot hotpl
272 * @handler_priv: MMC/SD-card slot conte
273 *
274 * Some MMC/SD host controllers implement slot
275 * write-protect detection natively. However,
276 * leave these functions to the CPU. This stru
277 * such slot-function drivers.
278 */
279 struct mmc_slot {
280 int cd_irq;
281 bool cd_wake_enabled;
282 void *handler_priv;
283 };
284
285 struct regulator;
286 struct mmc_pwrseq;
287
288 struct mmc_supply {
289 struct regulator *vmmc; /* Car
290 struct regulator *vqmmc; /* Opt
291 };
292
293 struct mmc_ctx {
294 struct task_struct *task;
295 };
296
297 struct mmc_host {
298 struct device *parent;
299 struct device class_dev;
300 int index;
301 const struct mmc_host_ops *ops;
302 struct mmc_pwrseq *pwrseq;
303 unsigned int f_min;
304 unsigned int f_max;
305 unsigned int f_init;
306 u32 ocr_avail;
307 u32 ocr_avail_sdio
308 u32 ocr_avail_sd;
309 u32 ocr_avail_mmc;
310 struct wakeup_source *ws;
311 u32 max_current_33
312 u32 max_current_30
313 u32 max_current_18
314
315 #define MMC_VDD_165_195 0x00000080
316 #define MMC_VDD_20_21 0x00000100
317 #define MMC_VDD_21_22 0x00000200
318 #define MMC_VDD_22_23 0x00000400
319 #define MMC_VDD_23_24 0x00000800
320 #define MMC_VDD_24_25 0x00001000
321 #define MMC_VDD_25_26 0x00002000
322 #define MMC_VDD_26_27 0x00004000
323 #define MMC_VDD_27_28 0x00008000
324 #define MMC_VDD_28_29 0x00010000
325 #define MMC_VDD_29_30 0x00020000
326 #define MMC_VDD_30_31 0x00040000
327 #define MMC_VDD_31_32 0x00080000
328 #define MMC_VDD_32_33 0x00100000
329 #define MMC_VDD_33_34 0x00200000
330 #define MMC_VDD_34_35 0x00400000
331 #define MMC_VDD_35_36 0x00800000
332
333 u32 caps;
334
335 #define MMC_CAP_4_BIT_DATA (1 << 0)
336 #define MMC_CAP_MMC_HIGHSPEED (1 << 1)
337 #define MMC_CAP_SD_HIGHSPEED (1 << 2)
338 #define MMC_CAP_SDIO_IRQ (1 << 3)
339 #define MMC_CAP_SPI (1 << 4)
340 #define MMC_CAP_NEEDS_POLL (1 << 5)
341 #define MMC_CAP_8_BIT_DATA (1 << 6)
342 #define MMC_CAP_AGGRESSIVE_PM (1 << 7)
343 #define MMC_CAP_NONREMOVABLE (1 << 8)
344 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9)
345 #define MMC_CAP_3_3V_DDR (1 << 11)
346 #define MMC_CAP_1_8V_DDR (1 << 12)
347 #define MMC_CAP_1_2V_DDR (1 << 13)
348 #define MMC_CAP_DDR (MMC_CAP_3_3V_
349 MMC_CAP_1_2V_
350 #define MMC_CAP_POWER_OFF_CARD (1 << 14)
351 #define MMC_CAP_BUS_WIDTH_TEST (1 << 15)
352 #define MMC_CAP_UHS_SDR12 (1 << 16)
353 #define MMC_CAP_UHS_SDR25 (1 << 17)
354 #define MMC_CAP_UHS_SDR50 (1 << 18)
355 #define MMC_CAP_UHS_SDR104 (1 << 19)
356 #define MMC_CAP_UHS_DDR50 (1 << 20)
357 #define MMC_CAP_UHS (MMC_CAP_UHS_S
358 MMC_CAP_UHS_S
359 MMC_CAP_UHS_D
360 #define MMC_CAP_SYNC_RUNTIME_PM (1 << 21)
361 #define MMC_CAP_NEED_RSP_BUSY (1 << 22)
362 #define MMC_CAP_DRIVER_TYPE_A (1 << 23)
363 #define MMC_CAP_DRIVER_TYPE_C (1 << 24)
364 #define MMC_CAP_DRIVER_TYPE_D (1 << 25)
365 #define MMC_CAP_DONE_COMPLETE (1 << 27)
366 #define MMC_CAP_CD_WAKE (1 << 28)
367 #define MMC_CAP_CMD_DURING_TFR (1 << 29)
368 #define MMC_CAP_CMD23 (1 << 30)
369 #define MMC_CAP_HW_RESET (1 << 31)
370
371 u32 caps2;
372
373 #define MMC_CAP2_BOOTPART_NOACC (1 << 0)
374 #define MMC_CAP2_FULL_PWR_CYCLE (1 << 2)
375 #define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1
376 #define MMC_CAP2_HS200_1_8V_SDR (1 << 5)
377 #define MMC_CAP2_HS200_1_2V_SDR (1 << 6)
378 #define MMC_CAP2_HS200 (MMC_CAP2_HS20
379 MMC_CAP2_HS20
380 #define MMC_CAP2_SD_EXP (1 << 7)
381 #define MMC_CAP2_SD_EXP_1_2V (1 << 8)
382 #define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10)
383 #define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11)
384 #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14)
385 #define MMC_CAP2_HS400_1_8V (1 << 15)
386 #define MMC_CAP2_HS400_1_2V (1 << 16)
387 #define MMC_CAP2_HS400 (MMC_CAP2_HS40
388 MMC_CAP2_HS40
389 #define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS20
390 #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS20
391 #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
392 #define MMC_CAP2_NO_WRITE_PROTECT (1 << 18)
393 #define MMC_CAP2_NO_SDIO (1 << 19)
394 #define MMC_CAP2_HS400_ES (1 << 20)
395 #define MMC_CAP2_NO_SD (1 << 21)
396 #define MMC_CAP2_NO_MMC (1 << 22)
397 #define MMC_CAP2_CQE (1 << 23)
398 #define MMC_CAP2_CQE_DCMD (1 << 24)
399 #define MMC_CAP2_AVOID_3_3V (1 << 25)
400 #define MMC_CAP2_MERGE_CAPABLE (1 << 26)
401 #ifdef CONFIG_MMC_CRYPTO
402 #define MMC_CAP2_CRYPTO (1 << 27)
403 #else
404 #define MMC_CAP2_CRYPTO 0
405 #endif
406 #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28)
407
408 int fixed_drv_type
409
410 mmc_pm_flag_t pm_caps;
411
412 /* host specific block data */
413 unsigned int max_seg_size;
414 unsigned short max_segs;
415 unsigned short unused;
416 unsigned int max_req_size;
417 unsigned int max_blk_size;
418 unsigned int max_blk_count;
419 unsigned int max_busy_timeo
420
421 /* private data */
422 spinlock_t lock;
423
424 struct mmc_ios ios;
425
426 /* group bitfields together to minimiz
427 unsigned int use_spi_crc:1;
428 unsigned int claimed:1;
429 unsigned int doing_init_tun
430 unsigned int can_retune:1;
431 unsigned int doing_retune:1
432 unsigned int retune_now:1;
433 unsigned int retune_paused:
434 unsigned int retune_crc_dis
435 unsigned int can_dma_map_me
436 unsigned int vqmmc_enabled:
437
438 int rescan_disable
439 int rescan_entered
440
441 int need_retune;
442 int hold_retune;
443 unsigned int retune_period;
444 struct timer_list retune_timer;
445
446 bool trigger_card_e
447
448 struct mmc_card *card;
449
450 wait_queue_head_t wq;
451 struct mmc_ctx *claimer;
452 int claim_cnt;
453 struct mmc_ctx default_ctx;
454
455 struct delayed_work detect;
456 int detect_change;
457 struct mmc_slot slot;
458
459 const struct mmc_bus_ops *bus_ops;
460
461 unsigned int sdio_irqs;
462 struct task_struct *sdio_irq_thre
463 struct work_struct sdio_irq_work;
464 bool sdio_irq_pendi
465 atomic_t sdio_irq_threa
466
467 mmc_pm_flag_t pm_flags;
468
469 struct led_trigger *led;
470
471 #ifdef CONFIG_REGULATOR
472 bool regulator_enab
473 #endif
474 struct mmc_supply supply;
475
476 struct dentry *debugfs_root;
477
478 /* Ongoing data transfer that allows c
479 struct mmc_request *ongoing_mrq;
480
481 #ifdef CONFIG_FAIL_MMC_REQUEST
482 struct fault_attr fail_mmc_reque
483 #endif
484
485 unsigned int actual_clock;
486
487 unsigned int slotno; /* use
488
489 int dsr_req;
490 u32 dsr; /* opt
491
492 /* Command Queue Engine (CQE) support
493 const struct mmc_cqe_ops *cqe_ops;
494 void *cqe_private;
495 int cqe_qdepth;
496 bool cqe_enabled;
497 bool cqe_on;
498
499 /* Inline encryption support */
500 #ifdef CONFIG_MMC_CRYPTO
501 struct blk_crypto_profile crypto_profi
502 #endif
503
504 /* Host Software Queue support */
505 bool hsq_enabled;
506 int hsq_depth;
507
508 u32 err_stats[MMC_
509 unsigned long private[] ____
510 };
511
512 struct device_node;
513
514 struct mmc_host *mmc_alloc_host(int extra, str
515 struct mmc_host *devm_mmc_alloc_host(struct de
516 int mmc_add_host(struct mmc_host *);
517 void mmc_remove_host(struct mmc_host *);
518 void mmc_free_host(struct mmc_host *);
519 void mmc_of_parse_clk_phase(struct device *dev
520 struct mmc_clk_pha
521 int mmc_of_parse(struct mmc_host *host);
522 int mmc_of_parse_voltage(struct mmc_host *host
523
524 static inline void *mmc_priv(struct mmc_host *
525 {
526 return (void *)host->private;
527 }
528
529 static inline struct mmc_host *mmc_from_priv(v
530 {
531 return container_of(priv, struct mmc_h
532 }
533
534 #define mmc_host_is_spi(host) ((host)->caps
535
536 #define mmc_dev(x) ((x)->parent)
537 #define mmc_classdev(x) (&(x)->class_dev)
538 #define mmc_hostname(x) (dev_name(&(x)->class_
539
540 void mmc_detect_change(struct mmc_host *, unsi
541 void mmc_request_done(struct mmc_host *, struc
542 void mmc_command_done(struct mmc_host *host, s
543
544 void mmc_cqe_request_done(struct mmc_host *hos
545
546 /*
547 * May be called from host driver's system/run
548 * to know if SDIO IRQs has been claimed.
549 */
550 static inline bool sdio_irq_claimed(struct mmc
551 {
552 return host->sdio_irqs > 0;
553 }
554
555 static inline void mmc_signal_sdio_irq(struct
556 {
557 host->ops->enable_sdio_irq(host, 0);
558 host->sdio_irq_pending = true;
559 if (host->sdio_irq_thread)
560 wake_up_process(host->sdio_irq
561 }
562
563 void sdio_signal_irq(struct mmc_host *host);
564
565 #ifdef CONFIG_REGULATOR
566 int mmc_regulator_set_ocr(struct mmc_host *mmc
567 struct regulator *supp
568 unsigned short vdd_bit
569 int mmc_regulator_set_vqmmc(struct mmc_host *m
570 #else
571 static inline int mmc_regulator_set_ocr(struct
572 struct regula
573 unsigned shor
574 {
575 return 0;
576 }
577
578 static inline int mmc_regulator_set_vqmmc(stru
579 stru
580 {
581 return -EINVAL;
582 }
583 #endif
584
585 int mmc_regulator_get_supply(struct mmc_host *
586 int mmc_regulator_enable_vqmmc(struct mmc_host
587 void mmc_regulator_disable_vqmmc(struct mmc_ho
588
589 static inline int mmc_card_is_removable(struct
590 {
591 return !(host->caps & MMC_CAP_NONREMOV
592 }
593
594 static inline int mmc_card_keep_power(struct m
595 {
596 return host->pm_flags & MMC_PM_KEEP_PO
597 }
598
599 static inline int mmc_card_wake_sdio_irq(struc
600 {
601 return host->pm_flags & MMC_PM_WAKE_SD
602 }
603
604 /* TODO: Move to private header */
605 static inline int mmc_card_hs(struct mmc_card
606 {
607 return card->host->ios.timing == MMC_T
608 card->host->ios.timing == MMC_
609 }
610
611 /* TODO: Move to private header */
612 static inline int mmc_card_uhs(struct mmc_card
613 {
614 return card->host->ios.timing >= MMC_T
615 card->host->ios.timing <= MMC_
616 }
617
618 void mmc_retune_timer_stop(struct mmc_host *ho
619
620 static inline void mmc_retune_needed(struct mm
621 {
622 if (host->can_retune)
623 host->need_retune = 1;
624 }
625
626 static inline bool mmc_can_retune(struct mmc_h
627 {
628 return host->can_retune == 1;
629 }
630
631 static inline bool mmc_doing_retune(struct mmc
632 {
633 return host->doing_retune == 1;
634 }
635
636 static inline bool mmc_doing_tune(struct mmc_h
637 {
638 return host->doing_retune == 1 || host
639 }
640
641 static inline enum dma_data_direction mmc_get_
642 {
643 return data->flags & MMC_DATA_WRITE ?
644 }
645
646 static inline void mmc_debugfs_err_stats_inc(s
647 e
648 {
649 host->err_stats[stat] += 1;
650 }
651
652 int mmc_sd_switch(struct mmc_card *card, bool
653 u8 value, u8 *resp);
654 int mmc_send_status(struct mmc_card *card, u32
655 int mmc_send_tuning(struct mmc_host *host, u32
656 int mmc_send_abort_tuning(struct mmc_host *hos
657 int mmc_get_ext_csd(struct mmc_card *card, u8
658
659 #endif /* LINUX_MMC_HOST_H */
660
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