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TOMOYO Linux Cross Reference
Linux/include/linux/mtd/ndfc.h

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Diff markup

Differences between /include/linux/mtd/ndfc.h (Version linux-6.12-rc7) and /include/linux/mtd/ndfc.h (Version linux-4.4.302)


  1 /* SPDX-License-Identifier: GPL-2.0-only */    << 
  2 /*                                                  1 /*
                                                   >>   2  *  linux/include/linux/mtd/ndfc.h
                                                   >>   3  *
  3  *  Copyright (c) 2006 Thomas Gleixner <tglx@l      4  *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
  4  *                                                  5  *
                                                   >>   6  * This program is free software; you can redistribute it and/or modify
                                                   >>   7  * it under the terms of the GNU General Public License version 2 as
                                                   >>   8  * published by the Free Software Foundation.
                                                   >>   9  *
  5  *  Info:                                          10  *  Info:
  6  *   Contains defines, datastructures for ndfc     11  *   Contains defines, datastructures for ndfc nand controller
                                                   >>  12  *
  7  */                                                13  */
  8 #ifndef __LINUX_MTD_NDFC_H                         14 #ifndef __LINUX_MTD_NDFC_H
  9 #define __LINUX_MTD_NDFC_H                         15 #define __LINUX_MTD_NDFC_H
 10                                                    16 
 11 /* NDFC Register definitions */                    17 /* NDFC Register definitions */
 12 #define NDFC_CMD                0x00               18 #define NDFC_CMD                0x00
 13 #define NDFC_ALE                0x04               19 #define NDFC_ALE                0x04
 14 #define NDFC_DATA               0x08               20 #define NDFC_DATA               0x08
 15 #define NDFC_ECC                0x10               21 #define NDFC_ECC                0x10
 16 #define NDFC_BCFG0              0x30               22 #define NDFC_BCFG0              0x30
 17 #define NDFC_BCFG1              0x34               23 #define NDFC_BCFG1              0x34
 18 #define NDFC_BCFG2              0x38               24 #define NDFC_BCFG2              0x38
 19 #define NDFC_BCFG3              0x3c               25 #define NDFC_BCFG3              0x3c
 20 #define NDFC_CCR                0x40               26 #define NDFC_CCR                0x40
 21 #define NDFC_STAT               0x44               27 #define NDFC_STAT               0x44
 22 #define NDFC_HWCTL              0x48               28 #define NDFC_HWCTL              0x48
 23 #define NDFC_REVID              0x50               29 #define NDFC_REVID              0x50
 24                                                    30 
 25 #define NDFC_STAT_IS_READY      0x01000000         31 #define NDFC_STAT_IS_READY      0x01000000
 26                                                    32 
 27 #define NDFC_CCR_RESET_CE       0x80000000 /*      33 #define NDFC_CCR_RESET_CE       0x80000000 /* CE Reset */
 28 #define NDFC_CCR_RESET_ECC      0x40000000 /*      34 #define NDFC_CCR_RESET_ECC      0x40000000 /* ECC Reset */
 29 #define NDFC_CCR_RIE            0x20000000 /*      35 #define NDFC_CCR_RIE            0x20000000 /* Interrupt Enable on Device Rdy */
 30 #define NDFC_CCR_REN            0x10000000 /*      36 #define NDFC_CCR_REN            0x10000000 /* Enable wait for Rdy in LinearR */
 31 #define NDFC_CCR_ROMEN          0x08000000 /*      37 #define NDFC_CCR_ROMEN          0x08000000 /* Enable ROM In LinearR */
 32 #define NDFC_CCR_ARE            0x04000000 /*      38 #define NDFC_CCR_ARE            0x04000000 /* Auto-Read Enable */
 33 #define NDFC_CCR_BS(x)          (((x) & 0x3) <     39 #define NDFC_CCR_BS(x)          (((x) & 0x3) << 24) /* Select Bank on CE[x] */
 34 #define NDFC_CCR_BS_MASK        0x03000000 /*      40 #define NDFC_CCR_BS_MASK        0x03000000 /* Select Bank */
 35 #define NDFC_CCR_ARAC0          0x00000000 /*      41 #define NDFC_CCR_ARAC0          0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
 36 #define NDFC_CCR_ARAC1          0x00001000 /*      42 #define NDFC_CCR_ARAC1          0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
 37 #define NDFC_CCR_ARAC2          0x00002000 /*      43 #define NDFC_CCR_ARAC2          0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
 38 #define NDFC_CCR_ARAC3          0x00003000 /*      44 #define NDFC_CCR_ARAC3          0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
 39 #define NDFC_CCR_ARAC_MASK      0x00003000 /*      45 #define NDFC_CCR_ARAC_MASK      0x00003000 /* Auto-Read mode Addr Cycles */
 40 #define NDFC_CCR_RPG            0x0000C000 /*      46 #define NDFC_CCR_RPG            0x0000C000 /* Auto-Read Page */
 41 #define NDFC_CCR_EBCC           0x00000004 /*      47 #define NDFC_CCR_EBCC           0x00000004 /* EBC Configuration Completed */
 42 #define NDFC_CCR_DHC            0x00000002 /*      48 #define NDFC_CCR_DHC            0x00000002 /* Direct Hardware Control Enable */
 43                                                    49 
 44 #define NDFC_BxCFG_EN           0x80000000 /*      50 #define NDFC_BxCFG_EN           0x80000000 /* Bank Enable */
 45 #define NDFC_BxCFG_CED          0x40000000 /*      51 #define NDFC_BxCFG_CED          0x40000000 /* nCE Style */
 46 #define NDFC_BxCFG_SZ_MASK      0x08000000 /*      52 #define NDFC_BxCFG_SZ_MASK      0x08000000 /* Bank Size */
 47 #define NDFC_BxCFG_SZ_8BIT      0x00000000 /*      53 #define NDFC_BxCFG_SZ_8BIT      0x00000000 /* 8bit */
 48 #define NDFC_BxCFG_SZ_16BIT     0x08000000 /*      54 #define NDFC_BxCFG_SZ_16BIT     0x08000000 /* 16bit */
 49                                                    55 
 50 #define NDFC_MAX_BANKS          4                  56 #define NDFC_MAX_BANKS          4
 51                                                    57 
 52 struct ndfc_controller_settings {                  58 struct ndfc_controller_settings {
 53         uint32_t        ccr_settings;              59         uint32_t        ccr_settings;
 54         uint64_t        ndfc_erpn;                 60         uint64_t        ndfc_erpn;
 55 };                                                 61 };
 56                                                    62 
 57 struct ndfc_chip_settings {                        63 struct ndfc_chip_settings {
 58         uint32_t        bank_settings;             64         uint32_t        bank_settings;
 59 };                                                 65 };
 60                                                    66 
 61 #endif                                             67 #endif
 62                                                    68 

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