1 /* SPDX-License-Identifier: GPL-2.0 */ <<
2 /* Primary function overlay window definitions 1 /* Primary function overlay window definitions
3 * and service functions used by LPDDR chips 2 * and service functions used by LPDDR chips
4 */ 3 */
5 #ifndef __LINUX_MTD_PFOW_H 4 #ifndef __LINUX_MTD_PFOW_H
6 #define __LINUX_MTD_PFOW_H 5 #define __LINUX_MTD_PFOW_H
7 6
8 #include <linux/mtd/qinfo.h> 7 #include <linux/mtd/qinfo.h>
9 8
10 /* PFOW registers addressing */ 9 /* PFOW registers addressing */
11 /* Address of symbol "P" */ 10 /* Address of symbol "P" */
12 #define PFOW_QUERY_STRING_P 11 #define PFOW_QUERY_STRING_P 0x0000
13 /* Address of symbol "F" */ 12 /* Address of symbol "F" */
14 #define PFOW_QUERY_STRING_F 13 #define PFOW_QUERY_STRING_F 0x0002
15 /* Address of symbol "O" */ 14 /* Address of symbol "O" */
16 #define PFOW_QUERY_STRING_O 15 #define PFOW_QUERY_STRING_O 0x0004
17 /* Address of symbol "W" */ 16 /* Address of symbol "W" */
18 #define PFOW_QUERY_STRING_W 17 #define PFOW_QUERY_STRING_W 0x0006
19 /* Identification info for LPDDR chip */ 18 /* Identification info for LPDDR chip */
20 #define PFOW_MANUFACTURER_ID 19 #define PFOW_MANUFACTURER_ID 0x0020
21 #define PFOW_DEVICE_ID 20 #define PFOW_DEVICE_ID 0x0022
22 /* Address in PFOW where prog buffer can be fo !! 21 /* Address in PFOW where prog buffer can can be found */
23 #define PFOW_PROGRAM_BUFFER_OFFSET 22 #define PFOW_PROGRAM_BUFFER_OFFSET 0x0040
24 /* Size of program buffer in words */ 23 /* Size of program buffer in words */
25 #define PFOW_PROGRAM_BUFFER_SIZE 24 #define PFOW_PROGRAM_BUFFER_SIZE 0x0042
26 /* Address command code register */ 25 /* Address command code register */
27 #define PFOW_COMMAND_CODE 26 #define PFOW_COMMAND_CODE 0x0080
28 /* command data register */ 27 /* command data register */
29 #define PFOW_COMMAND_DATA 28 #define PFOW_COMMAND_DATA 0x0084
30 /* command address register lower address bits 29 /* command address register lower address bits */
31 #define PFOW_COMMAND_ADDRESS_L 30 #define PFOW_COMMAND_ADDRESS_L 0x0088
32 /* command address register upper address bits 31 /* command address register upper address bits */
33 #define PFOW_COMMAND_ADDRESS_H 32 #define PFOW_COMMAND_ADDRESS_H 0x008a
34 /* number of bytes to be proggrammed lower add 33 /* number of bytes to be proggrammed lower address bits */
35 #define PFOW_DATA_COUNT_L 34 #define PFOW_DATA_COUNT_L 0x0090
36 /* number of bytes to be proggrammed higher ad 35 /* number of bytes to be proggrammed higher address bits */
37 #define PFOW_DATA_COUNT_H 36 #define PFOW_DATA_COUNT_H 0x0092
38 /* command execution register, the only possib 37 /* command execution register, the only possible value is 0x01 */
39 #define PFOW_COMMAND_EXECUTE 38 #define PFOW_COMMAND_EXECUTE 0x00c0
40 /* 0x01 should be written at this address to c 39 /* 0x01 should be written at this address to clear buffer */
41 #define PFOW_CLEAR_PROGRAM_BUFFER 40 #define PFOW_CLEAR_PROGRAM_BUFFER 0x00c4
42 /* device program/erase suspend register */ 41 /* device program/erase suspend register */
43 #define PFOW_PROGRAM_ERASE_SUSPEND 42 #define PFOW_PROGRAM_ERASE_SUSPEND 0x00c8
44 /* device status register */ 43 /* device status register */
45 #define PFOW_DSR 44 #define PFOW_DSR 0x00cc
46 45
47 /* LPDDR memory device command codes */ 46 /* LPDDR memory device command codes */
48 /* They are possible values of PFOW command co 47 /* They are possible values of PFOW command code register */
49 #define LPDDR_WORD_PROGRAM 0x0041 48 #define LPDDR_WORD_PROGRAM 0x0041
50 #define LPDDR_BUFF_PROGRAM 0x00E9 49 #define LPDDR_BUFF_PROGRAM 0x00E9
51 #define LPDDR_BLOCK_ERASE 0x0020 50 #define LPDDR_BLOCK_ERASE 0x0020
52 #define LPDDR_LOCK_BLOCK 0x0061 51 #define LPDDR_LOCK_BLOCK 0x0061
53 #define LPDDR_UNLOCK_BLOCK 0x0062 52 #define LPDDR_UNLOCK_BLOCK 0x0062
54 #define LPDDR_READ_BLOCK_LOCK_STATUS 0x0065 53 #define LPDDR_READ_BLOCK_LOCK_STATUS 0x0065
55 #define LPDDR_INFO_QUERY 0x0098 54 #define LPDDR_INFO_QUERY 0x0098
56 #define LPDDR_READ_OTP 0x0097 55 #define LPDDR_READ_OTP 0x0097
57 #define LPDDR_PROG_OTP 0x00C0 56 #define LPDDR_PROG_OTP 0x00C0
58 #define LPDDR_RESUME 0x00D0 57 #define LPDDR_RESUME 0x00D0
59 58
60 /* Defines possible value of PFOW command exec 59 /* Defines possible value of PFOW command execution register */
61 #define LPDDR_START_EXECUTION 60 #define LPDDR_START_EXECUTION 0x0001
62 61
63 /* Defines possible value of PFOW program/eras 62 /* Defines possible value of PFOW program/erase suspend register */
64 #define LPDDR_SUSPEND 63 #define LPDDR_SUSPEND 0x0001
65 64
66 /* Possible values of PFOW device status regis 65 /* Possible values of PFOW device status register */
67 /* access R - read; RC read & clearable */ 66 /* access R - read; RC read & clearable */
68 #define DSR_DPS (1<<1) /* RC; 67 #define DSR_DPS (1<<1) /* RC; device protect status
69 * 0 - 68 * 0 - not protected 1 - locked */
70 #define DSR_PSS (1<<2) /* R; p 69 #define DSR_PSS (1<<2) /* R; program suspend status;
71 * 0-pr 70 * 0-prog in progress/completed,
72 * 1- p 71 * 1- prog suspended */
73 #define DSR_VPPS (1<<3) /* RC; 72 #define DSR_VPPS (1<<3) /* RC; 0-Vpp OK, * 1-Vpp low */
74 #define DSR_PROGRAM_STATUS (1<<4) /* RC; 73 #define DSR_PROGRAM_STATUS (1<<4) /* RC; 0-successful, 1-error */
75 #define DSR_ERASE_STATUS (1<<5) /* RC; 74 #define DSR_ERASE_STATUS (1<<5) /* RC; erase or blank check status;
76 * 0-su 75 * 0-success erase/blank check,
77 * 1 bl 76 * 1 blank check error */
78 #define DSR_ESS (1<<6) /* R; e 77 #define DSR_ESS (1<<6) /* R; erase suspend status;
79 * 0-er 78 * 0-erase in progress/complete,
80 * 1 er 79 * 1 erase suspended */
81 #define DSR_READY_STATUS (1<<7) /* R; D 80 #define DSR_READY_STATUS (1<<7) /* R; Device status
82 * 0-bu 81 * 0-busy,
83 * 1-re 82 * 1-ready */
84 #define DSR_RPS (0x3<<8) /* RC 83 #define DSR_RPS (0x3<<8) /* RC; region program status
85 * 00 - 84 * 00 - Success,
86 * 01-r 85 * 01-re-program attempt in region with
87 * obje 86 * object mode data,
88 * 10-o 87 * 10-object mode program w attempt in
89 * regi 88 * region with control mode data
90 * 11-a 89 * 11-attempt to program invalid half
91 * with 90 * with 0x41 command */
92 #define DSR_AOS (1<<12) /* RC; 91 #define DSR_AOS (1<<12) /* RC; 1- AO related failure */
93 #define DSR_AVAILABLE (1<<15) /* R; 92 #define DSR_AVAILABLE (1<<15) /* R; Device availbility
94 * 1 - 93 * 1 - Device available
95 * 0 - 94 * 0 - not available */
96 95
97 /* The superset of all possible error bits in 96 /* The superset of all possible error bits in DSR */
98 #define DSR_ERR 0x133A 97 #define DSR_ERR 0x133A
99 98
100 static inline void send_pfow_command(struct ma 99 static inline void send_pfow_command(struct map_info *map,
101 unsigned long 100 unsigned long cmd_code, unsigned long adr,
102 unsigned long 101 unsigned long len, map_word *datum)
103 { 102 {
104 int bits_per_chip = map_bankwidth(map) 103 int bits_per_chip = map_bankwidth(map) * 8;
105 104
106 map_write(map, CMD(cmd_code), map->pfo 105 map_write(map, CMD(cmd_code), map->pfow_base + PFOW_COMMAND_CODE);
107 map_write(map, CMD(adr & ((1<<bits_per 106 map_write(map, CMD(adr & ((1<<bits_per_chip) - 1)),
108 map->pfow_base 107 map->pfow_base + PFOW_COMMAND_ADDRESS_L);
109 map_write(map, CMD(adr>>bits_per_chip) 108 map_write(map, CMD(adr>>bits_per_chip),
110 map->pfow_base 109 map->pfow_base + PFOW_COMMAND_ADDRESS_H);
111 if (len) { 110 if (len) {
112 map_write(map, CMD(len & ((1<< 111 map_write(map, CMD(len & ((1<<bits_per_chip) - 1)),
113 map->p 112 map->pfow_base + PFOW_DATA_COUNT_L);
114 map_write(map, CMD(len>>bits_p 113 map_write(map, CMD(len>>bits_per_chip),
115 map->p 114 map->pfow_base + PFOW_DATA_COUNT_H);
116 } 115 }
117 if (datum) 116 if (datum)
118 map_write(map, *datum, map->pf 117 map_write(map, *datum, map->pfow_base + PFOW_COMMAND_DATA);
119 118
120 /* Command execution start */ 119 /* Command execution start */
121 map_write(map, CMD(LPDDR_START_EXECUTI 120 map_write(map, CMD(LPDDR_START_EXECUTION),
122 map->pfow_base + PFOW_ 121 map->pfow_base + PFOW_COMMAND_EXECUTE);
>> 122 }
>> 123
>> 124 static inline void print_drs_error(unsigned dsr)
>> 125 {
>> 126 int prog_status = (dsr & DSR_RPS) >> 8;
>> 127
>> 128 if (!(dsr & DSR_AVAILABLE))
>> 129 printk(KERN_NOTICE"DSR.15: (0) Device not Available\n");
>> 130 if ((prog_status & 0x03) == 0x03)
>> 131 printk(KERN_NOTICE"DSR.9,8: (11) Attempt to program invalid "
>> 132 "half with 41h command\n");
>> 133 else if (prog_status & 0x02)
>> 134 printk(KERN_NOTICE"DSR.9,8: (10) Object Mode Program attempt "
>> 135 "in region with Control Mode data\n");
>> 136 else if (prog_status & 0x01)
>> 137 printk(KERN_NOTICE"DSR.9,8: (01) Program attempt in region "
>> 138 "with Object Mode data\n");
>> 139 if (!(dsr & DSR_READY_STATUS))
>> 140 printk(KERN_NOTICE"DSR.7: (0) Device is Busy\n");
>> 141 if (dsr & DSR_ESS)
>> 142 printk(KERN_NOTICE"DSR.6: (1) Erase Suspended\n");
>> 143 if (dsr & DSR_ERASE_STATUS)
>> 144 printk(KERN_NOTICE"DSR.5: (1) Erase/Blank check error\n");
>> 145 if (dsr & DSR_PROGRAM_STATUS)
>> 146 printk(KERN_NOTICE"DSR.4: (1) Program Error\n");
>> 147 if (dsr & DSR_VPPS)
>> 148 printk(KERN_NOTICE"DSR.3: (1) Vpp low detect, operation "
>> 149 "aborted\n");
>> 150 if (dsr & DSR_PSS)
>> 151 printk(KERN_NOTICE"DSR.2: (1) Program suspended\n");
>> 152 if (dsr & DSR_DPS)
>> 153 printk(KERN_NOTICE"DSR.1: (1) Aborted Erase/Program attempt "
>> 154 "on locked block\n");
123 } 155 }
124 #endif /* __LINUX_MTD_PFOW_H */ 156 #endif /* __LINUX_MTD_PFOW_H */
125 157
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