1 /* SPDX-License-Identifier: GPL-2.0+ */ <<
2 /* 1 /*
3 * Copyright (C) 2014 Freescale Semiconductor, 2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License as published by
>> 6 * the Free Software Foundation; either version 2 of the License, or
>> 7 * (at your option) any later version.
4 */ 8 */
5 9
6 #ifndef __LINUX_MTD_SPI_NOR_H 10 #ifndef __LINUX_MTD_SPI_NOR_H
7 #define __LINUX_MTD_SPI_NOR_H 11 #define __LINUX_MTD_SPI_NOR_H
8 12
9 #include <linux/bitops.h> 13 #include <linux/bitops.h>
>> 14 #include <linux/mtd/cfi.h>
10 #include <linux/mtd/mtd.h> 15 #include <linux/mtd/mtd.h>
11 #include <linux/spi/spi-mem.h> !! 16
>> 17 /*
>> 18 * Manufacturer IDs
>> 19 *
>> 20 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
>> 21 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
>> 22 */
>> 23 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
>> 24 #define SNOR_MFR_GIGADEVICE 0xc8
>> 25 #define SNOR_MFR_INTEL CFI_MFR_INTEL
>> 26 #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
>> 27 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
>> 28 #define SNOR_MFR_SPANSION CFI_MFR_AMD
>> 29 #define SNOR_MFR_SST CFI_MFR_SST
>> 30 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
12 31
13 /* 32 /*
14 * Note on opcode nomenclature: some opcodes h 33 * Note on opcode nomenclature: some opcodes have a format like
15 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x 34 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
16 * of I/O lines used for the opcode, address, 35 * of I/O lines used for the opcode, address, and data (respectively). The
17 * FUNCTION has an optional suffix of '4', to 36 * FUNCTION has an optional suffix of '4', to represent an opcode which
18 * requires a 4-byte (32-bit) address. 37 * requires a 4-byte (32-bit) address.
19 */ 38 */
20 39
21 /* Flash opcodes. */ 40 /* Flash opcodes. */
22 #define SPINOR_OP_WRDI 0x04 /* Wri <<
23 #define SPINOR_OP_WREN 0x06 /* Wri 41 #define SPINOR_OP_WREN 0x06 /* Write enable */
24 #define SPINOR_OP_RDSR 0x05 /* Rea 42 #define SPINOR_OP_RDSR 0x05 /* Read status register */
25 #define SPINOR_OP_WRSR 0x01 /* Wri 43 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
26 #define SPINOR_OP_RDSR2 0x3f /* Rea 44 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
27 #define SPINOR_OP_WRSR2 0x3e /* Wri 45 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
28 #define SPINOR_OP_READ 0x03 /* Rea 46 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
29 #define SPINOR_OP_READ_FAST 0x0b /* Rea 47 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
30 #define SPINOR_OP_READ_1_1_2 0x3b /* Rea 48 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
31 #define SPINOR_OP_READ_1_2_2 0xbb /* Rea 49 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
32 #define SPINOR_OP_READ_1_1_4 0x6b /* Rea 50 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Rea 51 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
34 #define SPINOR_OP_READ_1_1_8 0x8b /* Rea <<
35 #define SPINOR_OP_READ_1_8_8 0xcb /* Rea <<
36 #define SPINOR_OP_PP 0x02 /* Pag 52 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
37 #define SPINOR_OP_PP_1_1_4 0x32 /* Qua 53 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
38 #define SPINOR_OP_PP_1_4_4 0x38 /* Qua 54 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
39 #define SPINOR_OP_PP_1_1_8 0x82 /* Oct <<
40 #define SPINOR_OP_PP_1_8_8 0xc2 /* Oct <<
41 #define SPINOR_OP_BE_4K 0x20 /* Era 55 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
42 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Era 56 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
43 #define SPINOR_OP_BE_32K 0x52 /* Era 57 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
44 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Era 58 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
45 #define SPINOR_OP_SE 0xd8 /* Sec 59 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
46 #define SPINOR_OP_RDID 0x9f /* Rea 60 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
47 #define SPINOR_OP_RDSFDP 0x5a /* Rea 61 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
48 #define SPINOR_OP_RDCR 0x35 /* Rea 62 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
49 #define SPINOR_OP_SRSTEN 0x66 /* Sof !! 63 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
50 #define SPINOR_OP_SRST 0x99 /* Sof !! 64 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
51 #define SPINOR_OP_GBULK 0x98 /* Glo !! 65 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
>> 66 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
52 67
53 /* 4-byte address opcodes - used on Spansion a 68 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
54 #define SPINOR_OP_READ_4B 0x13 /* Rea 69 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
55 #define SPINOR_OP_READ_FAST_4B 0x0c /* Rea 70 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
56 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Rea 71 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
57 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Rea 72 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
58 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Rea 73 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
59 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Rea 74 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
60 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Rea <<
61 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Rea <<
62 #define SPINOR_OP_PP_4B 0x12 /* Pag 75 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
63 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Qua 76 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
64 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Qua 77 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
65 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Oct <<
66 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Oct <<
67 #define SPINOR_OP_BE_4K_4B 0x21 /* Era 78 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
68 #define SPINOR_OP_BE_32K_4B 0x5c /* Era 79 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
69 #define SPINOR_OP_SE_4B 0xdc /* Sec 80 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
70 81
71 /* Double Transfer Rate opcodes - defined in J 82 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
72 #define SPINOR_OP_READ_1_1_1_DTR 0x0d 83 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
73 #define SPINOR_OP_READ_1_2_2_DTR 0xbd 84 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
74 #define SPINOR_OP_READ_1_4_4_DTR 0xed 85 #define SPINOR_OP_READ_1_4_4_DTR 0xed
75 86
76 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e 87 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
77 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe 88 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
78 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee 89 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
79 90
80 /* Used for SST flashes only. */ 91 /* Used for SST flashes only. */
81 #define SPINOR_OP_BP 0x02 /* Byt 92 #define SPINOR_OP_BP 0x02 /* Byte program */
>> 93 #define SPINOR_OP_WRDI 0x04 /* Write disable */
82 #define SPINOR_OP_AAI_WP 0xad /* Aut 94 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
83 95
>> 96 /* Used for S3AN flashes only */
>> 97 #define SPINOR_OP_XSE 0x50 /* Sector erase */
>> 98 #define SPINOR_OP_XPP 0x82 /* Page program */
>> 99 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
>> 100
>> 101 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
>> 102 #define XSR_RDY BIT(7) /* Ready */
>> 103
>> 104
84 /* Used for Macronix and Winbond flashes. */ 105 /* Used for Macronix and Winbond flashes. */
85 #define SPINOR_OP_EN4B 0xb7 /* Ent 106 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
86 #define SPINOR_OP_EX4B 0xe9 /* Exi 107 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
87 108
88 /* Used for Spansion flashes only. */ 109 /* Used for Spansion flashes only. */
89 #define SPINOR_OP_BRWR 0x17 /* Ban 110 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
>> 111 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
90 112
91 /* Used for Micron flashes only. */ 113 /* Used for Micron flashes only. */
92 #define SPINOR_OP_RD_EVCR 0x65 /* Read 114 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
93 #define SPINOR_OP_WD_EVCR 0x61 /* Writ 115 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
94 116
95 /* Used for GigaDevices and Winbond flashes. * <<
96 #define SPINOR_OP_ESECR 0x44 /* Era <<
97 #define SPINOR_OP_PSECR 0x42 /* Pro <<
98 #define SPINOR_OP_RSECR 0x48 /* Rea <<
99 <<
100 /* Status Register bits. */ 117 /* Status Register bits. */
101 #define SR_WIP BIT(0) /* Wri 118 #define SR_WIP BIT(0) /* Write in progress */
102 #define SR_WEL BIT(1) /* Wri 119 #define SR_WEL BIT(1) /* Write enable latch */
103 /* meaning of other SR_* bits may differ betwe 120 /* meaning of other SR_* bits may differ between vendors */
104 #define SR_BP0 BIT(2) /* Blo 121 #define SR_BP0 BIT(2) /* Block protect 0 */
105 #define SR_BP1 BIT(3) /* Blo 122 #define SR_BP1 BIT(3) /* Block protect 1 */
106 #define SR_BP2 BIT(4) /* Blo 123 #define SR_BP2 BIT(4) /* Block protect 2 */
107 #define SR_BP3 BIT(5) /* Blo !! 124 #define SR_TB BIT(5) /* Top/Bottom protect */
108 #define SR_TB_BIT5 BIT(5) /* Top <<
109 #define SR_BP3_BIT6 BIT(6) /* Blo <<
110 #define SR_TB_BIT6 BIT(6) /* Top <<
111 #define SR_SRWD BIT(7) /* SR 125 #define SR_SRWD BIT(7) /* SR write protect */
112 /* Spansion/Cypress specific status bits */ 126 /* Spansion/Cypress specific status bits */
113 #define SR_E_ERR BIT(5) 127 #define SR_E_ERR BIT(5)
114 #define SR_P_ERR BIT(6) 128 #define SR_P_ERR BIT(6)
115 129
116 #define SR1_QUAD_EN_BIT6 BIT(6) !! 130 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
117 <<
118 #define SR_BP_SHIFT 2 <<
119 131
120 /* Enhanced Volatile Configuration Register bi 132 /* Enhanced Volatile Configuration Register bits */
121 #define EVCR_QUAD_EN_MICRON BIT(7) /* Mic 133 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
122 134
>> 135 /* Flag Status Register bits */
>> 136 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
>> 137 #define FSR_E_ERR BIT(5) /* Erase operation status */
>> 138 #define FSR_P_ERR BIT(4) /* Program operation status */
>> 139 #define FSR_PT_ERR BIT(1) /* Protection error bit */
>> 140
>> 141 /* Configuration Register bits. */
>> 142 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
>> 143
123 /* Status Register 2 bits. */ 144 /* Status Register 2 bits. */
124 #define SR2_QUAD_EN_BIT1 BIT(1) <<
125 #define SR2_LB1 BIT(3) /* Sec <<
126 #define SR2_LB2 BIT(4) /* Sec <<
127 #define SR2_LB3 BIT(5) /* Sec <<
128 #define SR2_QUAD_EN_BIT7 BIT(7) 145 #define SR2_QUAD_EN_BIT7 BIT(7)
129 146
130 /* Supported SPI protocols */ 147 /* Supported SPI protocols */
131 #define SNOR_PROTO_INST_MASK GENMASK(23, 16 148 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
132 #define SNOR_PROTO_INST_SHIFT 16 149 #define SNOR_PROTO_INST_SHIFT 16
133 #define SNOR_PROTO_INST(_nbits) \ 150 #define SNOR_PROTO_INST(_nbits) \
134 ((((unsigned long)(_nbits)) << SNOR_PR 151 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
135 SNOR_PROTO_INST_MASK) 152 SNOR_PROTO_INST_MASK)
136 153
137 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8) 154 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
138 #define SNOR_PROTO_ADDR_SHIFT 8 155 #define SNOR_PROTO_ADDR_SHIFT 8
139 #define SNOR_PROTO_ADDR(_nbits) \ 156 #define SNOR_PROTO_ADDR(_nbits) \
140 ((((unsigned long)(_nbits)) << SNOR_PR 157 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
141 SNOR_PROTO_ADDR_MASK) 158 SNOR_PROTO_ADDR_MASK)
142 159
143 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0) 160 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
144 #define SNOR_PROTO_DATA_SHIFT 0 161 #define SNOR_PROTO_DATA_SHIFT 0
145 #define SNOR_PROTO_DATA(_nbits) \ 162 #define SNOR_PROTO_DATA(_nbits) \
146 ((((unsigned long)(_nbits)) << SNOR_PR 163 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
147 SNOR_PROTO_DATA_MASK) 164 SNOR_PROTO_DATA_MASK)
148 165
149 #define SNOR_PROTO_IS_DTR BIT(24) /* Dou 166 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
150 167
151 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbit 168 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
152 (SNOR_PROTO_INST(_inst_nbits) | 169 (SNOR_PROTO_INST(_inst_nbits) | \
153 SNOR_PROTO_ADDR(_addr_nbits) | 170 SNOR_PROTO_ADDR(_addr_nbits) | \
154 SNOR_PROTO_DATA(_data_nbits)) 171 SNOR_PROTO_DATA(_data_nbits))
155 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbit 172 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
156 (SNOR_PROTO_IS_DTR | 173 (SNOR_PROTO_IS_DTR | \
157 SNOR_PROTO_STR(_inst_nbits, _addr_nbi 174 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
158 175
159 enum spi_nor_protocol { 176 enum spi_nor_protocol {
160 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1 177 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
161 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1 178 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
162 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1 179 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
163 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1 180 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
164 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2 181 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
165 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4 182 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
166 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8 183 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
167 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2 184 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
168 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4 185 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
169 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8 186 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
170 187
171 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR( 188 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
172 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR( 189 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
173 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR( 190 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
174 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR( 191 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
175 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR( <<
176 }; 192 };
177 193
178 static inline bool spi_nor_protocol_is_dtr(enu 194 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
179 { 195 {
180 return !!(proto & SNOR_PROTO_IS_DTR); 196 return !!(proto & SNOR_PROTO_IS_DTR);
181 } 197 }
182 198
183 static inline u8 spi_nor_get_protocol_inst_nbi 199 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
184 { 200 {
185 return ((unsigned long)(proto & SNOR_P 201 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
186 SNOR_PROTO_INST_SHIFT; 202 SNOR_PROTO_INST_SHIFT;
187 } 203 }
188 204
189 static inline u8 spi_nor_get_protocol_addr_nbi 205 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
190 { 206 {
191 return ((unsigned long)(proto & SNOR_P 207 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
192 SNOR_PROTO_ADDR_SHIFT; 208 SNOR_PROTO_ADDR_SHIFT;
193 } 209 }
194 210
195 static inline u8 spi_nor_get_protocol_data_nbi 211 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
196 { 212 {
197 return ((unsigned long)(proto & SNOR_P 213 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
198 SNOR_PROTO_DATA_SHIFT; 214 SNOR_PROTO_DATA_SHIFT;
199 } 215 }
200 216
201 static inline u8 spi_nor_get_protocol_width(en 217 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
202 { 218 {
203 return spi_nor_get_protocol_data_nbits 219 return spi_nor_get_protocol_data_nbits(proto);
204 } 220 }
205 221
>> 222 #define SPI_NOR_MAX_CMD_SIZE 8
>> 223 enum spi_nor_ops {
>> 224 SPI_NOR_OPS_READ = 0,
>> 225 SPI_NOR_OPS_WRITE,
>> 226 SPI_NOR_OPS_ERASE,
>> 227 SPI_NOR_OPS_LOCK,
>> 228 SPI_NOR_OPS_UNLOCK,
>> 229 };
>> 230
>> 231 enum spi_nor_option_flags {
>> 232 SNOR_F_USE_FSR = BIT(0),
>> 233 SNOR_F_HAS_SR_TB = BIT(1),
>> 234 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
>> 235 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
>> 236 SNOR_F_READY_XSR_RDY = BIT(4),
>> 237 SNOR_F_USE_CLSR = BIT(5),
>> 238 SNOR_F_BROKEN_RESET = BIT(6),
>> 239 };
>> 240
206 /** 241 /**
207 * struct spi_nor_hwcaps - Structure for descr !! 242 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
208 * supported by the SPI controller (bus master !! 243 * @size: the size of the sector/block erased by the erase type.
209 * @mask: the bitmask listing al !! 244 * JEDEC JESD216B imposes erase sizes to be a power of 2.
>> 245 * @size_shift: @size is a power of 2, the shift is stored in
>> 246 * @size_shift.
>> 247 * @size_mask: the size mask based on @size_shift.
>> 248 * @opcode: the SPI command op code to erase the sector/block.
>> 249 * @idx: Erase Type index as sorted in the Basic Flash Parameter
>> 250 * Table. It will be used to synchronize the supported
>> 251 * Erase Types with the ones identified in the SFDP
>> 252 * optional tables.
210 */ 253 */
211 struct spi_nor_hwcaps { !! 254 struct spi_nor_erase_type {
212 u32 mask; !! 255 u32 size;
>> 256 u32 size_shift;
>> 257 u32 size_mask;
>> 258 u8 opcode;
>> 259 u8 idx;
213 }; 260 };
214 261
215 /* !! 262 /**
216 *(Fast) Read capabilities. !! 263 * struct spi_nor_erase_command - Used for non-uniform erases
217 * MUST be ordered by priority: the higher bit !! 264 * The structure is used to describe a list of erase commands to be executed
218 * As a matter of performances, it is relevant !! 265 * once we validate that the erase can be performed. The elements in the list
219 * then Quad SPI protocols before Dual SPI pro !! 266 * are run-length encoded.
220 * (Slow) Read. !! 267 * @list: for inclusion into the list of erase commands.
>> 268 * @count: how many times the same erase command should be
>> 269 * consecutively used.
>> 270 * @size: the size of the sector/block erased by the command.
>> 271 * @opcode: the SPI command op code to erase the sector/block.
221 */ 272 */
222 #define SNOR_HWCAPS_READ_MASK GENMAS !! 273 struct spi_nor_erase_command {
223 #define SNOR_HWCAPS_READ BIT(0) !! 274 struct list_head list;
224 #define SNOR_HWCAPS_READ_FAST BIT(1) !! 275 u32 count;
225 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) !! 276 u32 size;
226 !! 277 u8 opcode;
227 #define SNOR_HWCAPS_READ_DUAL GENMAS !! 278 };
228 #define SNOR_HWCAPS_READ_1_1_2 BIT(3) <<
229 #define SNOR_HWCAPS_READ_1_2_2 BIT(4) <<
230 #define SNOR_HWCAPS_READ_2_2_2 BIT(5) <<
231 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) <<
232 <<
233 #define SNOR_HWCAPS_READ_QUAD GENMAS <<
234 #define SNOR_HWCAPS_READ_1_1_4 BIT(7) <<
235 #define SNOR_HWCAPS_READ_1_4_4 BIT(8) <<
236 #define SNOR_HWCAPS_READ_4_4_4 BIT(9) <<
237 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10 <<
238 <<
239 #define SNOR_HWCAPS_READ_OCTAL GENMAS <<
240 #define SNOR_HWCAPS_READ_1_1_8 BIT(11 <<
241 #define SNOR_HWCAPS_READ_1_8_8 BIT(12 <<
242 #define SNOR_HWCAPS_READ_8_8_8 BIT(13 <<
243 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14 <<
244 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15 <<
245 279
246 /* !! 280 /**
247 * Page Program capabilities. !! 281 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
248 * MUST be ordered by priority: the higher bit !! 282 * @offset: the offset in the data array of erase region start.
249 * Like (Fast) Read capabilities, Octal/Quad S !! 283 * LSB bits are used as a bitmask encoding flags to
250 * legacy SPI 1-1-1 protocol. !! 284 * determine if this region is overlaid, if this region is
251 * Note that Dual Page Programs are not suppor !! 285 * the last in the SPI NOR flash memory and to indicate
252 * JEDEC/SFDP standard to define them. Also at !! 286 * all the supported erase commands inside this region.
253 * implements such commands. !! 287 * The erase types are sorted in ascending order with the
>> 288 * smallest Erase Type size being at BIT(0).
>> 289 * @size: the size of the region in bytes.
254 */ 290 */
255 #define SNOR_HWCAPS_PP_MASK GENMAS !! 291 struct spi_nor_erase_region {
256 #define SNOR_HWCAPS_PP BIT(16 !! 292 u64 offset;
>> 293 u64 size;
>> 294 };
257 295
258 #define SNOR_HWCAPS_PP_QUAD GENMAS !! 296 #define SNOR_ERASE_TYPE_MAX 4
259 #define SNOR_HWCAPS_PP_1_1_4 BIT(17 !! 297 #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
260 #define SNOR_HWCAPS_PP_1_4_4 BIT(18 <<
261 #define SNOR_HWCAPS_PP_4_4_4 BIT(19 <<
262 <<
263 #define SNOR_HWCAPS_PP_OCTAL GENMAS <<
264 #define SNOR_HWCAPS_PP_1_1_8 BIT(20 <<
265 #define SNOR_HWCAPS_PP_1_8_8 BIT(21 <<
266 #define SNOR_HWCAPS_PP_8_8_8 BIT(22 <<
267 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23 <<
268 <<
269 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_R <<
270 SNOR_HWCAPS_R <<
271 SNOR_HWCAPS_R <<
272 SNOR_HWCAPS_P <<
273 SNOR_HWCAPS_P <<
274 <<
275 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_R <<
276 SNOR_HWCAPS_P <<
277 <<
278 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_R <<
279 SNOR_HWCAPS_R <<
280 SNOR_HWCAPS_R <<
281 SNOR_HWCAPS_R <<
282 SNOR_HWCAPS_R <<
283 298
284 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_R !! 299 #define SNOR_LAST_REGION BIT(4)
285 SNOR_HWCAPS_P !! 300 #define SNOR_OVERLAID_REGION BIT(5)
286 301
287 /* Forward declaration that is used in 'struct !! 302 #define SNOR_ERASE_FLAGS_MAX 6
288 struct spi_nor; !! 303 #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
289 304
290 /** 305 /**
291 * struct spi_nor_controller_ops - SPI NOR con !! 306 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
292 * operations. !! 307 * @regions: array of erase regions. The regions are consecutive in
293 * @prepare: [OPTIONAL] do some pre !! 308 * address space. Walking through the regions is done
294 * read/write/erase/lock/ !! 309 * incrementally.
295 * @unprepare: [OPTIONAL] do some pos !! 310 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
296 * read/write/erase/lock/ !! 311 * sector size (legacy implementation).
297 * @read_reg: read out the register. !! 312 * @erase_type: an array of erase types shared by all the regions.
298 * @write_reg: write data to the regi !! 313 * The erase types are sorted in ascending order, with the
299 * @read: read data from the SPI !! 314 * smallest Erase Type size being the first member in the
300 * @write: write data to the SPI !! 315 * erase_type array.
301 * @erase: erase a sector of the !! 316 * @uniform_erase_type: bitmask encoding erase types that can erase the
302 * not provided by the dr !! 317 * entire memory. This member is completed at init by
303 * opcode via write_reg() !! 318 * uniform and non-uniform SPI NOR flash memories if they
304 */ !! 319 * support at least one erase type that can erase the
305 struct spi_nor_controller_ops { !! 320 * entire memory.
306 int (*prepare)(struct spi_nor *nor); !! 321 */
307 void (*unprepare)(struct spi_nor *nor) !! 322 struct spi_nor_erase_map {
308 int (*read_reg)(struct spi_nor *nor, u !! 323 struct spi_nor_erase_region *regions;
309 int (*write_reg)(struct spi_nor *nor, !! 324 struct spi_nor_erase_region uniform_region;
310 size_t len); !! 325 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
311 !! 326 u8 uniform_erase_type;
312 ssize_t (*read)(struct spi_nor *nor, l <<
313 ssize_t (*write)(struct spi_nor *nor, <<
314 const u8 *buf); <<
315 int (*erase)(struct spi_nor *nor, loff <<
316 }; 327 };
317 328
318 /** 329 /**
319 * enum spi_nor_cmd_ext - describes the comman !! 330 * struct flash_info - Forward declaration of a structure used internally by
320 * @SPI_NOR_EXT_NONE: no extension. This is th !! 331 * spi_nor_scan()
321 * SPI mode <<
322 * @SPI_NOR_EXT_REPEAT: the extension is same <<
323 * @SPI_NOR_EXT_INVERT: the extension is the b <<
324 * @SPI_NOR_EXT_HEX: the extension is any hex <<
325 * combine to form a 16-bit <<
326 */ <<
327 enum spi_nor_cmd_ext { <<
328 SPI_NOR_EXT_NONE = 0, <<
329 SPI_NOR_EXT_REPEAT, <<
330 SPI_NOR_EXT_INVERT, <<
331 SPI_NOR_EXT_HEX, <<
332 }; <<
333 <<
334 /* <<
335 * Forward declarations that are used internal <<
336 * drivers. <<
337 */ 332 */
338 struct flash_info; 333 struct flash_info;
339 struct spi_nor_manufacturer; <<
340 struct spi_nor_flash_parameter; <<
341 334
342 /** 335 /**
343 * struct spi_nor - Structure for defining the !! 336 * struct spi_nor - Structure for defining a the SPI NOR layer
344 * @mtd: an mtd_info structure !! 337 * @mtd: point to a mtd_info structure
345 * @lock: the lock for the read/ 338 * @lock: the lock for the read/write/erase/lock/unlock operations
346 * @rww: Read-While-Write (RWW) !! 339 * @dev: point to a spi device, or a spi nor controller device.
347 * @rww.wait: wait queue for the RWW !! 340 * @info: spi-nor part JDEC MFR id and other info
348 * @rww.ongoing_io: the bus is busy !! 341 * @page_size: the page size of the SPI NOR
349 * @rww.ongoing_rd: a read is ongoing on t !! 342 * @addr_width: number of address bytes
350 * @rww.ongoing_pe: a program/erase is ong <<
351 * @rww.used_banks: bitmap of the banks in <<
352 * @dev: pointer to an SPI devi <<
353 * @spimem: pointer to the SPI mem <<
354 * @bouncebuf: bounce buffer used whe <<
355 * layer is not DMA-able <<
356 * @bouncebuf_size: size of the bounce buf <<
357 * @id: The flash's ID bytes. <<
358 * SPI_NOR_MAX_ID_LEN byt <<
359 * @info: SPI NOR part JEDEC MFR <<
360 * @manufacturer: SPI NOR manufacturer <<
361 * @addr_nbytes: number of address byte <<
362 * @erase_opcode: the opcode for erasing 343 * @erase_opcode: the opcode for erasing a sector
363 * @read_opcode: the read opcode 344 * @read_opcode: the read opcode
364 * @read_dummy: the dummy needed by th 345 * @read_dummy: the dummy needed by the read operation
365 * @program_opcode: the program opcode 346 * @program_opcode: the program opcode
366 * @sst_write_second: used by the SST write 347 * @sst_write_second: used by the SST write operation
367 * @flags: flag options for the c !! 348 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
368 * @cmd_ext_type: the command opcode ext <<
369 * @read_proto: the SPI protocol for r 349 * @read_proto: the SPI protocol for read operations
370 * @write_proto: the SPI protocol for w 350 * @write_proto: the SPI protocol for write operations
371 * @reg_proto: the SPI protocol for r !! 351 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
372 * @sfdp: the SFDP data of the f !! 352 * @cmd_buf: used by the write_reg
373 * @debugfs_root: pointer to the debugfs !! 353 * @erase_map: the erase map of the SPI NOR
374 * @controller_ops: SPI NOR controller dri !! 354 * @prepare: [OPTIONAL] do some preparations for the
375 * @params: [FLASH-SPECIFIC] SPI N !! 355 * read/write/erase/lock/unlock operations
376 * The structure includes !! 356 * @unprepare: [OPTIONAL] do some post work after the
377 * settings that can be o !! 357 * read/write/erase/lock/unlock operations
378 * hooks, or dynamically !! 358 * @read_reg: [DRIVER-SPECIFIC] read out the register
379 * @dirmap: pointers to struct spi !! 359 * @write_reg: [DRIVER-SPECIFIC] write data to the register
380 * @priv: pointer to the private !! 360 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
>> 361 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
>> 362 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
>> 363 * at the offset @offs; if not provided by the driver,
>> 364 * spi-nor will send the erase opcode via write_reg()
>> 365 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
>> 366 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
>> 367 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
>> 368 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
>> 369 * completely locked
>> 370 * @priv: the private data
381 */ 371 */
382 struct spi_nor { 372 struct spi_nor {
383 struct mtd_info mtd; 373 struct mtd_info mtd;
384 struct mutex lock; 374 struct mutex lock;
385 struct spi_nor_rww { <<
386 wait_queue_head_t wait; <<
387 bool ongoing_io; <<
388 bool ongoing_rd; <<
389 bool ongoing_pe; <<
390 unsigned int used_banks; <<
391 } rww; <<
392 struct device *dev; 375 struct device *dev;
393 struct spi_mem *spimem; <<
394 u8 *bouncebuf; <<
395 size_t bouncebuf_size <<
396 u8 *id; <<
397 const struct flash_info *info; 376 const struct flash_info *info;
398 const struct spi_nor_manufacturer *man !! 377 u32 page_size;
399 u8 addr_nbytes; !! 378 u8 addr_width;
400 u8 erase_opcode; 379 u8 erase_opcode;
401 u8 read_opcode; 380 u8 read_opcode;
402 u8 read_dummy; 381 u8 read_dummy;
403 u8 program_opcode 382 u8 program_opcode;
404 enum spi_nor_protocol read_proto; 383 enum spi_nor_protocol read_proto;
405 enum spi_nor_protocol write_proto; 384 enum spi_nor_protocol write_proto;
406 enum spi_nor_protocol reg_proto; 385 enum spi_nor_protocol reg_proto;
407 bool sst_write_seco 386 bool sst_write_second;
408 u32 flags; 387 u32 flags;
409 enum spi_nor_cmd_ext cmd_ext_type; !! 388 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
410 struct sfdp *sfdp; !! 389 struct spi_nor_erase_map erase_map;
411 struct dentry *debugfs_root; !! 390
412 !! 391 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
413 const struct spi_nor_controller_ops *c !! 392 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
414 !! 393 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
415 struct spi_nor_flash_parameter *params !! 394 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
416 !! 395
417 struct { !! 396 ssize_t (*read)(struct spi_nor *nor, loff_t from,
418 struct spi_mem_dirmap_desc *rd !! 397 size_t len, u_char *read_buf);
419 struct spi_mem_dirmap_desc *wd !! 398 ssize_t (*write)(struct spi_nor *nor, loff_t to,
420 } dirmap; !! 399 size_t len, const u_char *write_buf);
>> 400 int (*erase)(struct spi_nor *nor, loff_t offs);
>> 401
>> 402 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
>> 403 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
>> 404 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
>> 405 int (*quad_enable)(struct spi_nor *nor);
421 406
422 void *priv; 407 void *priv;
423 }; 408 };
424 409
>> 410 static u64 __maybe_unused
>> 411 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
>> 412 {
>> 413 return region->offset & SNOR_LAST_REGION;
>> 414 }
>> 415
>> 416 static u64 __maybe_unused
>> 417 spi_nor_region_end(const struct spi_nor_erase_region *region)
>> 418 {
>> 419 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
>> 420 }
>> 421
>> 422 static void __maybe_unused
>> 423 spi_nor_region_mark_end(struct spi_nor_erase_region *region)
>> 424 {
>> 425 region->offset |= SNOR_LAST_REGION;
>> 426 }
>> 427
>> 428 static void __maybe_unused
>> 429 spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
>> 430 {
>> 431 region->offset |= SNOR_OVERLAID_REGION;
>> 432 }
>> 433
>> 434 static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
>> 435 {
>> 436 return !!nor->erase_map.uniform_erase_type;
>> 437 }
>> 438
425 static inline void spi_nor_set_flash_node(stru 439 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
426 stru 440 struct device_node *np)
427 { 441 {
428 mtd_set_of_node(&nor->mtd, np); 442 mtd_set_of_node(&nor->mtd, np);
429 } 443 }
430 444
431 static inline struct device_node *spi_nor_get_ 445 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
432 { 446 {
433 return mtd_get_of_node(&nor->mtd); 447 return mtd_get_of_node(&nor->mtd);
434 } 448 }
435 449
436 /** 450 /**
>> 451 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
>> 452 * supported by the SPI controller (bus master).
>> 453 * @mask: the bitmask listing all the supported hw capabilies
>> 454 */
>> 455 struct spi_nor_hwcaps {
>> 456 u32 mask;
>> 457 };
>> 458
>> 459 /*
>> 460 *(Fast) Read capabilities.
>> 461 * MUST be ordered by priority: the higher bit position, the higher priority.
>> 462 * As a matter of performances, it is relevant to use Octo SPI protocols first,
>> 463 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
>> 464 * (Slow) Read.
>> 465 */
>> 466 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
>> 467 #define SNOR_HWCAPS_READ BIT(0)
>> 468 #define SNOR_HWCAPS_READ_FAST BIT(1)
>> 469 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
>> 470
>> 471 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
>> 472 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
>> 473 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
>> 474 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
>> 475 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
>> 476
>> 477 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
>> 478 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
>> 479 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
>> 480 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
>> 481 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
>> 482
>> 483 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
>> 484 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
>> 485 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
>> 486 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
>> 487 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
>> 488
>> 489 /*
>> 490 * Page Program capabilities.
>> 491 * MUST be ordered by priority: the higher bit position, the higher priority.
>> 492 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
>> 493 * legacy SPI 1-1-1 protocol.
>> 494 * Note that Dual Page Programs are not supported because there is no existing
>> 495 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
>> 496 * implements such commands.
>> 497 */
>> 498 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
>> 499 #define SNOR_HWCAPS_PP BIT(16)
>> 500
>> 501 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
>> 502 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
>> 503 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
>> 504 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
>> 505
>> 506 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
>> 507 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
>> 508 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
>> 509 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
>> 510
>> 511 /**
437 * spi_nor_scan() - scan the SPI NOR 512 * spi_nor_scan() - scan the SPI NOR
438 * @nor: the spi_nor structure 513 * @nor: the spi_nor structure
439 * @name: the chip type name 514 * @name: the chip type name
440 * @hwcaps: the hardware capabilities supp 515 * @hwcaps: the hardware capabilities supported by the controller driver
441 * 516 *
442 * The drivers can use this function to scan t !! 517 * The drivers can use this fuction to scan the SPI NOR.
443 * In the scanning, it will try to get all the 518 * In the scanning, it will try to get all the necessary information to
444 * fill the mtd_info{} and the spi_nor{}. 519 * fill the mtd_info{} and the spi_nor{}.
445 * 520 *
446 * The chip type name can be provided through 521 * The chip type name can be provided through the @name parameter.
447 * 522 *
448 * Return: 0 for success, others for failure. 523 * Return: 0 for success, others for failure.
449 */ 524 */
450 int spi_nor_scan(struct spi_nor *nor, const ch 525 int spi_nor_scan(struct spi_nor *nor, const char *name,
451 const struct spi_nor_hwcaps * 526 const struct spi_nor_hwcaps *hwcaps);
>> 527
>> 528 /**
>> 529 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
>> 530 * @nor: the spi_nor structure
>> 531 */
>> 532 void spi_nor_restore(struct spi_nor *nor);
452 533
453 #endif 534 #endif
454 535
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