1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, 3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 */ 4 */
5 5
6 #ifndef __LINUX_MTD_SPI_NOR_H 6 #ifndef __LINUX_MTD_SPI_NOR_H
7 #define __LINUX_MTD_SPI_NOR_H 7 #define __LINUX_MTD_SPI_NOR_H
8 8
9 #include <linux/bitops.h> 9 #include <linux/bitops.h>
>> 10 #include <linux/mtd/cfi.h>
10 #include <linux/mtd/mtd.h> 11 #include <linux/mtd/mtd.h>
11 #include <linux/spi/spi-mem.h> 12 #include <linux/spi/spi-mem.h>
12 13
13 /* 14 /*
14 * Note on opcode nomenclature: some opcodes h 15 * Note on opcode nomenclature: some opcodes have a format like
15 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x 16 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
16 * of I/O lines used for the opcode, address, 17 * of I/O lines used for the opcode, address, and data (respectively). The
17 * FUNCTION has an optional suffix of '4', to 18 * FUNCTION has an optional suffix of '4', to represent an opcode which
18 * requires a 4-byte (32-bit) address. 19 * requires a 4-byte (32-bit) address.
19 */ 20 */
20 21
21 /* Flash opcodes. */ 22 /* Flash opcodes. */
22 #define SPINOR_OP_WRDI 0x04 /* Wri 23 #define SPINOR_OP_WRDI 0x04 /* Write disable */
23 #define SPINOR_OP_WREN 0x06 /* Wri 24 #define SPINOR_OP_WREN 0x06 /* Write enable */
24 #define SPINOR_OP_RDSR 0x05 /* Rea 25 #define SPINOR_OP_RDSR 0x05 /* Read status register */
25 #define SPINOR_OP_WRSR 0x01 /* Wri 26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
26 #define SPINOR_OP_RDSR2 0x3f /* Rea 27 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
27 #define SPINOR_OP_WRSR2 0x3e /* Wri 28 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
28 #define SPINOR_OP_READ 0x03 /* Rea 29 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
29 #define SPINOR_OP_READ_FAST 0x0b /* Rea 30 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
30 #define SPINOR_OP_READ_1_1_2 0x3b /* Rea 31 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
31 #define SPINOR_OP_READ_1_2_2 0xbb /* Rea 32 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
32 #define SPINOR_OP_READ_1_1_4 0x6b /* Rea 33 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Rea 34 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
34 #define SPINOR_OP_READ_1_1_8 0x8b /* Rea 35 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
35 #define SPINOR_OP_READ_1_8_8 0xcb /* Rea 36 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
36 #define SPINOR_OP_PP 0x02 /* Pag 37 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
37 #define SPINOR_OP_PP_1_1_4 0x32 /* Qua 38 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
38 #define SPINOR_OP_PP_1_4_4 0x38 /* Qua 39 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
39 #define SPINOR_OP_PP_1_1_8 0x82 /* Oct 40 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
40 #define SPINOR_OP_PP_1_8_8 0xc2 /* Oct 41 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
41 #define SPINOR_OP_BE_4K 0x20 /* Era 42 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
42 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Era 43 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
43 #define SPINOR_OP_BE_32K 0x52 /* Era 44 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
44 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Era 45 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
45 #define SPINOR_OP_SE 0xd8 /* Sec 46 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
46 #define SPINOR_OP_RDID 0x9f /* Rea 47 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
47 #define SPINOR_OP_RDSFDP 0x5a /* Rea 48 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
48 #define SPINOR_OP_RDCR 0x35 /* Rea 49 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
>> 50 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
>> 51 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
>> 52 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
>> 53 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
49 #define SPINOR_OP_SRSTEN 0x66 /* Sof 54 #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
50 #define SPINOR_OP_SRST 0x99 /* Sof 55 #define SPINOR_OP_SRST 0x99 /* Software Reset */
51 #define SPINOR_OP_GBULK 0x98 /* Glo 56 #define SPINOR_OP_GBULK 0x98 /* Global Block Unlock */
52 57
53 /* 4-byte address opcodes - used on Spansion a 58 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
54 #define SPINOR_OP_READ_4B 0x13 /* Rea 59 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
55 #define SPINOR_OP_READ_FAST_4B 0x0c /* Rea 60 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
56 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Rea 61 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
57 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Rea 62 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
58 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Rea 63 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
59 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Rea 64 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
60 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Rea 65 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
61 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Rea 66 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
62 #define SPINOR_OP_PP_4B 0x12 /* Pag 67 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
63 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Qua 68 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
64 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Qua 69 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
65 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Oct 70 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
66 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Oct 71 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
67 #define SPINOR_OP_BE_4K_4B 0x21 /* Era 72 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
68 #define SPINOR_OP_BE_32K_4B 0x5c /* Era 73 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
69 #define SPINOR_OP_SE_4B 0xdc /* Sec 74 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
70 75
71 /* Double Transfer Rate opcodes - defined in J 76 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
72 #define SPINOR_OP_READ_1_1_1_DTR 0x0d 77 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
73 #define SPINOR_OP_READ_1_2_2_DTR 0xbd 78 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
74 #define SPINOR_OP_READ_1_4_4_DTR 0xed 79 #define SPINOR_OP_READ_1_4_4_DTR 0xed
75 80
76 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e 81 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
77 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe 82 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
78 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee 83 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
79 84
80 /* Used for SST flashes only. */ 85 /* Used for SST flashes only. */
81 #define SPINOR_OP_BP 0x02 /* Byt 86 #define SPINOR_OP_BP 0x02 /* Byte program */
82 #define SPINOR_OP_AAI_WP 0xad /* Aut 87 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
83 88
>> 89 /* Used for S3AN flashes only */
>> 90 #define SPINOR_OP_XSE 0x50 /* Sector erase */
>> 91 #define SPINOR_OP_XPP 0x82 /* Page program */
>> 92 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
>> 93
>> 94 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
>> 95 #define XSR_RDY BIT(7) /* Ready */
>> 96
>> 97
84 /* Used for Macronix and Winbond flashes. */ 98 /* Used for Macronix and Winbond flashes. */
85 #define SPINOR_OP_EN4B 0xb7 /* Ent 99 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
86 #define SPINOR_OP_EX4B 0xe9 /* Exi 100 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
87 101
88 /* Used for Spansion flashes only. */ 102 /* Used for Spansion flashes only. */
89 #define SPINOR_OP_BRWR 0x17 /* Ban 103 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
>> 104 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
90 105
91 /* Used for Micron flashes only. */ 106 /* Used for Micron flashes only. */
92 #define SPINOR_OP_RD_EVCR 0x65 /* Read 107 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
93 #define SPINOR_OP_WD_EVCR 0x61 /* Writ 108 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
94 109
95 /* Used for GigaDevices and Winbond flashes. * <<
96 #define SPINOR_OP_ESECR 0x44 /* Era <<
97 #define SPINOR_OP_PSECR 0x42 /* Pro <<
98 #define SPINOR_OP_RSECR 0x48 /* Rea <<
99 <<
100 /* Status Register bits. */ 110 /* Status Register bits. */
101 #define SR_WIP BIT(0) /* Wri 111 #define SR_WIP BIT(0) /* Write in progress */
102 #define SR_WEL BIT(1) /* Wri 112 #define SR_WEL BIT(1) /* Write enable latch */
103 /* meaning of other SR_* bits may differ betwe 113 /* meaning of other SR_* bits may differ between vendors */
104 #define SR_BP0 BIT(2) /* Blo 114 #define SR_BP0 BIT(2) /* Block protect 0 */
105 #define SR_BP1 BIT(3) /* Blo 115 #define SR_BP1 BIT(3) /* Block protect 1 */
106 #define SR_BP2 BIT(4) /* Blo 116 #define SR_BP2 BIT(4) /* Block protect 2 */
107 #define SR_BP3 BIT(5) /* Blo 117 #define SR_BP3 BIT(5) /* Block protect 3 */
108 #define SR_TB_BIT5 BIT(5) /* Top 118 #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
109 #define SR_BP3_BIT6 BIT(6) /* Blo 119 #define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
110 #define SR_TB_BIT6 BIT(6) /* Top 120 #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
111 #define SR_SRWD BIT(7) /* SR 121 #define SR_SRWD BIT(7) /* SR write protect */
112 /* Spansion/Cypress specific status bits */ 122 /* Spansion/Cypress specific status bits */
113 #define SR_E_ERR BIT(5) 123 #define SR_E_ERR BIT(5)
114 #define SR_P_ERR BIT(6) 124 #define SR_P_ERR BIT(6)
115 125
116 #define SR1_QUAD_EN_BIT6 BIT(6) 126 #define SR1_QUAD_EN_BIT6 BIT(6)
117 127
118 #define SR_BP_SHIFT 2 128 #define SR_BP_SHIFT 2
119 129
120 /* Enhanced Volatile Configuration Register bi 130 /* Enhanced Volatile Configuration Register bits */
121 #define EVCR_QUAD_EN_MICRON BIT(7) /* Mic 131 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
122 132
>> 133 /* Flag Status Register bits */
>> 134 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
>> 135 #define FSR_E_ERR BIT(5) /* Erase operation status */
>> 136 #define FSR_P_ERR BIT(4) /* Program operation status */
>> 137 #define FSR_PT_ERR BIT(1) /* Protection error bit */
>> 138
123 /* Status Register 2 bits. */ 139 /* Status Register 2 bits. */
124 #define SR2_QUAD_EN_BIT1 BIT(1) 140 #define SR2_QUAD_EN_BIT1 BIT(1)
125 #define SR2_LB1 BIT(3) /* Sec <<
126 #define SR2_LB2 BIT(4) /* Sec <<
127 #define SR2_LB3 BIT(5) /* Sec <<
128 #define SR2_QUAD_EN_BIT7 BIT(7) 141 #define SR2_QUAD_EN_BIT7 BIT(7)
129 142
130 /* Supported SPI protocols */ 143 /* Supported SPI protocols */
131 #define SNOR_PROTO_INST_MASK GENMASK(23, 16 144 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
132 #define SNOR_PROTO_INST_SHIFT 16 145 #define SNOR_PROTO_INST_SHIFT 16
133 #define SNOR_PROTO_INST(_nbits) \ 146 #define SNOR_PROTO_INST(_nbits) \
134 ((((unsigned long)(_nbits)) << SNOR_PR 147 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
135 SNOR_PROTO_INST_MASK) 148 SNOR_PROTO_INST_MASK)
136 149
137 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8) 150 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
138 #define SNOR_PROTO_ADDR_SHIFT 8 151 #define SNOR_PROTO_ADDR_SHIFT 8
139 #define SNOR_PROTO_ADDR(_nbits) \ 152 #define SNOR_PROTO_ADDR(_nbits) \
140 ((((unsigned long)(_nbits)) << SNOR_PR 153 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
141 SNOR_PROTO_ADDR_MASK) 154 SNOR_PROTO_ADDR_MASK)
142 155
143 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0) 156 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
144 #define SNOR_PROTO_DATA_SHIFT 0 157 #define SNOR_PROTO_DATA_SHIFT 0
145 #define SNOR_PROTO_DATA(_nbits) \ 158 #define SNOR_PROTO_DATA(_nbits) \
146 ((((unsigned long)(_nbits)) << SNOR_PR 159 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
147 SNOR_PROTO_DATA_MASK) 160 SNOR_PROTO_DATA_MASK)
148 161
149 #define SNOR_PROTO_IS_DTR BIT(24) /* Dou 162 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
150 163
151 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbit 164 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
152 (SNOR_PROTO_INST(_inst_nbits) | 165 (SNOR_PROTO_INST(_inst_nbits) | \
153 SNOR_PROTO_ADDR(_addr_nbits) | 166 SNOR_PROTO_ADDR(_addr_nbits) | \
154 SNOR_PROTO_DATA(_data_nbits)) 167 SNOR_PROTO_DATA(_data_nbits))
155 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbit 168 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
156 (SNOR_PROTO_IS_DTR | 169 (SNOR_PROTO_IS_DTR | \
157 SNOR_PROTO_STR(_inst_nbits, _addr_nbi 170 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
158 171
159 enum spi_nor_protocol { 172 enum spi_nor_protocol {
160 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1 173 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
161 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1 174 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
162 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1 175 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
163 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1 176 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
164 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2 177 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
165 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4 178 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
166 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8 179 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
167 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2 180 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
168 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4 181 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
169 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8 182 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
170 183
171 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR( 184 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
172 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR( 185 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
173 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR( 186 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
174 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR( 187 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
175 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR( 188 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
176 }; 189 };
177 190
178 static inline bool spi_nor_protocol_is_dtr(enu 191 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
179 { 192 {
180 return !!(proto & SNOR_PROTO_IS_DTR); 193 return !!(proto & SNOR_PROTO_IS_DTR);
181 } 194 }
182 195
183 static inline u8 spi_nor_get_protocol_inst_nbi 196 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
184 { 197 {
185 return ((unsigned long)(proto & SNOR_P 198 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
186 SNOR_PROTO_INST_SHIFT; 199 SNOR_PROTO_INST_SHIFT;
187 } 200 }
188 201
189 static inline u8 spi_nor_get_protocol_addr_nbi 202 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
190 { 203 {
191 return ((unsigned long)(proto & SNOR_P 204 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
192 SNOR_PROTO_ADDR_SHIFT; 205 SNOR_PROTO_ADDR_SHIFT;
193 } 206 }
194 207
195 static inline u8 spi_nor_get_protocol_data_nbi 208 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
196 { 209 {
197 return ((unsigned long)(proto & SNOR_P 210 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
198 SNOR_PROTO_DATA_SHIFT; 211 SNOR_PROTO_DATA_SHIFT;
199 } 212 }
200 213
201 static inline u8 spi_nor_get_protocol_width(en 214 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
202 { 215 {
203 return spi_nor_get_protocol_data_nbits 216 return spi_nor_get_protocol_data_nbits(proto);
204 } 217 }
205 218
206 /** 219 /**
207 * struct spi_nor_hwcaps - Structure for descr 220 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
208 * supported by the SPI controller (bus master 221 * supported by the SPI controller (bus master).
209 * @mask: the bitmask listing al 222 * @mask: the bitmask listing all the supported hw capabilies
210 */ 223 */
211 struct spi_nor_hwcaps { 224 struct spi_nor_hwcaps {
212 u32 mask; 225 u32 mask;
213 }; 226 };
214 227
215 /* 228 /*
216 *(Fast) Read capabilities. 229 *(Fast) Read capabilities.
217 * MUST be ordered by priority: the higher bit 230 * MUST be ordered by priority: the higher bit position, the higher priority.
218 * As a matter of performances, it is relevant 231 * As a matter of performances, it is relevant to use Octal SPI protocols first,
219 * then Quad SPI protocols before Dual SPI pro 232 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
220 * (Slow) Read. 233 * (Slow) Read.
221 */ 234 */
222 #define SNOR_HWCAPS_READ_MASK GENMAS 235 #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
223 #define SNOR_HWCAPS_READ BIT(0) 236 #define SNOR_HWCAPS_READ BIT(0)
224 #define SNOR_HWCAPS_READ_FAST BIT(1) 237 #define SNOR_HWCAPS_READ_FAST BIT(1)
225 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) 238 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
226 239
227 #define SNOR_HWCAPS_READ_DUAL GENMAS 240 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
228 #define SNOR_HWCAPS_READ_1_1_2 BIT(3) 241 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
229 #define SNOR_HWCAPS_READ_1_2_2 BIT(4) 242 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
230 #define SNOR_HWCAPS_READ_2_2_2 BIT(5) 243 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
231 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6) 244 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
232 245
233 #define SNOR_HWCAPS_READ_QUAD GENMAS 246 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
234 #define SNOR_HWCAPS_READ_1_1_4 BIT(7) 247 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
235 #define SNOR_HWCAPS_READ_1_4_4 BIT(8) 248 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
236 #define SNOR_HWCAPS_READ_4_4_4 BIT(9) 249 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
237 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10 250 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
238 251
239 #define SNOR_HWCAPS_READ_OCTAL GENMAS 252 #define SNOR_HWCAPS_READ_OCTAL GENMASK(15, 11)
240 #define SNOR_HWCAPS_READ_1_1_8 BIT(11 253 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
241 #define SNOR_HWCAPS_READ_1_8_8 BIT(12 254 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
242 #define SNOR_HWCAPS_READ_8_8_8 BIT(13 255 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
243 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14 256 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
244 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15 257 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
245 258
246 /* 259 /*
247 * Page Program capabilities. 260 * Page Program capabilities.
248 * MUST be ordered by priority: the higher bit 261 * MUST be ordered by priority: the higher bit position, the higher priority.
249 * Like (Fast) Read capabilities, Octal/Quad S 262 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
250 * legacy SPI 1-1-1 protocol. 263 * legacy SPI 1-1-1 protocol.
251 * Note that Dual Page Programs are not suppor 264 * Note that Dual Page Programs are not supported because there is no existing
252 * JEDEC/SFDP standard to define them. Also at 265 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
253 * implements such commands. 266 * implements such commands.
254 */ 267 */
255 #define SNOR_HWCAPS_PP_MASK GENMAS 268 #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
256 #define SNOR_HWCAPS_PP BIT(16 269 #define SNOR_HWCAPS_PP BIT(16)
257 270
258 #define SNOR_HWCAPS_PP_QUAD GENMAS 271 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
259 #define SNOR_HWCAPS_PP_1_1_4 BIT(17 272 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
260 #define SNOR_HWCAPS_PP_1_4_4 BIT(18 273 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
261 #define SNOR_HWCAPS_PP_4_4_4 BIT(19 274 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
262 275
263 #define SNOR_HWCAPS_PP_OCTAL GENMAS 276 #define SNOR_HWCAPS_PP_OCTAL GENMASK(23, 20)
264 #define SNOR_HWCAPS_PP_1_1_8 BIT(20 277 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
265 #define SNOR_HWCAPS_PP_1_8_8 BIT(21 278 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
266 #define SNOR_HWCAPS_PP_8_8_8 BIT(22 279 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
267 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23 280 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
268 281
269 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_R 282 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
270 SNOR_HWCAPS_R 283 SNOR_HWCAPS_READ_4_4_4 | \
271 SNOR_HWCAPS_R 284 SNOR_HWCAPS_READ_8_8_8 | \
272 SNOR_HWCAPS_P 285 SNOR_HWCAPS_PP_4_4_4 | \
273 SNOR_HWCAPS_P 286 SNOR_HWCAPS_PP_8_8_8)
274 287
275 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_R 288 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
276 SNOR_HWCAPS_P 289 SNOR_HWCAPS_PP_8_8_8_DTR)
277 290
278 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_R 291 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
279 SNOR_HWCAPS_R 292 SNOR_HWCAPS_READ_1_2_2_DTR | \
280 SNOR_HWCAPS_R 293 SNOR_HWCAPS_READ_1_4_4_DTR | \
281 SNOR_HWCAPS_R 294 SNOR_HWCAPS_READ_1_8_8_DTR | \
282 SNOR_HWCAPS_R 295 SNOR_HWCAPS_READ_8_8_8_DTR)
283 296
284 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_R 297 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
285 SNOR_HWCAPS_P 298 SNOR_HWCAPS_PP_MASK)
286 299
287 /* Forward declaration that is used in 'struct 300 /* Forward declaration that is used in 'struct spi_nor_controller_ops' */
288 struct spi_nor; 301 struct spi_nor;
289 302
290 /** 303 /**
291 * struct spi_nor_controller_ops - SPI NOR con 304 * struct spi_nor_controller_ops - SPI NOR controller driver specific
292 * operations. 305 * operations.
293 * @prepare: [OPTIONAL] do some pre 306 * @prepare: [OPTIONAL] do some preparations for the
294 * read/write/erase/lock/ 307 * read/write/erase/lock/unlock operations.
295 * @unprepare: [OPTIONAL] do some pos 308 * @unprepare: [OPTIONAL] do some post work after the
296 * read/write/erase/lock/ 309 * read/write/erase/lock/unlock operations.
297 * @read_reg: read out the register. 310 * @read_reg: read out the register.
298 * @write_reg: write data to the regi 311 * @write_reg: write data to the register.
299 * @read: read data from the SPI 312 * @read: read data from the SPI NOR.
300 * @write: write data to the SPI 313 * @write: write data to the SPI NOR.
301 * @erase: erase a sector of the 314 * @erase: erase a sector of the SPI NOR at the offset @offs; if
302 * not provided by the dr 315 * not provided by the driver, SPI NOR will send the erase
303 * opcode via write_reg() 316 * opcode via write_reg().
304 */ 317 */
305 struct spi_nor_controller_ops { 318 struct spi_nor_controller_ops {
306 int (*prepare)(struct spi_nor *nor); 319 int (*prepare)(struct spi_nor *nor);
307 void (*unprepare)(struct spi_nor *nor) 320 void (*unprepare)(struct spi_nor *nor);
308 int (*read_reg)(struct spi_nor *nor, u 321 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
309 int (*write_reg)(struct spi_nor *nor, 322 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
310 size_t len); 323 size_t len);
311 324
312 ssize_t (*read)(struct spi_nor *nor, l 325 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
313 ssize_t (*write)(struct spi_nor *nor, 326 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
314 const u8 *buf); 327 const u8 *buf);
315 int (*erase)(struct spi_nor *nor, loff 328 int (*erase)(struct spi_nor *nor, loff_t offs);
316 }; 329 };
317 330
318 /** 331 /**
319 * enum spi_nor_cmd_ext - describes the comman 332 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
320 * @SPI_NOR_EXT_NONE: no extension. This is th 333 * @SPI_NOR_EXT_NONE: no extension. This is the default, and is used in Legacy
321 * SPI mode 334 * SPI mode
322 * @SPI_NOR_EXT_REPEAT: the extension is same 335 * @SPI_NOR_EXT_REPEAT: the extension is same as the opcode
323 * @SPI_NOR_EXT_INVERT: the extension is the b 336 * @SPI_NOR_EXT_INVERT: the extension is the bitwise inverse of the opcode
324 * @SPI_NOR_EXT_HEX: the extension is any hex 337 * @SPI_NOR_EXT_HEX: the extension is any hex value. The command and opcode
325 * combine to form a 16-bit 338 * combine to form a 16-bit opcode.
326 */ 339 */
327 enum spi_nor_cmd_ext { 340 enum spi_nor_cmd_ext {
328 SPI_NOR_EXT_NONE = 0, 341 SPI_NOR_EXT_NONE = 0,
329 SPI_NOR_EXT_REPEAT, 342 SPI_NOR_EXT_REPEAT,
330 SPI_NOR_EXT_INVERT, 343 SPI_NOR_EXT_INVERT,
331 SPI_NOR_EXT_HEX, 344 SPI_NOR_EXT_HEX,
332 }; 345 };
333 346
334 /* 347 /*
335 * Forward declarations that are used internal 348 * Forward declarations that are used internally by the core and manufacturer
336 * drivers. 349 * drivers.
337 */ 350 */
338 struct flash_info; 351 struct flash_info;
339 struct spi_nor_manufacturer; 352 struct spi_nor_manufacturer;
340 struct spi_nor_flash_parameter; 353 struct spi_nor_flash_parameter;
341 354
342 /** 355 /**
343 * struct spi_nor - Structure for defining the 356 * struct spi_nor - Structure for defining the SPI NOR layer
344 * @mtd: an mtd_info structure 357 * @mtd: an mtd_info structure
345 * @lock: the lock for the read/ 358 * @lock: the lock for the read/write/erase/lock/unlock operations
346 * @rww: Read-While-Write (RWW) <<
347 * @rww.wait: wait queue for the RWW <<
348 * @rww.ongoing_io: the bus is busy <<
349 * @rww.ongoing_rd: a read is ongoing on t <<
350 * @rww.ongoing_pe: a program/erase is ong <<
351 * @rww.used_banks: bitmap of the banks in <<
352 * @dev: pointer to an SPI devi 359 * @dev: pointer to an SPI device or an SPI NOR controller device
353 * @spimem: pointer to the SPI mem 360 * @spimem: pointer to the SPI memory device
354 * @bouncebuf: bounce buffer used whe 361 * @bouncebuf: bounce buffer used when the buffer passed by the MTD
355 * layer is not DMA-able 362 * layer is not DMA-able
356 * @bouncebuf_size: size of the bounce buf 363 * @bouncebuf_size: size of the bounce buffer
357 * @id: The flash's ID bytes. <<
358 * SPI_NOR_MAX_ID_LEN byt <<
359 * @info: SPI NOR part JEDEC MFR 364 * @info: SPI NOR part JEDEC MFR ID and other info
360 * @manufacturer: SPI NOR manufacturer 365 * @manufacturer: SPI NOR manufacturer
361 * @addr_nbytes: number of address byte !! 366 * @page_size: the page size of the SPI NOR
>> 367 * @addr_width: number of address bytes
362 * @erase_opcode: the opcode for erasing 368 * @erase_opcode: the opcode for erasing a sector
363 * @read_opcode: the read opcode 369 * @read_opcode: the read opcode
364 * @read_dummy: the dummy needed by th 370 * @read_dummy: the dummy needed by the read operation
365 * @program_opcode: the program opcode 371 * @program_opcode: the program opcode
366 * @sst_write_second: used by the SST write 372 * @sst_write_second: used by the SST write operation
367 * @flags: flag options for the c 373 * @flags: flag options for the current SPI NOR (SNOR_F_*)
368 * @cmd_ext_type: the command opcode ext 374 * @cmd_ext_type: the command opcode extension type for DTR mode.
369 * @read_proto: the SPI protocol for r 375 * @read_proto: the SPI protocol for read operations
370 * @write_proto: the SPI protocol for w 376 * @write_proto: the SPI protocol for write operations
371 * @reg_proto: the SPI protocol for r 377 * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations
372 * @sfdp: the SFDP data of the f <<
373 * @debugfs_root: pointer to the debugfs <<
374 * @controller_ops: SPI NOR controller dri 378 * @controller_ops: SPI NOR controller driver specific operations.
375 * @params: [FLASH-SPECIFIC] SPI N 379 * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings.
376 * The structure includes 380 * The structure includes legacy flash parameters and
377 * settings that can be o 381 * settings that can be overwritten by the spi_nor_fixups
378 * hooks, or dynamically 382 * hooks, or dynamically when parsing the SFDP tables.
379 * @dirmap: pointers to struct spi 383 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
380 * @priv: pointer to the private 384 * @priv: pointer to the private data
381 */ 385 */
382 struct spi_nor { 386 struct spi_nor {
383 struct mtd_info mtd; 387 struct mtd_info mtd;
384 struct mutex lock; 388 struct mutex lock;
385 struct spi_nor_rww { <<
386 wait_queue_head_t wait; <<
387 bool ongoing_io; <<
388 bool ongoing_rd; <<
389 bool ongoing_pe; <<
390 unsigned int used_banks; <<
391 } rww; <<
392 struct device *dev; 389 struct device *dev;
393 struct spi_mem *spimem; 390 struct spi_mem *spimem;
394 u8 *bouncebuf; 391 u8 *bouncebuf;
395 size_t bouncebuf_size 392 size_t bouncebuf_size;
396 u8 *id; <<
397 const struct flash_info *info; 393 const struct flash_info *info;
398 const struct spi_nor_manufacturer *man 394 const struct spi_nor_manufacturer *manufacturer;
399 u8 addr_nbytes; !! 395 u32 page_size;
>> 396 u8 addr_width;
400 u8 erase_opcode; 397 u8 erase_opcode;
401 u8 read_opcode; 398 u8 read_opcode;
402 u8 read_dummy; 399 u8 read_dummy;
403 u8 program_opcode 400 u8 program_opcode;
404 enum spi_nor_protocol read_proto; 401 enum spi_nor_protocol read_proto;
405 enum spi_nor_protocol write_proto; 402 enum spi_nor_protocol write_proto;
406 enum spi_nor_protocol reg_proto; 403 enum spi_nor_protocol reg_proto;
407 bool sst_write_seco 404 bool sst_write_second;
408 u32 flags; 405 u32 flags;
409 enum spi_nor_cmd_ext cmd_ext_type; 406 enum spi_nor_cmd_ext cmd_ext_type;
410 struct sfdp *sfdp; <<
411 struct dentry *debugfs_root; <<
412 407
413 const struct spi_nor_controller_ops *c 408 const struct spi_nor_controller_ops *controller_ops;
414 409
415 struct spi_nor_flash_parameter *params 410 struct spi_nor_flash_parameter *params;
416 411
417 struct { 412 struct {
418 struct spi_mem_dirmap_desc *rd 413 struct spi_mem_dirmap_desc *rdesc;
419 struct spi_mem_dirmap_desc *wd 414 struct spi_mem_dirmap_desc *wdesc;
420 } dirmap; 415 } dirmap;
421 416
422 void *priv; 417 void *priv;
423 }; 418 };
424 419
425 static inline void spi_nor_set_flash_node(stru 420 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
426 stru 421 struct device_node *np)
427 { 422 {
428 mtd_set_of_node(&nor->mtd, np); 423 mtd_set_of_node(&nor->mtd, np);
429 } 424 }
430 425
431 static inline struct device_node *spi_nor_get_ 426 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
432 { 427 {
433 return mtd_get_of_node(&nor->mtd); 428 return mtd_get_of_node(&nor->mtd);
434 } 429 }
435 430
436 /** 431 /**
437 * spi_nor_scan() - scan the SPI NOR 432 * spi_nor_scan() - scan the SPI NOR
438 * @nor: the spi_nor structure 433 * @nor: the spi_nor structure
439 * @name: the chip type name 434 * @name: the chip type name
440 * @hwcaps: the hardware capabilities supp 435 * @hwcaps: the hardware capabilities supported by the controller driver
441 * 436 *
442 * The drivers can use this function to scan t 437 * The drivers can use this function to scan the SPI NOR.
443 * In the scanning, it will try to get all the 438 * In the scanning, it will try to get all the necessary information to
444 * fill the mtd_info{} and the spi_nor{}. 439 * fill the mtd_info{} and the spi_nor{}.
445 * 440 *
446 * The chip type name can be provided through 441 * The chip type name can be provided through the @name parameter.
447 * 442 *
448 * Return: 0 for success, others for failure. 443 * Return: 0 for success, others for failure.
449 */ 444 */
450 int spi_nor_scan(struct spi_nor *nor, const ch 445 int spi_nor_scan(struct spi_nor *nor, const char *name,
451 const struct spi_nor_hwcaps * 446 const struct spi_nor_hwcaps *hwcaps);
>> 447
>> 448 /**
>> 449 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
>> 450 * @nor: the spi_nor structure
>> 451 */
>> 452 void spi_nor_restore(struct spi_nor *nor);
452 453
453 #endif 454 #endif
454 455
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