1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright (c) 2016-2017 Micron Technology, 3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 * 4 *
5 * Authors: 5 * Authors:
6 * Peter Pan <peterpandong@micron.com> 6 * Peter Pan <peterpandong@micron.com>
7 */ 7 */
8 #ifndef __LINUX_MTD_SPINAND_H 8 #ifndef __LINUX_MTD_SPINAND_H
9 #define __LINUX_MTD_SPINAND_H 9 #define __LINUX_MTD_SPINAND_H
10 10
11 #include <linux/mutex.h> 11 #include <linux/mutex.h>
12 #include <linux/bitops.h> 12 #include <linux/bitops.h>
13 #include <linux/device.h> 13 #include <linux/device.h>
14 #include <linux/mtd/mtd.h> 14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h> 15 #include <linux/mtd/nand.h>
16 #include <linux/spi/spi.h> 16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h> 17 #include <linux/spi/spi-mem.h>
18 18
19 /** 19 /**
20 * Standard SPI NAND flash operations 20 * Standard SPI NAND flash operations
21 */ 21 */
22 22
23 #define SPINAND_RESET_OP 23 #define SPINAND_RESET_OP \
24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), 24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
25 SPI_MEM_OP_NO_ADDR, 25 SPI_MEM_OP_NO_ADDR, \
26 SPI_MEM_OP_NO_DUMMY, 26 SPI_MEM_OP_NO_DUMMY, \
27 SPI_MEM_OP_NO_DATA) 27 SPI_MEM_OP_NO_DATA)
28 28
29 #define SPINAND_WR_EN_DIS_OP(enable) 29 #define SPINAND_WR_EN_DIS_OP(enable) \
30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0 30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
31 SPI_MEM_OP_NO_ADDR, 31 SPI_MEM_OP_NO_ADDR, \
32 SPI_MEM_OP_NO_DUMMY, 32 SPI_MEM_OP_NO_DUMMY, \
33 SPI_MEM_OP_NO_DATA) 33 SPI_MEM_OP_NO_DATA)
34 34
35 #define SPINAND_READID_OP(naddr, ndummy, buf, !! 35 #define SPINAND_READID_OP(ndummy, buf, len) \
36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), 36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
37 SPI_MEM_OP_ADDR(naddr, 0, 1 !! 37 SPI_MEM_OP_NO_ADDR, \
38 SPI_MEM_OP_DUMMY(ndummy, 1) 38 SPI_MEM_OP_DUMMY(ndummy, 1), \
39 SPI_MEM_OP_DATA_IN(len, buf 39 SPI_MEM_OP_DATA_IN(len, buf, 1))
40 40
41 #define SPINAND_SET_FEATURE_OP(reg, valptr) 41 #define SPINAND_SET_FEATURE_OP(reg, valptr) \
42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), 42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
43 SPI_MEM_OP_ADDR(1, reg, 1), 43 SPI_MEM_OP_ADDR(1, reg, 1), \
44 SPI_MEM_OP_NO_DUMMY, 44 SPI_MEM_OP_NO_DUMMY, \
45 SPI_MEM_OP_DATA_OUT(1, valp 45 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
46 46
47 #define SPINAND_GET_FEATURE_OP(reg, valptr) 47 #define SPINAND_GET_FEATURE_OP(reg, valptr) \
48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), 48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
49 SPI_MEM_OP_ADDR(1, reg, 1), 49 SPI_MEM_OP_ADDR(1, reg, 1), \
50 SPI_MEM_OP_NO_DUMMY, 50 SPI_MEM_OP_NO_DUMMY, \
51 SPI_MEM_OP_DATA_IN(1, valpt 51 SPI_MEM_OP_DATA_IN(1, valptr, 1))
52 52
53 #define SPINAND_BLK_ERASE_OP(addr) 53 #define SPINAND_BLK_ERASE_OP(addr) \
54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), 54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
55 SPI_MEM_OP_ADDR(3, addr, 1) 55 SPI_MEM_OP_ADDR(3, addr, 1), \
56 SPI_MEM_OP_NO_DUMMY, 56 SPI_MEM_OP_NO_DUMMY, \
57 SPI_MEM_OP_NO_DATA) 57 SPI_MEM_OP_NO_DATA)
58 58
59 #define SPINAND_PAGE_READ_OP(addr) 59 #define SPINAND_PAGE_READ_OP(addr) \
60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), 60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
61 SPI_MEM_OP_ADDR(3, addr, 1) 61 SPI_MEM_OP_ADDR(3, addr, 1), \
62 SPI_MEM_OP_NO_DUMMY, 62 SPI_MEM_OP_NO_DUMMY, \
63 SPI_MEM_OP_NO_DATA) 63 SPI_MEM_OP_NO_DATA)
64 64
65 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, 65 #define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \
66 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b 66 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
67 SPI_MEM_OP_ADDR(2, addr, 1) 67 SPI_MEM_OP_ADDR(2, addr, 1), \
68 SPI_MEM_OP_DUMMY(ndummy, 1) 68 SPI_MEM_OP_DUMMY(ndummy, 1), \
69 SPI_MEM_OP_DATA_IN(len, buf 69 SPI_MEM_OP_DATA_IN(len, buf, 1))
70 70
71 #define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fas <<
72 SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b <<
73 SPI_MEM_OP_ADDR(3, addr, 1) <<
74 SPI_MEM_OP_DUMMY(ndummy, 1) <<
75 SPI_MEM_OP_DATA_IN(len, buf <<
76 <<
77 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(add 71 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
78 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), 72 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
79 SPI_MEM_OP_ADDR(2, addr, 1) 73 SPI_MEM_OP_ADDR(2, addr, 1), \
80 SPI_MEM_OP_DUMMY(ndummy, 1) 74 SPI_MEM_OP_DUMMY(ndummy, 1), \
81 SPI_MEM_OP_DATA_IN(len, buf 75 SPI_MEM_OP_DATA_IN(len, buf, 2))
82 76
83 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A( <<
84 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), <<
85 SPI_MEM_OP_ADDR(3, addr, 1) <<
86 SPI_MEM_OP_DUMMY(ndummy, 1) <<
87 SPI_MEM_OP_DATA_IN(len, buf <<
88 <<
89 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(add 77 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
90 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), 78 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
91 SPI_MEM_OP_ADDR(2, addr, 1) 79 SPI_MEM_OP_ADDR(2, addr, 1), \
92 SPI_MEM_OP_DUMMY(ndummy, 1) 80 SPI_MEM_OP_DUMMY(ndummy, 1), \
93 SPI_MEM_OP_DATA_IN(len, buf 81 SPI_MEM_OP_DATA_IN(len, buf, 4))
94 82
95 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A( <<
96 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), <<
97 SPI_MEM_OP_ADDR(3, addr, 1) <<
98 SPI_MEM_OP_DUMMY(ndummy, 1) <<
99 SPI_MEM_OP_DATA_IN(len, buf <<
100 <<
101 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP 83 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
102 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), 84 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
103 SPI_MEM_OP_ADDR(2, addr, 2) 85 SPI_MEM_OP_ADDR(2, addr, 2), \
104 SPI_MEM_OP_DUMMY(ndummy, 2) 86 SPI_MEM_OP_DUMMY(ndummy, 2), \
105 SPI_MEM_OP_DATA_IN(len, buf 87 SPI_MEM_OP_DATA_IN(len, buf, 2))
106 88
107 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP <<
108 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), <<
109 SPI_MEM_OP_ADDR(3, addr, 2) <<
110 SPI_MEM_OP_DUMMY(ndummy, 2) <<
111 SPI_MEM_OP_DATA_IN(len, buf <<
112 <<
113 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP 89 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \
114 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), 90 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
115 SPI_MEM_OP_ADDR(2, addr, 4) 91 SPI_MEM_OP_ADDR(2, addr, 4), \
116 SPI_MEM_OP_DUMMY(ndummy, 4) 92 SPI_MEM_OP_DUMMY(ndummy, 4), \
117 SPI_MEM_OP_DATA_IN(len, buf 93 SPI_MEM_OP_DATA_IN(len, buf, 4))
118 94
119 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP <<
120 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), <<
121 SPI_MEM_OP_ADDR(3, addr, 4) <<
122 SPI_MEM_OP_DUMMY(ndummy, 4) <<
123 SPI_MEM_OP_DATA_IN(len, buf <<
124 <<
125 #define SPINAND_PROG_EXEC_OP(addr) 95 #define SPINAND_PROG_EXEC_OP(addr) \
126 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), 96 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
127 SPI_MEM_OP_ADDR(3, addr, 1) 97 SPI_MEM_OP_ADDR(3, addr, 1), \
128 SPI_MEM_OP_NO_DUMMY, 98 SPI_MEM_OP_NO_DUMMY, \
129 SPI_MEM_OP_NO_DATA) 99 SPI_MEM_OP_NO_DATA)
130 100
131 #define SPINAND_PROG_LOAD(reset, addr, buf, le 101 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \
132 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 102 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
133 SPI_MEM_OP_ADDR(2, addr, 1) 103 SPI_MEM_OP_ADDR(2, addr, 1), \
134 SPI_MEM_OP_NO_DUMMY, 104 SPI_MEM_OP_NO_DUMMY, \
135 SPI_MEM_OP_DATA_OUT(len, bu 105 SPI_MEM_OP_DATA_OUT(len, buf, 1))
136 106
137 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, 107 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \
138 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 108 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
139 SPI_MEM_OP_ADDR(2, addr, 1) 109 SPI_MEM_OP_ADDR(2, addr, 1), \
140 SPI_MEM_OP_NO_DUMMY, 110 SPI_MEM_OP_NO_DUMMY, \
141 SPI_MEM_OP_DATA_OUT(len, bu 111 SPI_MEM_OP_DATA_OUT(len, buf, 4))
142 112
143 /** 113 /**
144 * Standard SPI NAND flash commands 114 * Standard SPI NAND flash commands
145 */ 115 */
146 #define SPINAND_CMD_PROG_LOAD_X4 116 #define SPINAND_CMD_PROG_LOAD_X4 0x32
147 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 117 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
148 118
149 /* feature register */ 119 /* feature register */
150 #define REG_BLOCK_LOCK 0xa0 120 #define REG_BLOCK_LOCK 0xa0
151 #define BL_ALL_UNLOCKED 0x00 121 #define BL_ALL_UNLOCKED 0x00
152 122
153 /* configuration register */ 123 /* configuration register */
154 #define REG_CFG 0xb0 124 #define REG_CFG 0xb0
155 #define CFG_OTP_ENABLE BIT(6) 125 #define CFG_OTP_ENABLE BIT(6)
156 #define CFG_ECC_ENABLE BIT(4) 126 #define CFG_ECC_ENABLE BIT(4)
157 #define CFG_QUAD_ENABLE BIT(0) 127 #define CFG_QUAD_ENABLE BIT(0)
158 128
159 /* status register */ 129 /* status register */
160 #define REG_STATUS 0xc0 130 #define REG_STATUS 0xc0
161 #define STATUS_BUSY BIT(0) 131 #define STATUS_BUSY BIT(0)
162 #define STATUS_ERASE_FAILED BIT(2) 132 #define STATUS_ERASE_FAILED BIT(2)
163 #define STATUS_PROG_FAILED BIT(3) 133 #define STATUS_PROG_FAILED BIT(3)
164 #define STATUS_ECC_MASK GENMASK(5, 4) 134 #define STATUS_ECC_MASK GENMASK(5, 4)
165 #define STATUS_ECC_NO_BITFLIPS (0 << 4) 135 #define STATUS_ECC_NO_BITFLIPS (0 << 4)
166 #define STATUS_ECC_HAS_BITFLIPS (1 << 4) 136 #define STATUS_ECC_HAS_BITFLIPS (1 << 4)
167 #define STATUS_ECC_UNCOR_ERROR (2 << 4) 137 #define STATUS_ECC_UNCOR_ERROR (2 << 4)
168 138
169 struct spinand_op; 139 struct spinand_op;
170 struct spinand_device; 140 struct spinand_device;
171 141
172 #define SPINAND_MAX_ID_LEN 5 !! 142 #define SPINAND_MAX_ID_LEN 4
173 /* <<
174 * For erase, write and read operation, we got <<
175 * tBERS (erase) 1ms to 4ms <<
176 * tPROG 300us to 400us <<
177 * tREAD 25us to 100us <<
178 * In order to minimize latency, the min value <<
179 * initial delay, and dividing by 20 for the p <<
180 * For reset, 5us/10us/500us if the device is <<
181 * reading/programming/erasing when the RESET <<
182 * issue a RESET when the device is IDLE, 5us <<
183 * and poll delay. <<
184 */ <<
185 #define SPINAND_READ_INITIAL_DELAY_US 6 <<
186 #define SPINAND_READ_POLL_DELAY_US 5 <<
187 #define SPINAND_RESET_INITIAL_DELAY_US 5 <<
188 #define SPINAND_RESET_POLL_DELAY_US 5 <<
189 #define SPINAND_WRITE_INITIAL_DELAY_US 75 <<
190 #define SPINAND_WRITE_POLL_DELAY_US 15 <<
191 #define SPINAND_ERASE_INITIAL_DELAY_US 250 <<
192 #define SPINAND_ERASE_POLL_DELAY_US 50 <<
193 <<
194 #define SPINAND_WAITRDY_TIMEOUT_MS 400 <<
195 143
196 /** 144 /**
197 * struct spinand_id - SPI NAND id structure 145 * struct spinand_id - SPI NAND id structure
198 * @data: buffer containing the id bytes. Curr 146 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
199 * be extended if required 147 * be extended if required
200 * @len: ID length 148 * @len: ID length
>> 149 *
>> 150 * struct_spinand_id->data contains all bytes returned after a READ_ID command,
>> 151 * including dummy bytes if the chip does not emit ID bytes right after the
>> 152 * READ_ID command. The responsibility to extract real ID bytes is left to
>> 153 * struct_manufacurer_ops->detect().
201 */ 154 */
202 struct spinand_id { 155 struct spinand_id {
203 u8 data[SPINAND_MAX_ID_LEN]; 156 u8 data[SPINAND_MAX_ID_LEN];
204 int len; 157 int len;
205 }; 158 };
206 159
207 enum spinand_readid_method { <<
208 SPINAND_READID_METHOD_OPCODE, <<
209 SPINAND_READID_METHOD_OPCODE_ADDR, <<
210 SPINAND_READID_METHOD_OPCODE_DUMMY, <<
211 }; <<
212 <<
213 /** <<
214 * struct spinand_devid - SPI NAND device id s <<
215 * @id: device id of current chip <<
216 * @len: number of bytes in device id <<
217 * @method: method to read chip id <<
218 * There are 3 possible variants: <<
219 * SPINAND_READID_METHOD_OPCODE: chip <<
220 * after read_id opcode. <<
221 * SPINAND_READID_METHOD_OPCODE_ADDR: <<
222 * read_id opcode + 1-byte address. <<
223 * SPINAND_READID_METHOD_OPCODE_DUMMY <<
224 * read_id opcode + 1 dummy byte. <<
225 */ <<
226 struct spinand_devid { <<
227 const u8 *id; <<
228 const u8 len; <<
229 const enum spinand_readid_method metho <<
230 }; <<
231 <<
232 /** 160 /**
233 * struct manufacurer_ops - SPI NAND manufactu 161 * struct manufacurer_ops - SPI NAND manufacturer specific operations
>> 162 * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
>> 163 * the core calls the struct_manufacurer_ops->detect() hook of each
>> 164 * registered manufacturer until one of them return 1. Note that
>> 165 * the first thing to check in this hook is that the manufacturer ID
>> 166 * in struct_spinand_device->id matches the manufacturer whose
>> 167 * ->detect() hook has been called. Should return 1 if there's a
>> 168 * match, 0 if the manufacturer ID does not match and a negative
>> 169 * error code otherwise. When true is returned, the core assumes
>> 170 * that properties of the NAND chip (spinand->base.memorg and
>> 171 * spinand->base.eccreq) have been filled
234 * @init: initialize a SPI NAND device 172 * @init: initialize a SPI NAND device
235 * @cleanup: cleanup a SPI NAND device 173 * @cleanup: cleanup a SPI NAND device
236 * 174 *
237 * Each SPI NAND manufacturer driver should im 175 * Each SPI NAND manufacturer driver should implement this interface so that
238 * NAND chips coming from this vendor can be i !! 176 * NAND chips coming from this vendor can be detected and initialized properly.
239 */ 177 */
240 struct spinand_manufacturer_ops { 178 struct spinand_manufacturer_ops {
>> 179 int (*detect)(struct spinand_device *spinand);
241 int (*init)(struct spinand_device *spi 180 int (*init)(struct spinand_device *spinand);
242 void (*cleanup)(struct spinand_device 181 void (*cleanup)(struct spinand_device *spinand);
243 }; 182 };
244 183
245 /** 184 /**
246 * struct spinand_manufacturer - SPI NAND manu 185 * struct spinand_manufacturer - SPI NAND manufacturer instance
247 * @id: manufacturer ID 186 * @id: manufacturer ID
248 * @name: manufacturer name 187 * @name: manufacturer name
249 * @devid_len: number of bytes in device ID <<
250 * @chips: supported SPI NANDs under current m <<
251 * @nchips: number of SPI NANDs available in c <<
252 * @ops: manufacturer operations 188 * @ops: manufacturer operations
253 */ 189 */
254 struct spinand_manufacturer { 190 struct spinand_manufacturer {
255 u8 id; 191 u8 id;
256 char *name; 192 char *name;
257 const struct spinand_info *chips; <<
258 const size_t nchips; <<
259 const struct spinand_manufacturer_ops 193 const struct spinand_manufacturer_ops *ops;
260 }; 194 };
261 195
262 /* SPI NAND manufacturers */ 196 /* SPI NAND manufacturers */
263 extern const struct spinand_manufacturer allia <<
264 extern const struct spinand_manufacturer ato_s <<
265 extern const struct spinand_manufacturer esmt_ <<
266 extern const struct spinand_manufacturer fores <<
267 extern const struct spinand_manufacturer gigad 197 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
268 extern const struct spinand_manufacturer macro 198 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
269 extern const struct spinand_manufacturer micro 199 extern const struct spinand_manufacturer micron_spinand_manufacturer;
270 extern const struct spinand_manufacturer parag <<
271 extern const struct spinand_manufacturer toshi 200 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
272 extern const struct spinand_manufacturer winbo 201 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
273 extern const struct spinand_manufacturer xtx_s <<
274 202
275 /** 203 /**
276 * struct spinand_op_variants - SPI NAND opera 204 * struct spinand_op_variants - SPI NAND operation variants
277 * @ops: the list of variants for a given oper 205 * @ops: the list of variants for a given operation
278 * @nops: the number of variants 206 * @nops: the number of variants
279 * 207 *
280 * Some operations like read-from-cache/write- 208 * Some operations like read-from-cache/write-to-cache have several variants
281 * depending on the number of IO lines you use 209 * depending on the number of IO lines you use to transfer data or address
282 * cycles. This structure is a way to describe 210 * cycles. This structure is a way to describe the different variants supported
283 * by a chip and let the core pick the best on 211 * by a chip and let the core pick the best one based on the SPI mem controller
284 * capabilities. 212 * capabilities.
285 */ 213 */
286 struct spinand_op_variants { 214 struct spinand_op_variants {
287 const struct spi_mem_op *ops; 215 const struct spi_mem_op *ops;
288 unsigned int nops; 216 unsigned int nops;
289 }; 217 };
290 218
291 #define SPINAND_OP_VARIANTS(name, ...) 219 #define SPINAND_OP_VARIANTS(name, ...) \
292 const struct spinand_op_variants name 220 const struct spinand_op_variants name = { \
293 .ops = (struct spi_mem_op[]) { 221 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
294 .nops = sizeof((struct spi_mem 222 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
295 sizeof(struct spi_mem_ 223 sizeof(struct spi_mem_op), \
296 } 224 }
297 225
298 /** 226 /**
299 * spinand_ecc_info - description of the on-di 227 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
300 * chip 228 * chip
301 * @get_status: get the ECC status. Should ret 229 * @get_status: get the ECC status. Should return a positive number encoding
302 * the number of corrected bitfli 230 * the number of corrected bitflips if correction was possible or
303 * -EBADMSG if there are uncorrec 231 * -EBADMSG if there are uncorrectable errors. I can also return
304 * other negative error codes if 232 * other negative error codes if the error is not caused by
305 * uncorrectable bitflips 233 * uncorrectable bitflips
306 * @ooblayout: the OOB layout used by the on-d 234 * @ooblayout: the OOB layout used by the on-die ECC implementation
307 */ 235 */
308 struct spinand_ecc_info { 236 struct spinand_ecc_info {
309 int (*get_status)(struct spinand_devic 237 int (*get_status)(struct spinand_device *spinand, u8 status);
310 const struct mtd_ooblayout_ops *ooblay 238 const struct mtd_ooblayout_ops *ooblayout;
311 }; 239 };
312 240
313 #define SPINAND_HAS_QE_BIT BIT(0) 241 #define SPINAND_HAS_QE_BIT BIT(0)
314 #define SPINAND_HAS_CR_FEAT_BIT BIT(1) <<
315 <<
316 /** <<
317 * struct spinand_ondie_ecc_conf - private SPI <<
318 * @status: status of the last wait operation <<
319 * ->get_status() is not populated by <<
320 */ <<
321 struct spinand_ondie_ecc_conf { <<
322 u8 status; <<
323 }; <<
324 242
325 /** 243 /**
326 * struct spinand_info - Structure used to des 244 * struct spinand_info - Structure used to describe SPI NAND chips
327 * @model: model name 245 * @model: model name
328 * @devid: device ID 246 * @devid: device ID
329 * @flags: OR-ing of the SPINAND_XXX flags 247 * @flags: OR-ing of the SPINAND_XXX flags
330 * @memorg: memory organization 248 * @memorg: memory organization
331 * @eccreq: ECC requirements 249 * @eccreq: ECC requirements
332 * @eccinfo: on-die ECC info 250 * @eccinfo: on-die ECC info
333 * @op_variants: operations variants 251 * @op_variants: operations variants
334 * @op_variants.read_cache: variants of the re 252 * @op_variants.read_cache: variants of the read-cache operation
335 * @op_variants.write_cache: variants of the w 253 * @op_variants.write_cache: variants of the write-cache operation
336 * @op_variants.update_cache: variants of the 254 * @op_variants.update_cache: variants of the update-cache operation
337 * @select_target: function used to select a t 255 * @select_target: function used to select a target/die. Required only for
338 * multi-die chips 256 * multi-die chips
339 * 257 *
340 * Each SPI NAND manufacturer driver should ha 258 * Each SPI NAND manufacturer driver should have a spinand_info table
341 * describing all the chips supported by the d 259 * describing all the chips supported by the driver.
342 */ 260 */
343 struct spinand_info { 261 struct spinand_info {
344 const char *model; 262 const char *model;
345 struct spinand_devid devid; !! 263 u8 devid;
346 u32 flags; 264 u32 flags;
347 struct nand_memory_organization memorg 265 struct nand_memory_organization memorg;
348 struct nand_ecc_props eccreq; !! 266 struct nand_ecc_req eccreq;
349 struct spinand_ecc_info eccinfo; 267 struct spinand_ecc_info eccinfo;
350 struct { 268 struct {
351 const struct spinand_op_varian 269 const struct spinand_op_variants *read_cache;
352 const struct spinand_op_varian 270 const struct spinand_op_variants *write_cache;
353 const struct spinand_op_varian 271 const struct spinand_op_variants *update_cache;
354 } op_variants; 272 } op_variants;
355 int (*select_target)(struct spinand_de 273 int (*select_target)(struct spinand_device *spinand,
356 unsigned int targ 274 unsigned int target);
357 }; 275 };
358 276
359 #define SPINAND_ID(__method, ...) <<
360 { <<
361 .id = (const u8[]){ __VA_ARGS_ <<
362 .len = sizeof((u8[]){ __VA_ARG <<
363 .method = __method, <<
364 } <<
365 <<
366 #define SPINAND_INFO_OP_VARIANTS(__read, __wri 277 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
367 { 278 { \
368 .read_cache = __read, 279 .read_cache = __read, \
369 .write_cache = __write, 280 .write_cache = __write, \
370 .update_cache = __update, 281 .update_cache = __update, \
371 } 282 }
372 283
373 #define SPINAND_ECCINFO(__ooblayout, __get_sta 284 #define SPINAND_ECCINFO(__ooblayout, __get_status) \
374 .eccinfo = { 285 .eccinfo = { \
375 .ooblayout = __ooblayout, 286 .ooblayout = __ooblayout, \
376 .get_status = __get_status, 287 .get_status = __get_status, \
377 } 288 }
378 289
379 #define SPINAND_SELECT_TARGET(__func) 290 #define SPINAND_SELECT_TARGET(__func) \
380 .select_target = __func, 291 .select_target = __func,
381 292
382 #define SPINAND_INFO(__model, __id, __memorg, 293 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
383 __flags, ...) 294 __flags, ...) \
384 { 295 { \
385 .model = __model, 296 .model = __model, \
386 .devid = __id, 297 .devid = __id, \
387 .memorg = __memorg, 298 .memorg = __memorg, \
388 .eccreq = __eccreq, 299 .eccreq = __eccreq, \
389 .op_variants = __op_variants, 300 .op_variants = __op_variants, \
390 .flags = __flags, 301 .flags = __flags, \
391 __VA_ARGS__ 302 __VA_ARGS__ \
392 } 303 }
393 304
394 struct spinand_dirmap { 305 struct spinand_dirmap {
395 struct spi_mem_dirmap_desc *wdesc; 306 struct spi_mem_dirmap_desc *wdesc;
396 struct spi_mem_dirmap_desc *rdesc; 307 struct spi_mem_dirmap_desc *rdesc;
397 struct spi_mem_dirmap_desc *wdesc_ecc; <<
398 struct spi_mem_dirmap_desc *rdesc_ecc; <<
399 }; 308 };
400 309
401 /** 310 /**
402 * struct spinand_device - SPI NAND device ins 311 * struct spinand_device - SPI NAND device instance
403 * @base: NAND device instance 312 * @base: NAND device instance
404 * @spimem: pointer to the SPI mem object 313 * @spimem: pointer to the SPI mem object
405 * @lock: lock used to serialize accesses to t 314 * @lock: lock used to serialize accesses to the NAND
406 * @id: NAND ID as returned by READ_ID 315 * @id: NAND ID as returned by READ_ID
407 * @flags: NAND flags 316 * @flags: NAND flags
408 * @op_templates: various SPI mem op templates 317 * @op_templates: various SPI mem op templates
409 * @op_templates.read_cache: read cache op tem 318 * @op_templates.read_cache: read cache op template
410 * @op_templates.write_cache: write cache op t 319 * @op_templates.write_cache: write cache op template
411 * @op_templates.update_cache: update cache op 320 * @op_templates.update_cache: update cache op template
412 * @select_target: select a specific target/di 321 * @select_target: select a specific target/die. Usually called before sending
413 * a command addressing a page 322 * a command addressing a page or an eraseblock embedded in
414 * this die. Only required if 323 * this die. Only required if your chip exposes several dies
415 * @cur_target: currently selected target/die 324 * @cur_target: currently selected target/die
416 * @eccinfo: on-die ECC information 325 * @eccinfo: on-die ECC information
417 * @cfg_cache: config register cache. One entr 326 * @cfg_cache: config register cache. One entry per die
418 * @databuf: bounce buffer for data 327 * @databuf: bounce buffer for data
419 * @oobbuf: bounce buffer for OOB data 328 * @oobbuf: bounce buffer for OOB data
420 * @scratchbuf: buffer used for everything but 329 * @scratchbuf: buffer used for everything but page accesses. This is needed
421 * because the spi-mem interface 330 * because the spi-mem interface explicitly requests that buffers
422 * passed in spi_mem_op be DMA-ab 331 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
423 * the stack 332 * the stack
424 * @manufacturer: SPI NAND manufacturer inform 333 * @manufacturer: SPI NAND manufacturer information
425 * @priv: manufacturer private data 334 * @priv: manufacturer private data
426 */ 335 */
427 struct spinand_device { 336 struct spinand_device {
428 struct nand_device base; 337 struct nand_device base;
429 struct spi_mem *spimem; 338 struct spi_mem *spimem;
430 struct mutex lock; 339 struct mutex lock;
431 struct spinand_id id; 340 struct spinand_id id;
432 u32 flags; 341 u32 flags;
433 342
434 struct { 343 struct {
435 const struct spi_mem_op *read_ 344 const struct spi_mem_op *read_cache;
436 const struct spi_mem_op *write 345 const struct spi_mem_op *write_cache;
437 const struct spi_mem_op *updat 346 const struct spi_mem_op *update_cache;
438 } op_templates; 347 } op_templates;
439 348
440 struct spinand_dirmap *dirmaps; 349 struct spinand_dirmap *dirmaps;
441 350
442 int (*select_target)(struct spinand_de 351 int (*select_target)(struct spinand_device *spinand,
443 unsigned int targ 352 unsigned int target);
444 unsigned int cur_target; 353 unsigned int cur_target;
445 354
446 struct spinand_ecc_info eccinfo; 355 struct spinand_ecc_info eccinfo;
447 356
448 u8 *cfg_cache; 357 u8 *cfg_cache;
449 u8 *databuf; 358 u8 *databuf;
450 u8 *oobbuf; 359 u8 *oobbuf;
451 u8 *scratchbuf; 360 u8 *scratchbuf;
452 const struct spinand_manufacturer *man 361 const struct spinand_manufacturer *manufacturer;
453 void *priv; 362 void *priv;
454 }; 363 };
455 364
456 /** 365 /**
457 * mtd_to_spinand() - Get the SPI NAND device 366 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
458 * @mtd: MTD instance 367 * @mtd: MTD instance
459 * 368 *
460 * Return: the SPI NAND device attached to @mt 369 * Return: the SPI NAND device attached to @mtd.
461 */ 370 */
462 static inline struct spinand_device *mtd_to_sp 371 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
463 { 372 {
464 return container_of(mtd_to_nanddev(mtd 373 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
465 } 374 }
466 375
467 /** 376 /**
468 * spinand_to_mtd() - Get the MTD device embed 377 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
469 * @spinand: SPI NAND device 378 * @spinand: SPI NAND device
470 * 379 *
471 * Return: the MTD device embedded in @spinand 380 * Return: the MTD device embedded in @spinand.
472 */ 381 */
473 static inline struct mtd_info *spinand_to_mtd( 382 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
474 { 383 {
475 return nanddev_to_mtd(&spinand->base); 384 return nanddev_to_mtd(&spinand->base);
476 } 385 }
477 386
478 /** 387 /**
479 * nand_to_spinand() - Get the SPI NAND device 388 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
480 * @nand: NAND object 389 * @nand: NAND object
481 * 390 *
482 * Return: the SPI NAND device embedding @nand 391 * Return: the SPI NAND device embedding @nand.
483 */ 392 */
484 static inline struct spinand_device *nand_to_s 393 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
485 { 394 {
486 return container_of(nand, struct spina 395 return container_of(nand, struct spinand_device, base);
487 } 396 }
488 397
489 /** 398 /**
490 * spinand_to_nand() - Get the NAND device emb 399 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
491 * @spinand: SPI NAND device 400 * @spinand: SPI NAND device
492 * 401 *
493 * Return: the NAND device embedded in @spinan 402 * Return: the NAND device embedded in @spinand.
494 */ 403 */
495 static inline struct nand_device * 404 static inline struct nand_device *
496 spinand_to_nand(struct spinand_device *spinand 405 spinand_to_nand(struct spinand_device *spinand)
497 { 406 {
498 return &spinand->base; 407 return &spinand->base;
499 } 408 }
500 409
501 /** 410 /**
502 * spinand_set_of_node - Attach a DT node to a 411 * spinand_set_of_node - Attach a DT node to a SPI NAND device
503 * @spinand: SPI NAND device 412 * @spinand: SPI NAND device
504 * @np: DT node 413 * @np: DT node
505 * 414 *
506 * Attach a DT node to a SPI NAND device. 415 * Attach a DT node to a SPI NAND device.
507 */ 416 */
508 static inline void spinand_set_of_node(struct 417 static inline void spinand_set_of_node(struct spinand_device *spinand,
509 struct 418 struct device_node *np)
510 { 419 {
511 nanddev_set_of_node(&spinand->base, np 420 nanddev_set_of_node(&spinand->base, np);
512 } 421 }
513 422
514 int spinand_match_and_init(struct spinand_devi !! 423 int spinand_match_and_init(struct spinand_device *dev,
515 const struct spinan 424 const struct spinand_info *table,
516 unsigned int table_ !! 425 unsigned int table_size, u8 devid);
517 enum spinand_readid <<
518 426
519 int spinand_upd_cfg(struct spinand_device *spi 427 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
520 int spinand_select_target(struct spinand_devic 428 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
521 429
522 #endif /* __LINUX_MTD_SPINAND_H */ 430 #endif /* __LINUX_MTD_SPINAND_H */
523 431
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