1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Copyright (c) 2020 Synopsys, Inc. and/or it
4 * Synopsys DesignWare XPCS helpers
5 */
6
7 #ifndef __LINUX_PCS_XPCS_H
8 #define __LINUX_PCS_XPCS_H
9
10 #include <linux/clk.h>
11 #include <linux/fwnode.h>
12 #include <linux/mdio.h>
13 #include <linux/phy.h>
14 #include <linux/phylink.h>
15 #include <linux/types.h>
16
17 /* AN mode */
18 #define DW_AN_C73 1
19 #define DW_AN_C37_SGMII 2
20 #define DW_2500BASEX 3
21 #define DW_AN_C37_1000BASEX 4
22 #define DW_10GBASER 5
23
24 struct dw_xpcs_desc;
25
26 enum dw_xpcs_pcs_id {
27 DW_XPCS_ID_NATIVE = 0,
28 NXP_SJA1105_XPCS_ID = 0x00000010,
29 NXP_SJA1110_XPCS_ID = 0x00000020,
30 DW_XPCS_ID = 0x7996ced0,
31 DW_XPCS_ID_MASK = 0xffffffff,
32 };
33
34 enum dw_xpcs_pma_id {
35 DW_XPCS_PMA_ID_NATIVE = 0,
36 DW_XPCS_PMA_GEN1_3G_ID,
37 DW_XPCS_PMA_GEN2_3G_ID,
38 DW_XPCS_PMA_GEN2_6G_ID,
39 DW_XPCS_PMA_GEN4_3G_ID,
40 DW_XPCS_PMA_GEN4_6G_ID,
41 DW_XPCS_PMA_GEN5_10G_ID,
42 DW_XPCS_PMA_GEN5_12G_ID,
43 WX_TXGBE_XPCS_PMA_10G_ID = 0x0018fc80,
44 };
45
46 struct dw_xpcs_info {
47 u32 pcs;
48 u32 pma;
49 };
50
51 enum dw_xpcs_clock {
52 DW_XPCS_CORE_CLK,
53 DW_XPCS_PAD_CLK,
54 DW_XPCS_NUM_CLKS,
55 };
56
57 struct dw_xpcs {
58 struct dw_xpcs_info info;
59 const struct dw_xpcs_desc *desc;
60 struct mdio_device *mdiodev;
61 struct clk_bulk_data clks[DW_XPCS_NUM_
62 struct phylink_pcs pcs;
63 phy_interface_t interface;
64 };
65
66 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy
67 void xpcs_link_up(struct phylink_pcs *pcs, uns
68 phy_interface_t interface, i
69 int xpcs_do_config(struct dw_xpcs *xpcs, phy_i
70 const unsigned long *advert
71 void xpcs_get_interfaces(struct dw_xpcs *xpcs,
72 int xpcs_config_eee(struct dw_xpcs *xpcs, int
73 int enable);
74 struct dw_xpcs *xpcs_create_mdiodev(struct mii
75 phy_interf
76 struct dw_xpcs *xpcs_create_fwnode(struct fwno
77 phy_interfa
78 void xpcs_destroy(struct dw_xpcs *xpcs);
79
80 #endif /* __LINUX_PCS_XPCS_H */
81
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