1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright (C) 2019 Cadence Design Systems I 3 * Copyright (C) 2019 Cadence Design Systems Inc.
4 */ 4 */
5 5
6 #ifndef __PHY_DP_H_ 6 #ifndef __PHY_DP_H_
7 #define __PHY_DP_H_ 7 #define __PHY_DP_H_
8 8
9 #include <linux/types.h> 9 #include <linux/types.h>
10 10
11 #define PHY_SUBMODE_DP 0 <<
12 #define PHY_SUBMODE_EDP 1 <<
13 <<
14 /** 11 /**
15 * struct phy_configure_opts_dp - DisplayPort 12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
16 * 13 *
17 * This structure is used to represent the con 14 * This structure is used to represent the configuration state of a
18 * DisplayPort phy. 15 * DisplayPort phy.
19 */ 16 */
20 struct phy_configure_opts_dp { 17 struct phy_configure_opts_dp {
21 /** 18 /**
22 * @link_rate: 19 * @link_rate:
23 * 20 *
24 * Link Rate, in Mb/s, of the main lin 21 * Link Rate, in Mb/s, of the main link.
25 * 22 *
26 * Allowed values: 1620, 2160, 2430, 2 23 * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
27 */ 24 */
28 unsigned int link_rate; 25 unsigned int link_rate;
29 26
30 /** 27 /**
31 * @lanes: 28 * @lanes:
32 * 29 *
33 * Number of active, consecutive, data 30 * Number of active, consecutive, data lanes, starting from
34 * lane 0, used for the transmissions 31 * lane 0, used for the transmissions on main link.
35 * 32 *
36 * Allowed values: 1, 2, 4 33 * Allowed values: 1, 2, 4
37 */ 34 */
38 unsigned int lanes; 35 unsigned int lanes;
39 36
40 /** 37 /**
41 * @voltage: 38 * @voltage:
42 * 39 *
43 * Voltage swing levels, as specified 40 * Voltage swing levels, as specified by DisplayPort specification,
44 * to be used by particular lanes. One 41 * to be used by particular lanes. One value per lane.
45 * voltage[0] is for lane 0, voltage[1 42 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
46 * 43 *
47 * Maximum value: 3 44 * Maximum value: 3
48 */ 45 */
49 unsigned int voltage[4]; 46 unsigned int voltage[4];
50 47
51 /** 48 /**
52 * @pre: 49 * @pre:
53 * 50 *
54 * Pre-emphasis levels, as specified b 51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
55 * used by particular lanes. One value 52 * used by particular lanes. One value per lane.
56 * 53 *
57 * Maximum value: 3 54 * Maximum value: 3
58 */ 55 */
59 unsigned int pre[4]; 56 unsigned int pre[4];
60 57
61 /** 58 /**
62 * @ssc: 59 * @ssc:
63 * 60 *
64 * Flag indicating, whether or not to 61 * Flag indicating, whether or not to enable spread-spectrum clocking.
65 * 62 *
66 */ 63 */
67 u8 ssc : 1; 64 u8 ssc : 1;
68 65
69 /** 66 /**
70 * @set_rate: 67 * @set_rate:
71 * 68 *
72 * Flag indicating, whether or not rec 69 * Flag indicating, whether or not reconfigure link rate and SSC to
73 * requested values. 70 * requested values.
74 * 71 *
75 */ 72 */
76 u8 set_rate : 1; 73 u8 set_rate : 1;
77 74
78 /** 75 /**
79 * @set_lanes: 76 * @set_lanes:
80 * 77 *
81 * Flag indicating, whether or not rec 78 * Flag indicating, whether or not reconfigure lane count to
82 * requested value. 79 * requested value.
83 * 80 *
84 */ 81 */
85 u8 set_lanes : 1; 82 u8 set_lanes : 1;
86 83
87 /** 84 /**
88 * @set_voltages: 85 * @set_voltages:
89 * 86 *
90 * Flag indicating, whether or not rec 87 * Flag indicating, whether or not reconfigure voltage swing
91 * and pre-emphasis to requested value 88 * and pre-emphasis to requested values. Only lanes specified
92 * by "lanes" parameter will be affect 89 * by "lanes" parameter will be affected.
93 * 90 *
94 */ 91 */
95 u8 set_voltages : 1; 92 u8 set_voltages : 1;
96 }; 93 };
97 94
98 #endif /* __PHY_DP_H_ */ 95 #endif /* __PHY_DP_H_ */
99 96
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