1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright (C) 2019 Cadence Design Systems I 3 * Copyright (C) 2019 Cadence Design Systems Inc.
4 */ 4 */
5 5
6 #ifndef __PHY_DP_H_ 6 #ifndef __PHY_DP_H_
7 #define __PHY_DP_H_ 7 #define __PHY_DP_H_
8 8
9 #include <linux/types.h> 9 #include <linux/types.h>
10 10
11 #define PHY_SUBMODE_DP 0 11 #define PHY_SUBMODE_DP 0
12 #define PHY_SUBMODE_EDP 1 12 #define PHY_SUBMODE_EDP 1
13 13
14 /** 14 /**
15 * struct phy_configure_opts_dp - DisplayPort 15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
16 * 16 *
17 * This structure is used to represent the con 17 * This structure is used to represent the configuration state of a
18 * DisplayPort phy. 18 * DisplayPort phy.
19 */ 19 */
20 struct phy_configure_opts_dp { 20 struct phy_configure_opts_dp {
21 /** 21 /**
22 * @link_rate: 22 * @link_rate:
23 * 23 *
24 * Link Rate, in Mb/s, of the main lin 24 * Link Rate, in Mb/s, of the main link.
25 * 25 *
26 * Allowed values: 1620, 2160, 2430, 2 26 * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
27 */ 27 */
28 unsigned int link_rate; 28 unsigned int link_rate;
29 29
30 /** 30 /**
31 * @lanes: 31 * @lanes:
32 * 32 *
33 * Number of active, consecutive, data 33 * Number of active, consecutive, data lanes, starting from
34 * lane 0, used for the transmissions 34 * lane 0, used for the transmissions on main link.
35 * 35 *
36 * Allowed values: 1, 2, 4 36 * Allowed values: 1, 2, 4
37 */ 37 */
38 unsigned int lanes; 38 unsigned int lanes;
39 39
40 /** 40 /**
41 * @voltage: 41 * @voltage:
42 * 42 *
43 * Voltage swing levels, as specified 43 * Voltage swing levels, as specified by DisplayPort specification,
44 * to be used by particular lanes. One 44 * to be used by particular lanes. One value per lane.
45 * voltage[0] is for lane 0, voltage[1 45 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
46 * 46 *
47 * Maximum value: 3 47 * Maximum value: 3
48 */ 48 */
49 unsigned int voltage[4]; 49 unsigned int voltage[4];
50 50
51 /** 51 /**
52 * @pre: 52 * @pre:
53 * 53 *
54 * Pre-emphasis levels, as specified b 54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
55 * used by particular lanes. One value 55 * used by particular lanes. One value per lane.
56 * 56 *
57 * Maximum value: 3 57 * Maximum value: 3
58 */ 58 */
59 unsigned int pre[4]; 59 unsigned int pre[4];
60 60
61 /** 61 /**
62 * @ssc: 62 * @ssc:
63 * 63 *
64 * Flag indicating, whether or not to 64 * Flag indicating, whether or not to enable spread-spectrum clocking.
65 * 65 *
66 */ 66 */
67 u8 ssc : 1; 67 u8 ssc : 1;
68 68
69 /** 69 /**
70 * @set_rate: 70 * @set_rate:
71 * 71 *
72 * Flag indicating, whether or not rec 72 * Flag indicating, whether or not reconfigure link rate and SSC to
73 * requested values. 73 * requested values.
74 * 74 *
75 */ 75 */
76 u8 set_rate : 1; 76 u8 set_rate : 1;
77 77
78 /** 78 /**
79 * @set_lanes: 79 * @set_lanes:
80 * 80 *
81 * Flag indicating, whether or not rec 81 * Flag indicating, whether or not reconfigure lane count to
82 * requested value. 82 * requested value.
83 * 83 *
84 */ 84 */
85 u8 set_lanes : 1; 85 u8 set_lanes : 1;
86 86
87 /** 87 /**
88 * @set_voltages: 88 * @set_voltages:
89 * 89 *
90 * Flag indicating, whether or not rec 90 * Flag indicating, whether or not reconfigure voltage swing
91 * and pre-emphasis to requested value 91 * and pre-emphasis to requested values. Only lanes specified
92 * by "lanes" parameter will be affect 92 * by "lanes" parameter will be affected.
93 * 93 *
94 */ 94 */
95 u8 set_voltages : 1; 95 u8 set_voltages : 1;
96 }; 96 };
97 97
98 #endif /* __PHY_DP_H_ */ 98 #endif /* __PHY_DP_H_ */
99 99
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