1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Copyright 2020,2022 NXP
4 */
5
6 #ifndef __PHY_LVDS_H_
7 #define __PHY_LVDS_H_
8
9 /**
10 * struct phy_configure_opts_lvds - LVDS confi
11 * @bits_per_lane_and_dclk_cycle: Number
12 * clock
13 * @differential_clk_rate: Clock
14 * differ
15 * @lanes: Number
16 * data l
17 * used f
18 * @is_slave: Boolea
19 * which
20 * phy to
21 * otherw
22 *
23 * This structure is used to represent the con
24 */
25 struct phy_configure_opts_lvds {
26 unsigned int bits_per_lane_and_dclk
27 unsigned long differential_clk_rate;
28 unsigned int lanes;
29 bool is_slave;
30 };
31
32 #endif /* __PHY_LVDS_H_ */
33
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