1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * usb-omap.h - Platform data for the various 3 * usb-omap.h - Platform data for the various OMAP USB IPs
4 * 4 *
5 * Copyright (C) 2012 Texas Instruments Incorp 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com
6 */ 6 */
7 7
8 #define OMAP3_HS_USB_PORTS 3 8 #define OMAP3_HS_USB_PORTS 3
9 9
10 enum usbhs_omap_port_mode { 10 enum usbhs_omap_port_mode {
11 OMAP_USBHS_PORT_MODE_UNUSED, 11 OMAP_USBHS_PORT_MODE_UNUSED,
12 OMAP_EHCI_PORT_MODE_PHY, 12 OMAP_EHCI_PORT_MODE_PHY,
13 OMAP_EHCI_PORT_MODE_TLL, 13 OMAP_EHCI_PORT_MODE_TLL,
14 OMAP_EHCI_PORT_MODE_HSIC, 14 OMAP_EHCI_PORT_MODE_HSIC,
15 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0, 15 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
16 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM, 16 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
17 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0, 17 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
18 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM, 18 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
19 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0, 19 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
20 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM, 20 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
21 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0, 21 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
22 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM, 22 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
23 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0, 23 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
24 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM 24 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
25 }; 25 };
26 26
27 struct usbtll_omap_platform_data { 27 struct usbtll_omap_platform_data {
28 enum usbhs_omap_port_mode 28 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
29 }; 29 };
30 30
31 struct ehci_hcd_omap_platform_data { 31 struct ehci_hcd_omap_platform_data {
32 enum usbhs_omap_port_mode port_m 32 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
33 int reset_ 33 int reset_gpio_port[OMAP3_HS_USB_PORTS];
34 struct regulator *regul 34 struct regulator *regulator[OMAP3_HS_USB_PORTS];
35 unsigned phy_re 35 unsigned phy_reset:1;
36 }; 36 };
37 37
38 struct ohci_hcd_omap_platform_data { 38 struct ohci_hcd_omap_platform_data {
39 enum usbhs_omap_port_mode port_m 39 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
40 unsigned es2_co 40 unsigned es2_compatibility:1;
41 }; 41 };
42 42
43 struct usbhs_omap_platform_data { 43 struct usbhs_omap_platform_data {
44 int nports 44 int nports;
45 enum usbhs_omap_port_mode port_m 45 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
46 int reset_ 46 int reset_gpio_port[OMAP3_HS_USB_PORTS];
47 struct regulator *regul 47 struct regulator *regulator[OMAP3_HS_USB_PORTS];
48 48
49 struct ehci_hcd_omap_platform_data 49 struct ehci_hcd_omap_platform_data *ehci_data;
50 struct ohci_hcd_omap_platform_data 50 struct ohci_hcd_omap_platform_data *ohci_data;
51 51
52 /* OMAP3 <= ES2.1 have a single ulpi b 52 /* OMAP3 <= ES2.1 have a single ulpi bypass control bit */
53 unsigned single_ulpi_bypass:1; 53 unsigned single_ulpi_bypass:1;
54 unsigned es2_compatibility:1; 54 unsigned es2_compatibility:1;
55 unsigned phy_reset:1; 55 unsigned phy_reset:1;
56 }; 56 };
57 57
58 /*-------------------------------------------- 58 /*-------------------------------------------------------------------------*/
59 59
60 struct omap_musb_board_data { 60 struct omap_musb_board_data {
61 u8 interface_type; 61 u8 interface_type;
62 u8 mode; 62 u8 mode;
63 u16 power; 63 u16 power;
64 unsigned extvbus:1; 64 unsigned extvbus:1;
65 void (*set_phy_power)(u8 on); 65 void (*set_phy_power)(u8 on);
66 void (*clear_irq)(void); 66 void (*clear_irq)(void);
67 void (*set_mode)(u8 mode); 67 void (*set_mode)(u8 mode);
68 void (*reset)(void); 68 void (*reset)(void);
69 }; 69 };
70 70
71 enum musb_interface { 71 enum musb_interface {
72 MUSB_INTERFACE_ULPI, 72 MUSB_INTERFACE_ULPI,
73 MUSB_INTERFACE_UTMI 73 MUSB_INTERFACE_UTMI
74 }; 74 };
75 75
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