1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 // Copyright (c) 2022 Pengutronix, Oleksij Rem 3 // Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
4 */ 4 */
5 #ifndef _LINUX_PSE_CONTROLLER_H 5 #ifndef _LINUX_PSE_CONTROLLER_H
6 #define _LINUX_PSE_CONTROLLER_H 6 #define _LINUX_PSE_CONTROLLER_H
7 7
8 #include <linux/ethtool.h> 8 #include <linux/ethtool.h>
9 #include <linux/list.h> 9 #include <linux/list.h>
10 #include <uapi/linux/ethtool.h> 10 #include <uapi/linux/ethtool.h>
11 11
12 /* Maximum current in uA according to IEEE 802 12 /* Maximum current in uA according to IEEE 802.3-2022 Table 145-1 */
13 #define MAX_PI_CURRENT 1920000 13 #define MAX_PI_CURRENT 1920000
14 14
15 struct phy_device; 15 struct phy_device;
16 struct pse_controller_dev; 16 struct pse_controller_dev;
17 17
18 /** 18 /**
19 * struct pse_control_config - PSE control/cha 19 * struct pse_control_config - PSE control/channel configuration.
20 * 20 *
21 * @podl_admin_control: set PoDL PSE admin con 21 * @podl_admin_control: set PoDL PSE admin control as described in
22 * IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEA 22 * IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEAdminControl
23 * @c33_admin_control: set PSE admin control a 23 * @c33_admin_control: set PSE admin control as described in
24 * IEEE 802.3-2022 30.9.1.2.1 acPSEAdminC 24 * IEEE 802.3-2022 30.9.1.2.1 acPSEAdminControl
25 */ 25 */
26 struct pse_control_config { 26 struct pse_control_config {
27 enum ethtool_podl_pse_admin_state podl 27 enum ethtool_podl_pse_admin_state podl_admin_control;
28 enum ethtool_c33_pse_admin_state c33_a 28 enum ethtool_c33_pse_admin_state c33_admin_control;
29 }; 29 };
30 30
31 /** 31 /**
32 * struct pse_control_status - PSE control/cha 32 * struct pse_control_status - PSE control/channel status.
33 * 33 *
34 * @podl_admin_state: operational state of the 34 * @podl_admin_state: operational state of the PoDL PSE
35 * functions. IEEE 802.3-2018 30.15.1.1.2 35 * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
36 * @podl_pw_status: power detection status of 36 * @podl_pw_status: power detection status of the PoDL PSE.
37 * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPo 37 * IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus:
38 * @c33_admin_state: operational state of the 38 * @c33_admin_state: operational state of the PSE
39 * functions. IEEE 802.3-2022 30.9.1.1.2 39 * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
40 * @c33_pw_status: power detection status of t 40 * @c33_pw_status: power detection status of the PSE.
41 * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDe 41 * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus:
42 * @c33_pw_class: detected class of a powered 42 * @c33_pw_class: detected class of a powered PD
43 * IEEE 802.3-2022 30.9.1.1.8 aPSEPowerCl 43 * IEEE 802.3-2022 30.9.1.1.8 aPSEPowerClassification
44 * @c33_actual_pw: power currently delivered b 44 * @c33_actual_pw: power currently delivered by the PSE in mW
45 * IEEE 802.3-2022 30.9.1.1.23 aPSEActual 45 * IEEE 802.3-2022 30.9.1.1.23 aPSEActualPower
46 * @c33_ext_state_info: extended state informa 46 * @c33_ext_state_info: extended state information of the PSE
47 * @c33_avail_pw_limit: available power limit 47 * @c33_avail_pw_limit: available power limit of the PSE in mW
48 * IEEE 802.3-2022 145.2.5.4 pse_avail_pw 48 * IEEE 802.3-2022 145.2.5.4 pse_avail_pwr
49 * @c33_pw_limit_ranges: supported power limit 49 * @c33_pw_limit_ranges: supported power limit configuration range. The driver
50 * is in charge of the memory allocation. 50 * is in charge of the memory allocation.
51 * @c33_pw_limit_nb_ranges: number of supporte 51 * @c33_pw_limit_nb_ranges: number of supported power limit configuration
52 * ranges 52 * ranges
53 */ 53 */
54 struct pse_control_status { 54 struct pse_control_status {
55 enum ethtool_podl_pse_admin_state podl 55 enum ethtool_podl_pse_admin_state podl_admin_state;
56 enum ethtool_podl_pse_pw_d_status podl 56 enum ethtool_podl_pse_pw_d_status podl_pw_status;
57 enum ethtool_c33_pse_admin_state c33_a 57 enum ethtool_c33_pse_admin_state c33_admin_state;
58 enum ethtool_c33_pse_pw_d_status c33_p 58 enum ethtool_c33_pse_pw_d_status c33_pw_status;
59 u32 c33_pw_class; 59 u32 c33_pw_class;
60 u32 c33_actual_pw; 60 u32 c33_actual_pw;
61 struct ethtool_c33_pse_ext_state_info 61 struct ethtool_c33_pse_ext_state_info c33_ext_state_info;
62 u32 c33_avail_pw_limit; 62 u32 c33_avail_pw_limit;
63 struct ethtool_c33_pse_pw_limit_range 63 struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
64 u32 c33_pw_limit_nb_ranges; 64 u32 c33_pw_limit_nb_ranges;
65 }; 65 };
66 66
67 /** 67 /**
68 * struct pse_controller_ops - PSE controller 68 * struct pse_controller_ops - PSE controller driver callbacks
69 * 69 *
70 * @ethtool_get_status: get PSE control status 70 * @ethtool_get_status: get PSE control status for ethtool interface
71 * @setup_pi_matrix: setup PI matrix of the PS 71 * @setup_pi_matrix: setup PI matrix of the PSE controller
72 * @pi_is_enabled: Return 1 if the PSE PI is e 72 * @pi_is_enabled: Return 1 if the PSE PI is enabled, 0 if not.
73 * May also return negative er 73 * May also return negative errno.
74 * @pi_enable: Configure the PSE PI as enabled 74 * @pi_enable: Configure the PSE PI as enabled.
75 * @pi_disable: Configure the PSE PI as disabl 75 * @pi_disable: Configure the PSE PI as disabled.
76 * @pi_get_voltage: Return voltage similarly t 76 * @pi_get_voltage: Return voltage similarly to get_voltage regulator
77 * callback. 77 * callback.
78 * @pi_get_current_limit: Get the configured c 78 * @pi_get_current_limit: Get the configured current limit similarly to
79 * get_current_limit re 79 * get_current_limit regulator callback.
80 * @pi_set_current_limit: Configure the curren 80 * @pi_set_current_limit: Configure the current limit similarly to
81 * set_current_limit re 81 * set_current_limit regulator callback.
82 * Should not return an 82 * Should not return an error in case of MAX_PI_CURRENT
83 * current value set. 83 * current value set.
84 */ 84 */
85 struct pse_controller_ops { 85 struct pse_controller_ops {
86 int (*ethtool_get_status)(struct pse_c 86 int (*ethtool_get_status)(struct pse_controller_dev *pcdev,
87 unsigned long id, struct netli 87 unsigned long id, struct netlink_ext_ack *extack,
88 struct pse_control_status *sta 88 struct pse_control_status *status);
89 int (*setup_pi_matrix)(struct pse_cont 89 int (*setup_pi_matrix)(struct pse_controller_dev *pcdev);
90 int (*pi_is_enabled)(struct pse_contro 90 int (*pi_is_enabled)(struct pse_controller_dev *pcdev, int id);
91 int (*pi_enable)(struct pse_controller 91 int (*pi_enable)(struct pse_controller_dev *pcdev, int id);
92 int (*pi_disable)(struct pse_controlle 92 int (*pi_disable)(struct pse_controller_dev *pcdev, int id);
93 int (*pi_get_voltage)(struct pse_contr 93 int (*pi_get_voltage)(struct pse_controller_dev *pcdev, int id);
94 int (*pi_get_current_limit)(struct pse 94 int (*pi_get_current_limit)(struct pse_controller_dev *pcdev,
95 int id); 95 int id);
96 int (*pi_set_current_limit)(struct pse 96 int (*pi_set_current_limit)(struct pse_controller_dev *pcdev,
97 int id, in 97 int id, int max_uA);
98 }; 98 };
99 99
100 struct module; 100 struct module;
101 struct device_node; 101 struct device_node;
102 struct of_phandle_args; 102 struct of_phandle_args;
103 struct pse_control; 103 struct pse_control;
104 104
105 /* PSE PI pairset pinout can either be Alterna 105 /* PSE PI pairset pinout can either be Alternative A or Alternative B */
106 enum pse_pi_pairset_pinout { 106 enum pse_pi_pairset_pinout {
107 ALTERNATIVE_A, 107 ALTERNATIVE_A,
108 ALTERNATIVE_B, 108 ALTERNATIVE_B,
109 }; 109 };
110 110
111 /** 111 /**
112 * struct pse_pi_pairset - PSE PI pairset enti 112 * struct pse_pi_pairset - PSE PI pairset entity describing the pinout
113 * alternative ant its 113 * alternative ant its phandle
114 * 114 *
115 * @pinout: description of the pinout alternat 115 * @pinout: description of the pinout alternative
116 * @np: device node pointer describing the pai 116 * @np: device node pointer describing the pairset phandle
117 */ 117 */
118 struct pse_pi_pairset { 118 struct pse_pi_pairset {
119 enum pse_pi_pairset_pinout pinout; 119 enum pse_pi_pairset_pinout pinout;
120 struct device_node *np; 120 struct device_node *np;
121 }; 121 };
122 122
123 /** 123 /**
124 * struct pse_pi - PSE PI (Power Interface) en 124 * struct pse_pi - PSE PI (Power Interface) entity as described in
125 * IEEE 802.3-2022 145.2.4 125 * IEEE 802.3-2022 145.2.4
126 * 126 *
127 * @pairset: table of the PSE PI pinout altern 127 * @pairset: table of the PSE PI pinout alternative for the two pairset
128 * @np: device node pointer of the PSE PI node 128 * @np: device node pointer of the PSE PI node
129 * @rdev: regulator represented by the PSE PI 129 * @rdev: regulator represented by the PSE PI
130 * @admin_state_enabled: PI enabled state 130 * @admin_state_enabled: PI enabled state
131 */ 131 */
132 struct pse_pi { 132 struct pse_pi {
133 struct pse_pi_pairset pairset[2]; 133 struct pse_pi_pairset pairset[2];
134 struct device_node *np; 134 struct device_node *np;
135 struct regulator_dev *rdev; 135 struct regulator_dev *rdev;
136 bool admin_state_enabled; 136 bool admin_state_enabled;
137 }; 137 };
138 138
139 /** 139 /**
140 * struct pse_controller_dev - PSE controller 140 * struct pse_controller_dev - PSE controller entity that might
141 * provide multipl 141 * provide multiple PSE controls
142 * @ops: a pointer to device specific struct p 142 * @ops: a pointer to device specific struct pse_controller_ops
143 * @owner: kernel module of the PSE controller 143 * @owner: kernel module of the PSE controller driver
144 * @list: internal list of PSE controller devi 144 * @list: internal list of PSE controller devices
145 * @pse_control_head: head of internal list of 145 * @pse_control_head: head of internal list of requested PSE controls
146 * @dev: corresponding driver model device str 146 * @dev: corresponding driver model device struct
147 * @of_pse_n_cells: number of cells in PSE lin 147 * @of_pse_n_cells: number of cells in PSE line specifiers
148 * @nr_lines: number of PSE controls in this c 148 * @nr_lines: number of PSE controls in this controller device
149 * @lock: Mutex for serialization access to th 149 * @lock: Mutex for serialization access to the PSE controller
150 * @types: types of the PSE controller 150 * @types: types of the PSE controller
151 * @pi: table of PSE PIs described in this con 151 * @pi: table of PSE PIs described in this controller device
152 * @no_of_pse_pi: flag set if the pse_pis devi 152 * @no_of_pse_pi: flag set if the pse_pis devicetree node is not used
153 */ 153 */
154 struct pse_controller_dev { 154 struct pse_controller_dev {
155 const struct pse_controller_ops *ops; 155 const struct pse_controller_ops *ops;
156 struct module *owner; 156 struct module *owner;
157 struct list_head list; 157 struct list_head list;
158 struct list_head pse_control_head; 158 struct list_head pse_control_head;
159 struct device *dev; 159 struct device *dev;
160 int of_pse_n_cells; 160 int of_pse_n_cells;
161 unsigned int nr_lines; 161 unsigned int nr_lines;
162 struct mutex lock; 162 struct mutex lock;
163 enum ethtool_pse_types types; 163 enum ethtool_pse_types types;
164 struct pse_pi *pi; 164 struct pse_pi *pi;
165 bool no_of_pse_pi; 165 bool no_of_pse_pi;
166 }; 166 };
167 167
168 #if IS_ENABLED(CONFIG_PSE_CONTROLLER) 168 #if IS_ENABLED(CONFIG_PSE_CONTROLLER)
169 int pse_controller_register(struct pse_control 169 int pse_controller_register(struct pse_controller_dev *pcdev);
170 void pse_controller_unregister(struct pse_cont 170 void pse_controller_unregister(struct pse_controller_dev *pcdev);
171 struct device; 171 struct device;
172 int devm_pse_controller_register(struct device 172 int devm_pse_controller_register(struct device *dev,
173 struct pse_co 173 struct pse_controller_dev *pcdev);
174 174
175 struct pse_control *of_pse_control_get(struct 175 struct pse_control *of_pse_control_get(struct device_node *node);
176 void pse_control_put(struct pse_control *psec) 176 void pse_control_put(struct pse_control *psec);
177 177
178 int pse_ethtool_get_status(struct pse_control 178 int pse_ethtool_get_status(struct pse_control *psec,
179 struct netlink_ext_ 179 struct netlink_ext_ack *extack,
180 struct pse_control_ 180 struct pse_control_status *status);
181 int pse_ethtool_set_config(struct pse_control 181 int pse_ethtool_set_config(struct pse_control *psec,
182 struct netlink_ext_ 182 struct netlink_ext_ack *extack,
183 const struct pse_co 183 const struct pse_control_config *config);
184 int pse_ethtool_set_pw_limit(struct pse_contro 184 int pse_ethtool_set_pw_limit(struct pse_control *psec,
185 struct netlink_ex 185 struct netlink_ext_ack *extack,
186 const unsigned in 186 const unsigned int pw_limit);
187 int pse_ethtool_get_pw_limit(struct pse_contro 187 int pse_ethtool_get_pw_limit(struct pse_control *psec,
188 struct netlink_ex 188 struct netlink_ext_ack *extack);
189 189
190 bool pse_has_podl(struct pse_control *psec); 190 bool pse_has_podl(struct pse_control *psec);
191 bool pse_has_c33(struct pse_control *psec); 191 bool pse_has_c33(struct pse_control *psec);
192 192
193 #else 193 #else
194 194
195 static inline struct pse_control *of_pse_contr 195 static inline struct pse_control *of_pse_control_get(struct device_node *node)
196 { 196 {
197 return ERR_PTR(-ENOENT); 197 return ERR_PTR(-ENOENT);
198 } 198 }
199 199
200 static inline void pse_control_put(struct pse_ 200 static inline void pse_control_put(struct pse_control *psec)
201 { 201 {
202 } 202 }
203 203
204 static inline int pse_ethtool_get_status(struc 204 static inline int pse_ethtool_get_status(struct pse_control *psec,
205 struc 205 struct netlink_ext_ack *extack,
206 struc 206 struct pse_control_status *status)
207 { 207 {
208 return -EOPNOTSUPP; 208 return -EOPNOTSUPP;
209 } 209 }
210 210
211 static inline int pse_ethtool_set_config(struc 211 static inline int pse_ethtool_set_config(struct pse_control *psec,
212 struc 212 struct netlink_ext_ack *extack,
213 const 213 const struct pse_control_config *config)
214 { 214 {
215 return -EOPNOTSUPP; 215 return -EOPNOTSUPP;
216 } 216 }
217 217
218 static inline int pse_ethtool_set_pw_limit(str 218 static inline int pse_ethtool_set_pw_limit(struct pse_control *psec,
219 str 219 struct netlink_ext_ack *extack,
220 con 220 const unsigned int pw_limit)
221 { 221 {
222 return -EOPNOTSUPP; 222 return -EOPNOTSUPP;
223 } 223 }
224 224
225 static inline int pse_ethtool_get_pw_limit(str 225 static inline int pse_ethtool_get_pw_limit(struct pse_control *psec,
226 str 226 struct netlink_ext_ack *extack)
227 { 227 {
228 return -EOPNOTSUPP; 228 return -EOPNOTSUPP;
229 } 229 }
230 230
231 static inline bool pse_has_podl(struct pse_con 231 static inline bool pse_has_podl(struct pse_control *psec)
232 { 232 {
233 return false; 233 return false;
234 } 234 }
235 235
236 static inline bool pse_has_c33(struct pse_cont 236 static inline bool pse_has_c33(struct pse_control *psec)
237 { 237 {
238 return false; 238 return false;
239 } 239 }
240 240
241 #endif 241 #endif
242 242
243 #endif 243 #endif
244 244
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