1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /*
3 * Copyright (c) 2019 MediaTek Inc.
4 */
5
6 #ifndef __LINUX_REGULATOR_MT6358_H
7 #define __LINUX_REGULATOR_MT6358_H
8
9 enum {
10 MT6358_ID_VDRAM1 = 0,
11 MT6358_ID_VCORE,
12 MT6358_ID_VPA,
13 MT6358_ID_VPROC11,
14 MT6358_ID_VPROC12,
15 MT6358_ID_VGPU,
16 MT6358_ID_VS2,
17 MT6358_ID_VMODEM,
18 MT6358_ID_VS1,
19 MT6358_ID_VDRAM2 = 9,
20 MT6358_ID_VSIM1,
21 MT6358_ID_VIBR,
22 MT6358_ID_VRF12,
23 MT6358_ID_VIO18,
24 MT6358_ID_VUSB,
25 MT6358_ID_VCAMIO,
26 MT6358_ID_VCAMD,
27 MT6358_ID_VCN18,
28 MT6358_ID_VFE28,
29 MT6358_ID_VSRAM_PROC11,
30 MT6358_ID_VCN28,
31 MT6358_ID_VSRAM_OTHERS,
32 MT6358_ID_VSRAM_GPU,
33 MT6358_ID_VXO22,
34 MT6358_ID_VEFUSE,
35 MT6358_ID_VAUX18,
36 MT6358_ID_VMCH,
37 MT6358_ID_VBIF28,
38 MT6358_ID_VSRAM_PROC12,
39 MT6358_ID_VCAMA1,
40 MT6358_ID_VEMC,
41 MT6358_ID_VIO28,
42 MT6358_ID_VA12,
43 MT6358_ID_VRF18,
44 MT6358_ID_VCN33,
45 MT6358_ID_VCAMA2,
46 MT6358_ID_VMC,
47 MT6358_ID_VLDO28,
48 MT6358_ID_VAUD28,
49 MT6358_ID_VSIM2,
50 MT6358_ID_RG_MAX,
51 };
52
53 enum {
54 MT6366_ID_VDRAM1 = 0,
55 MT6366_ID_VCORE,
56 MT6366_ID_VPA,
57 MT6366_ID_VPROC11,
58 MT6366_ID_VPROC12,
59 MT6366_ID_VGPU,
60 MT6366_ID_VS2,
61 MT6366_ID_VMODEM,
62 MT6366_ID_VS1,
63 MT6366_ID_VDRAM2,
64 MT6366_ID_VSIM1,
65 MT6366_ID_VIBR,
66 MT6366_ID_VRF12,
67 MT6366_ID_VIO18,
68 MT6366_ID_VUSB,
69 MT6366_ID_VCN18,
70 MT6366_ID_VFE28,
71 MT6366_ID_VSRAM_PROC11,
72 MT6366_ID_VCN28,
73 MT6366_ID_VSRAM_OTHERS,
74 MT6366_ID_VSRAM_GPU,
75 MT6366_ID_VXO22,
76 MT6366_ID_VEFUSE,
77 MT6366_ID_VAUX18,
78 MT6366_ID_VMCH,
79 MT6366_ID_VBIF28,
80 MT6366_ID_VSRAM_PROC12,
81 MT6366_ID_VEMC,
82 MT6366_ID_VIO28,
83 MT6366_ID_VA12,
84 MT6366_ID_VRF18,
85 MT6366_ID_VCN33,
86 MT6366_ID_VMC,
87 MT6366_ID_VAUD28,
88 MT6366_ID_VSIM2,
89 MT6366_ID_VM18,
90 MT6366_ID_VMDDR,
91 MT6366_ID_VSRAM_CORE,
92 MT6366_ID_RG_MAX,
93 };
94
95 #define MT6358_MAX_REGULATOR MT6358_ID_RG_M
96 #define MT6366_MAX_REGULATOR MT6366_ID_RG_M
97
98 #endif /* __LINUX_REGULATOR_MT6358_H */
99
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