1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * Copyright (c) 2014 MediaTek Inc. 3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Flora Fu <flora.fu@mediatek.com> 4 * Author: Flora Fu <flora.fu@mediatek.com>
5 */ 5 */
6 6
7 #ifndef __LINUX_REGULATOR_MT6397_H 7 #ifndef __LINUX_REGULATOR_MT6397_H
8 #define __LINUX_REGULATOR_MT6397_H 8 #define __LINUX_REGULATOR_MT6397_H
9 9
10 enum { 10 enum {
11 MT6397_ID_VPCA15 = 0, 11 MT6397_ID_VPCA15 = 0,
12 MT6397_ID_VPCA7, 12 MT6397_ID_VPCA7,
13 MT6397_ID_VSRAMCA15, 13 MT6397_ID_VSRAMCA15,
14 MT6397_ID_VSRAMCA7, 14 MT6397_ID_VSRAMCA7,
15 MT6397_ID_VCORE, 15 MT6397_ID_VCORE,
16 MT6397_ID_VGPU, 16 MT6397_ID_VGPU,
17 MT6397_ID_VDRM, 17 MT6397_ID_VDRM,
18 MT6397_ID_VIO18 = 7, 18 MT6397_ID_VIO18 = 7,
19 MT6397_ID_VTCXO, 19 MT6397_ID_VTCXO,
20 MT6397_ID_VA28, 20 MT6397_ID_VA28,
21 MT6397_ID_VCAMA, 21 MT6397_ID_VCAMA,
22 MT6397_ID_VIO28, 22 MT6397_ID_VIO28,
23 MT6397_ID_VUSB, 23 MT6397_ID_VUSB,
24 MT6397_ID_VMC, 24 MT6397_ID_VMC,
25 MT6397_ID_VMCH, 25 MT6397_ID_VMCH,
26 MT6397_ID_VEMC3V3, 26 MT6397_ID_VEMC3V3,
27 MT6397_ID_VGP1, 27 MT6397_ID_VGP1,
28 MT6397_ID_VGP2, 28 MT6397_ID_VGP2,
29 MT6397_ID_VGP3, 29 MT6397_ID_VGP3,
30 MT6397_ID_VGP4, 30 MT6397_ID_VGP4,
31 MT6397_ID_VGP5, 31 MT6397_ID_VGP5,
32 MT6397_ID_VGP6, 32 MT6397_ID_VGP6,
33 MT6397_ID_VIBR, 33 MT6397_ID_VIBR,
34 MT6397_ID_RG_MAX, 34 MT6397_ID_RG_MAX,
35 }; 35 };
36 36
37 #define MT6397_MAX_REGULATOR MT6397_ID_RG_M 37 #define MT6397_MAX_REGULATOR MT6397_ID_RG_MAX
38 #define MT6397_REGULATOR_ID97 0x97 38 #define MT6397_REGULATOR_ID97 0x97
39 #define MT6397_REGULATOR_ID91 0x91 39 #define MT6397_REGULATOR_ID91 0x91
40 40
41 #endif /* __LINUX_REGULATOR_MT6397_H */ 41 #endif /* __LINUX_REGULATOR_MT6397_H */
42 42
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