1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* Driver for Realtek RTS5139 USB card reader 1 /* Driver for Realtek RTS5139 USB card reader
3 * 2 *
4 * Copyright(c) 2009-2013 Realtek Semiconducto 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
>> 4 *
>> 5 * This program is free software; you can redistribute it and/or modify it
>> 6 * under the terms of the GNU General Public License version 2
>> 7 * as published by the Free Software Foundation.
>> 8 *
>> 9 * This program is distributed in the hope that it will be useful, but
>> 10 * WITHOUT ANY WARRANTY; without even the implied warranty of
>> 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> 12 * General Public License for more details.
>> 13 *
>> 14 * You should have received a copy of the GNU General Public License along
>> 15 * with this program; if not, see <http://www.gnu.org/licenses/>.
5 * 16 *
6 * Author: 17 * Author:
7 * Roger Tseng <rogerable@realtek.com> 18 * Roger Tseng <rogerable@realtek.com>
8 */ 19 */
9 20
10 #ifndef __RTSX_USB_H 21 #ifndef __RTSX_USB_H
11 #define __RTSX_USB_H 22 #define __RTSX_USB_H
12 23
13 #include <linux/usb.h> 24 #include <linux/usb.h>
14 25
15 /* related module names */ 26 /* related module names */
16 #define RTSX_USB_SD_CARD 0 27 #define RTSX_USB_SD_CARD 0
17 #define RTSX_USB_MS_CARD 1 28 #define RTSX_USB_MS_CARD 1
18 29
19 /* endpoint numbers */ 30 /* endpoint numbers */
20 #define EP_BULK_OUT 1 31 #define EP_BULK_OUT 1
21 #define EP_BULK_IN 2 32 #define EP_BULK_IN 2
22 #define EP_INTR_IN 3 33 #define EP_INTR_IN 3
23 34
24 /* USB vendor requests */ 35 /* USB vendor requests */
25 #define RTSX_USB_REQ_REG_OP 0x00 36 #define RTSX_USB_REQ_REG_OP 0x00
26 #define RTSX_USB_REQ_POLL 0x02 37 #define RTSX_USB_REQ_POLL 0x02
27 38
28 /* miscellaneous parameters */ 39 /* miscellaneous parameters */
29 #define MIN_DIV_N 60 40 #define MIN_DIV_N 60
30 #define MAX_DIV_N 120 41 #define MAX_DIV_N 120
31 42
32 #define MAX_PHASE 15 43 #define MAX_PHASE 15
33 #define RX_TUNING_CNT 3 44 #define RX_TUNING_CNT 3
34 45
35 #define QFN24 0 46 #define QFN24 0
36 #define LQFP48 1 47 #define LQFP48 1
37 #define CHECK_PKG(ucr, pkg) ((ucr)->packag 48 #define CHECK_PKG(ucr, pkg) ((ucr)->package == (pkg))
38 49
39 /* data structures */ 50 /* data structures */
40 struct rtsx_ucr { 51 struct rtsx_ucr {
41 u16 vendor_id; 52 u16 vendor_id;
42 u16 product_id; 53 u16 product_id;
43 54
44 int package; 55 int package;
45 u8 ic_version; 56 u8 ic_version;
46 bool is_rts5179; 57 bool is_rts5179;
47 58
48 unsigned int cur_clk; 59 unsigned int cur_clk;
49 60
50 u8 *cmd_buf; 61 u8 *cmd_buf;
51 unsigned int cmd_idx; 62 unsigned int cmd_idx;
52 u8 *rsp_buf; 63 u8 *rsp_buf;
53 64
54 struct usb_device *pusb_dev; 65 struct usb_device *pusb_dev;
55 struct usb_interface *pusb_intf; 66 struct usb_interface *pusb_intf;
56 struct usb_sg_request current_sg; 67 struct usb_sg_request current_sg;
57 68
58 struct timer_list sg_timer; 69 struct timer_list sg_timer;
59 struct mutex dev_mutex; 70 struct mutex dev_mutex;
60 }; 71 };
61 72
62 /* buffer size */ 73 /* buffer size */
63 #define IOBUF_SIZE 1024 74 #define IOBUF_SIZE 1024
64 75
65 /* prototypes of exported functions */ 76 /* prototypes of exported functions */
66 extern int rtsx_usb_get_card_status(struct rts 77 extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
67 78
68 extern int rtsx_usb_read_register(struct rtsx_ 79 extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
69 extern int rtsx_usb_write_register(struct rtsx 80 extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
70 u8 data); 81 u8 data);
71 82
72 extern int rtsx_usb_ep0_write_register(struct 83 extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
73 u8 data); 84 u8 data);
74 extern int rtsx_usb_ep0_read_register(struct r 85 extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
75 u8 *data); 86 u8 *data);
76 87
77 extern void rtsx_usb_add_cmd(struct rtsx_ucr * 88 extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
78 u16 reg_addr, u8 mask, u8 data 89 u16 reg_addr, u8 mask, u8 data);
79 extern int rtsx_usb_send_cmd(struct rtsx_ucr * 90 extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
80 extern int rtsx_usb_get_rsp(struct rtsx_ucr *u 91 extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
81 extern int rtsx_usb_transfer_data(struct rtsx_ 92 extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
82 void *buf, unsig 93 void *buf, unsigned int len, int use_sg,
83 unsigned int *ac 94 unsigned int *act_len, int timeout);
84 95
85 extern int rtsx_usb_read_ppbuf(struct rtsx_ucr 96 extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
86 extern int rtsx_usb_write_ppbuf(struct rtsx_uc 97 extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
87 extern int rtsx_usb_switch_clock(struct rtsx_u 98 extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
88 u8 ssc_depth, bool initial_mod 99 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
89 extern int rtsx_usb_card_exclusive_check(struc 100 extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
90 101
91 /* card status */ 102 /* card status */
92 #define SD_CD 0x01 103 #define SD_CD 0x01
93 #define MS_CD 0x02 104 #define MS_CD 0x02
94 #define XD_CD 0x04 105 #define XD_CD 0x04
95 #define CD_MASK (SD_CD | MS_CD | XD_CD 106 #define CD_MASK (SD_CD | MS_CD | XD_CD)
96 #define SD_WP 0x08 107 #define SD_WP 0x08
97 108
98 /* reader command field offset & parameters */ 109 /* reader command field offset & parameters */
99 #define READ_REG_CMD 0 110 #define READ_REG_CMD 0
100 #define WRITE_REG_CMD 1 111 #define WRITE_REG_CMD 1
101 #define CHECK_REG_CMD 2 112 #define CHECK_REG_CMD 2
102 113
103 #define PACKET_TYPE 4 114 #define PACKET_TYPE 4
104 #define CNT_H 5 115 #define CNT_H 5
105 #define CNT_L 6 116 #define CNT_L 6
106 #define STAGE_FLAG 7 117 #define STAGE_FLAG 7
107 #define CMD_OFFSET 8 118 #define CMD_OFFSET 8
108 #define SEQ_WRITE_DATA_OFFSET 12 119 #define SEQ_WRITE_DATA_OFFSET 12
109 120
110 #define BATCH_CMD 0 121 #define BATCH_CMD 0
111 #define SEQ_READ 1 122 #define SEQ_READ 1
112 #define SEQ_WRITE 2 123 #define SEQ_WRITE 2
113 124
114 #define STAGE_R 0x01 125 #define STAGE_R 0x01
115 #define STAGE_DI 0x02 126 #define STAGE_DI 0x02
116 #define STAGE_DO 0x04 127 #define STAGE_DO 0x04
117 #define STAGE_MS_STATUS 0x08 128 #define STAGE_MS_STATUS 0x08
118 #define STAGE_XD_STATUS 0x10 129 #define STAGE_XD_STATUS 0x10
119 #define MODE_C 0x00 130 #define MODE_C 0x00
120 #define MODE_CR (STAGE_R) 131 #define MODE_CR (STAGE_R)
121 #define MODE_CDIR (STAGE_R | STA 132 #define MODE_CDIR (STAGE_R | STAGE_DI)
122 #define MODE_CDOR (STAGE_R | STA 133 #define MODE_CDOR (STAGE_R | STAGE_DO)
123 134
124 #define EP0_OP_SHIFT 14 135 #define EP0_OP_SHIFT 14
125 #define EP0_READ_REG_CMD 2 136 #define EP0_READ_REG_CMD 2
126 #define EP0_WRITE_REG_CMD 3 137 #define EP0_WRITE_REG_CMD 3
127 138
128 #define rtsx_usb_cmd_hdr_tag(ucr) 139 #define rtsx_usb_cmd_hdr_tag(ucr) \
129 do { 140 do { \
130 ucr->cmd_buf[0] = 'R'; 141 ucr->cmd_buf[0] = 'R'; \
131 ucr->cmd_buf[1] = 'T'; 142 ucr->cmd_buf[1] = 'T'; \
132 ucr->cmd_buf[2] = 'C'; 143 ucr->cmd_buf[2] = 'C'; \
133 ucr->cmd_buf[3] = 'R'; 144 ucr->cmd_buf[3] = 'R'; \
134 } while (0) 145 } while (0)
135 146
136 static inline void rtsx_usb_init_cmd(struct rt 147 static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
137 { 148 {
138 rtsx_usb_cmd_hdr_tag(ucr); 149 rtsx_usb_cmd_hdr_tag(ucr);
139 ucr->cmd_idx = 0; 150 ucr->cmd_idx = 0;
140 ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD; 151 ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
141 } 152 }
142 153
143 /* internal register address */ 154 /* internal register address */
144 #define FPDCTL 0xFC00 155 #define FPDCTL 0xFC00
145 #define SSC_DIV_N_0 0xFC07 156 #define SSC_DIV_N_0 0xFC07
146 #define SSC_CTL1 0xFC09 157 #define SSC_CTL1 0xFC09
147 #define SSC_CTL2 0xFC0A 158 #define SSC_CTL2 0xFC0A
148 #define CFG_MODE 0xFC0E 159 #define CFG_MODE 0xFC0E
149 #define CFG_MODE_1 0xFC0F 160 #define CFG_MODE_1 0xFC0F
150 #define RCCTL 0xFC14 161 #define RCCTL 0xFC14
151 #define SOF_WDOG 0xFC28 162 #define SOF_WDOG 0xFC28
152 #define SYS_DUMMY0 0xFC30 163 #define SYS_DUMMY0 0xFC30
153 164
154 #define MS_BLKEND 0xFD30 165 #define MS_BLKEND 0xFD30
155 #define MS_READ_START 0xFD31 166 #define MS_READ_START 0xFD31
156 #define MS_READ_COUNT 0xFD32 167 #define MS_READ_COUNT 0xFD32
157 #define MS_WRITE_START 0xFD33 168 #define MS_WRITE_START 0xFD33
158 #define MS_WRITE_COUNT 0xFD34 169 #define MS_WRITE_COUNT 0xFD34
159 #define MS_COMMAND 0xFD35 170 #define MS_COMMAND 0xFD35
160 #define MS_OLD_BLOCK_0 0xFD36 171 #define MS_OLD_BLOCK_0 0xFD36
161 #define MS_OLD_BLOCK_1 0xFD37 172 #define MS_OLD_BLOCK_1 0xFD37
162 #define MS_NEW_BLOCK_0 0xFD38 173 #define MS_NEW_BLOCK_0 0xFD38
163 #define MS_NEW_BLOCK_1 0xFD39 174 #define MS_NEW_BLOCK_1 0xFD39
164 #define MS_LOG_BLOCK_0 0xFD3A 175 #define MS_LOG_BLOCK_0 0xFD3A
165 #define MS_LOG_BLOCK_1 0xFD3B 176 #define MS_LOG_BLOCK_1 0xFD3B
166 #define MS_BUS_WIDTH 0xFD3C 177 #define MS_BUS_WIDTH 0xFD3C
167 #define MS_PAGE_START 0xFD3D 178 #define MS_PAGE_START 0xFD3D
168 #define MS_PAGE_LENGTH 0xFD3E 179 #define MS_PAGE_LENGTH 0xFD3E
169 #define MS_CFG 0xFD40 180 #define MS_CFG 0xFD40
170 #define MS_TPC 0xFD41 181 #define MS_TPC 0xFD41
171 #define MS_TRANS_CFG 0xFD42 182 #define MS_TRANS_CFG 0xFD42
172 #define MS_TRANSFER 0xFD43 183 #define MS_TRANSFER 0xFD43
173 #define MS_INT_REG 0xFD44 184 #define MS_INT_REG 0xFD44
174 #define MS_BYTE_CNT 0xFD45 185 #define MS_BYTE_CNT 0xFD45
175 #define MS_SECTOR_CNT_L 0xFD46 186 #define MS_SECTOR_CNT_L 0xFD46
176 #define MS_SECTOR_CNT_H 0xFD47 187 #define MS_SECTOR_CNT_H 0xFD47
177 #define MS_DBUS_H 0xFD48 188 #define MS_DBUS_H 0xFD48
178 189
179 #define CARD_DMA1_CTL 0xFD5C 190 #define CARD_DMA1_CTL 0xFD5C
180 #define CARD_PULL_CTL1 0xFD60 191 #define CARD_PULL_CTL1 0xFD60
181 #define CARD_PULL_CTL2 0xFD61 192 #define CARD_PULL_CTL2 0xFD61
182 #define CARD_PULL_CTL3 0xFD62 193 #define CARD_PULL_CTL3 0xFD62
183 #define CARD_PULL_CTL4 0xFD63 194 #define CARD_PULL_CTL4 0xFD63
184 #define CARD_PULL_CTL5 0xFD64 195 #define CARD_PULL_CTL5 0xFD64
185 #define CARD_PULL_CTL6 0xFD65 196 #define CARD_PULL_CTL6 0xFD65
186 #define CARD_EXIST 0xFD6F 197 #define CARD_EXIST 0xFD6F
187 #define CARD_INT_PEND 0xFD71 198 #define CARD_INT_PEND 0xFD71
188 199
189 #define LDO_POWER_CFG 0xFD7B 200 #define LDO_POWER_CFG 0xFD7B
190 201
191 #define SD_CFG1 0xFDA0 202 #define SD_CFG1 0xFDA0
192 #define SD_CFG2 0xFDA1 203 #define SD_CFG2 0xFDA1
193 #define SD_CFG3 0xFDA2 204 #define SD_CFG3 0xFDA2
194 #define SD_STAT1 0xFDA3 205 #define SD_STAT1 0xFDA3
195 #define SD_STAT2 0xFDA4 206 #define SD_STAT2 0xFDA4
196 #define SD_BUS_STAT 0xFDA5 207 #define SD_BUS_STAT 0xFDA5
197 #define SD_PAD_CTL 0xFDA6 208 #define SD_PAD_CTL 0xFDA6
198 #define SD_SAMPLE_POINT_CTL 0xFDA7 209 #define SD_SAMPLE_POINT_CTL 0xFDA7
199 #define SD_PUSH_POINT_CTL 0xFDA8 210 #define SD_PUSH_POINT_CTL 0xFDA8
200 #define SD_CMD0 0xFDA9 211 #define SD_CMD0 0xFDA9
201 #define SD_CMD1 0xFDAA 212 #define SD_CMD1 0xFDAA
202 #define SD_CMD2 0xFDAB 213 #define SD_CMD2 0xFDAB
203 #define SD_CMD3 0xFDAC 214 #define SD_CMD3 0xFDAC
204 #define SD_CMD4 0xFDAD 215 #define SD_CMD4 0xFDAD
205 #define SD_CMD5 0xFDAE 216 #define SD_CMD5 0xFDAE
206 #define SD_BYTE_CNT_L 0xFDAF 217 #define SD_BYTE_CNT_L 0xFDAF
207 #define SD_BYTE_CNT_H 0xFDB0 218 #define SD_BYTE_CNT_H 0xFDB0
208 #define SD_BLOCK_CNT_L 0xFDB1 219 #define SD_BLOCK_CNT_L 0xFDB1
209 #define SD_BLOCK_CNT_H 0xFDB2 220 #define SD_BLOCK_CNT_H 0xFDB2
210 #define SD_TRANSFER 0xFDB3 221 #define SD_TRANSFER 0xFDB3
211 #define SD_CMD_STATE 0xFDB5 222 #define SD_CMD_STATE 0xFDB5
212 #define SD_DATA_STATE 0xFDB6 223 #define SD_DATA_STATE 0xFDB6
213 #define SD_VPCLK0_CTL 0xFC2A 224 #define SD_VPCLK0_CTL 0xFC2A
214 #define SD_VPCLK1_CTL 0xFC2B 225 #define SD_VPCLK1_CTL 0xFC2B
215 #define SD_DCMPS0_CTL 0xFC2C 226 #define SD_DCMPS0_CTL 0xFC2C
216 #define SD_DCMPS1_CTL 0xFC2D 227 #define SD_DCMPS1_CTL 0xFC2D
217 228
218 #define CARD_DMA1_CTL 0xFD5C 229 #define CARD_DMA1_CTL 0xFD5C
219 230
220 #define HW_VERSION 0xFC01 231 #define HW_VERSION 0xFC01
221 232
222 #define SSC_CLK_FPGA_SEL 0xFC02 233 #define SSC_CLK_FPGA_SEL 0xFC02
223 #define CLK_DIV 0xFC03 234 #define CLK_DIV 0xFC03
224 #define SFSM_ED 0xFC04 235 #define SFSM_ED 0xFC04
225 236
226 #define CD_DEGLITCH_WIDTH 0xFC20 237 #define CD_DEGLITCH_WIDTH 0xFC20
227 #define CD_DEGLITCH_EN 0xFC21 238 #define CD_DEGLITCH_EN 0xFC21
228 #define AUTO_DELINK_EN 0xFC23 239 #define AUTO_DELINK_EN 0xFC23
229 240
230 #define FPGA_PULL_CTL 0xFC1D 241 #define FPGA_PULL_CTL 0xFC1D
231 #define CARD_CLK_SOURCE 0xFC2E 242 #define CARD_CLK_SOURCE 0xFC2E
232 243
233 #define CARD_SHARE_MODE 0xFD51 244 #define CARD_SHARE_MODE 0xFD51
234 #define CARD_DRIVE_SEL 0xFD52 245 #define CARD_DRIVE_SEL 0xFD52
235 #define CARD_STOP 0xFD53 246 #define CARD_STOP 0xFD53
236 #define CARD_OE 0xFD54 247 #define CARD_OE 0xFD54
237 #define CARD_AUTO_BLINK 0xFD55 248 #define CARD_AUTO_BLINK 0xFD55
238 #define CARD_GPIO 0xFD56 249 #define CARD_GPIO 0xFD56
239 #define SD30_DRIVE_SEL 0xFD57 250 #define SD30_DRIVE_SEL 0xFD57
240 251
241 #define CARD_DATA_SOURCE 0xFD5D 252 #define CARD_DATA_SOURCE 0xFD5D
242 #define CARD_SELECT 0xFD5E 253 #define CARD_SELECT 0xFD5E
243 254
244 #define CARD_CLK_EN 0xFD79 255 #define CARD_CLK_EN 0xFD79
245 #define CARD_PWR_CTL 0xFD7A 256 #define CARD_PWR_CTL 0xFD7A
246 257
247 #define OCPCTL 0xFD80 258 #define OCPCTL 0xFD80
248 #define OCPPARA1 0xFD81 259 #define OCPPARA1 0xFD81
249 #define OCPPARA2 0xFD82 260 #define OCPPARA2 0xFD82
250 #define OCPSTAT 0xFD83 261 #define OCPSTAT 0xFD83
251 262
252 #define HS_USB_STAT 0xFE01 263 #define HS_USB_STAT 0xFE01
253 #define HS_VCONTROL 0xFE26 264 #define HS_VCONTROL 0xFE26
254 #define HS_VSTAIN 0xFE27 265 #define HS_VSTAIN 0xFE27
255 #define HS_VLOADM 0xFE28 266 #define HS_VLOADM 0xFE28
256 #define HS_VSTAOUT 0xFE29 267 #define HS_VSTAOUT 0xFE29
257 268
258 #define MC_IRQ 0xFF00 269 #define MC_IRQ 0xFF00
259 #define MC_IRQEN 0xFF01 270 #define MC_IRQEN 0xFF01
260 #define MC_FIFO_CTL 0xFF02 271 #define MC_FIFO_CTL 0xFF02
261 #define MC_FIFO_BC0 0xFF03 272 #define MC_FIFO_BC0 0xFF03
262 #define MC_FIFO_BC1 0xFF04 273 #define MC_FIFO_BC1 0xFF04
263 #define MC_FIFO_STAT 0xFF05 274 #define MC_FIFO_STAT 0xFF05
264 #define MC_FIFO_MODE 0xFF06 275 #define MC_FIFO_MODE 0xFF06
265 #define MC_FIFO_RD_PTR0 0xFF07 276 #define MC_FIFO_RD_PTR0 0xFF07
266 #define MC_FIFO_RD_PTR1 0xFF08 277 #define MC_FIFO_RD_PTR1 0xFF08
267 #define MC_DMA_CTL 0xFF10 278 #define MC_DMA_CTL 0xFF10
268 #define MC_DMA_TC0 0xFF11 279 #define MC_DMA_TC0 0xFF11
269 #define MC_DMA_TC1 0xFF12 280 #define MC_DMA_TC1 0xFF12
270 #define MC_DMA_TC2 0xFF13 281 #define MC_DMA_TC2 0xFF13
271 #define MC_DMA_TC3 0xFF14 282 #define MC_DMA_TC3 0xFF14
272 #define MC_DMA_RST 0xFF15 283 #define MC_DMA_RST 0xFF15
273 284
274 #define RBUF_SIZE_MASK 0xFBFF 285 #define RBUF_SIZE_MASK 0xFBFF
275 #define RBUF_BASE 0xF000 286 #define RBUF_BASE 0xF000
276 #define PPBUF_BASE1 0xF800 287 #define PPBUF_BASE1 0xF800
277 #define PPBUF_BASE2 0xFA00 288 #define PPBUF_BASE2 0xFA00
278 289
279 /* internal register value macros */ 290 /* internal register value macros */
280 #define POWER_OFF 0x03 291 #define POWER_OFF 0x03
281 #define PARTIAL_POWER_ON 0x02 292 #define PARTIAL_POWER_ON 0x02
282 #define POWER_ON 0x00 293 #define POWER_ON 0x00
283 #define POWER_MASK 0x03 294 #define POWER_MASK 0x03
284 #define LDO3318_PWR_MASK 0x0C 295 #define LDO3318_PWR_MASK 0x0C
285 #define LDO_ON 0x00 296 #define LDO_ON 0x00
286 #define LDO_SUSPEND 0x08 297 #define LDO_SUSPEND 0x08
287 #define LDO_OFF 0x0C 298 #define LDO_OFF 0x0C
288 #define DV3318_AUTO_PWR_OFF 0x10 299 #define DV3318_AUTO_PWR_OFF 0x10
289 #define FORCE_LDO_POWERB 0x60 300 #define FORCE_LDO_POWERB 0x60
290 301
291 /* LDO_POWER_CFG */ 302 /* LDO_POWER_CFG */
292 #define TUNE_SD18_MASK 0x1C 303 #define TUNE_SD18_MASK 0x1C
293 #define TUNE_SD18_1V7 0x00 304 #define TUNE_SD18_1V7 0x00
294 #define TUNE_SD18_1V8 (0x01 305 #define TUNE_SD18_1V8 (0x01 << 2)
295 #define TUNE_SD18_1V9 (0x02 306 #define TUNE_SD18_1V9 (0x02 << 2)
296 #define TUNE_SD18_2V0 (0x03 307 #define TUNE_SD18_2V0 (0x03 << 2)
297 #define TUNE_SD18_2V7 (0x04 308 #define TUNE_SD18_2V7 (0x04 << 2)
298 #define TUNE_SD18_2V8 (0x05 309 #define TUNE_SD18_2V8 (0x05 << 2)
299 #define TUNE_SD18_2V9 (0x06 310 #define TUNE_SD18_2V9 (0x06 << 2)
300 #define TUNE_SD18_3V3 (0x07 311 #define TUNE_SD18_3V3 (0x07 << 2)
301 312
302 /* CLK_DIV */ 313 /* CLK_DIV */
303 #define CLK_CHANGE 0x80 314 #define CLK_CHANGE 0x80
304 #define CLK_DIV_1 0x00 315 #define CLK_DIV_1 0x00
305 #define CLK_DIV_2 0x01 316 #define CLK_DIV_2 0x01
306 #define CLK_DIV_4 0x02 317 #define CLK_DIV_4 0x02
307 #define CLK_DIV_8 0x03 318 #define CLK_DIV_8 0x03
308 319
309 #define SSC_POWER_MASK 0x01 320 #define SSC_POWER_MASK 0x01
310 #define SSC_POWER_DOWN 0x01 321 #define SSC_POWER_DOWN 0x01
311 #define SSC_POWER_ON 0x00 322 #define SSC_POWER_ON 0x00
312 323
313 #define FPGA_VER 0x80 324 #define FPGA_VER 0x80
314 #define HW_VER_MASK 0x0F 325 #define HW_VER_MASK 0x0F
315 326
316 #define EXTEND_DMA1_ASYNC_SIGNAL 0x02 327 #define EXTEND_DMA1_ASYNC_SIGNAL 0x02
317 328
318 /* CFG_MODE*/ 329 /* CFG_MODE*/
319 #define XTAL_FREE 0x80 330 #define XTAL_FREE 0x80
320 #define CLK_MODE_MASK 0x03 331 #define CLK_MODE_MASK 0x03
321 #define CLK_MODE_12M_XTAL 0x00 332 #define CLK_MODE_12M_XTAL 0x00
322 #define CLK_MODE_NON_XTAL 0x01 333 #define CLK_MODE_NON_XTAL 0x01
323 #define CLK_MODE_24M_OSC 0x02 334 #define CLK_MODE_24M_OSC 0x02
324 #define CLK_MODE_48M_OSC 0x03 335 #define CLK_MODE_48M_OSC 0x03
325 336
326 /* CFG_MODE_1*/ 337 /* CFG_MODE_1*/
327 #define RTS5179 0x02 338 #define RTS5179 0x02
328 339
329 #define NYET_EN 0x01 340 #define NYET_EN 0x01
330 #define NYET_MSAK 0x01 341 #define NYET_MSAK 0x01
331 342
332 #define SD30_DRIVE_MASK 0x07 343 #define SD30_DRIVE_MASK 0x07
333 #define SD20_DRIVE_MASK 0x03 344 #define SD20_DRIVE_MASK 0x03
334 345
335 #define DISABLE_SD_CD 0x08 346 #define DISABLE_SD_CD 0x08
336 #define DISABLE_MS_CD 0x10 347 #define DISABLE_MS_CD 0x10
337 #define DISABLE_XD_CD 0x20 348 #define DISABLE_XD_CD 0x20
338 #define SD_CD_DEGLITCH_EN 0x01 349 #define SD_CD_DEGLITCH_EN 0x01
339 #define MS_CD_DEGLITCH_EN 0x02 350 #define MS_CD_DEGLITCH_EN 0x02
340 #define XD_CD_DEGLITCH_EN 0x04 351 #define XD_CD_DEGLITCH_EN 0x04
341 352
342 #define CARD_SHARE_LQFP48 0x04 353 #define CARD_SHARE_LQFP48 0x04
343 #define CARD_SHARE_QFN24 0x00 354 #define CARD_SHARE_QFN24 0x00
344 #define CARD_SHARE_LQFP_SEL 0x04 355 #define CARD_SHARE_LQFP_SEL 0x04
345 #define CARD_SHARE_XD 0x00 356 #define CARD_SHARE_XD 0x00
346 #define CARD_SHARE_SD 0x01 357 #define CARD_SHARE_SD 0x01
347 #define CARD_SHARE_MS 0x02 358 #define CARD_SHARE_MS 0x02
348 #define CARD_SHARE_MASK 0x03 359 #define CARD_SHARE_MASK 0x03
349 360
350 361
351 /* SD30_DRIVE_SEL */ 362 /* SD30_DRIVE_SEL */
352 #define DRIVER_TYPE_A 0x05 363 #define DRIVER_TYPE_A 0x05
353 #define DRIVER_TYPE_B 0x03 364 #define DRIVER_TYPE_B 0x03
354 #define DRIVER_TYPE_C 0x02 365 #define DRIVER_TYPE_C 0x02
355 #define DRIVER_TYPE_D 0x01 366 #define DRIVER_TYPE_D 0x01
356 367
357 /* SD_BUS_STAT */ 368 /* SD_BUS_STAT */
358 #define SD_CLK_TOGGLE_EN 0x80 369 #define SD_CLK_TOGGLE_EN 0x80
359 #define SD_CLK_FORCE_STOP 0x40 370 #define SD_CLK_FORCE_STOP 0x40
360 #define SD_DAT3_STATUS 0x10 371 #define SD_DAT3_STATUS 0x10
361 #define SD_DAT2_STATUS 0x08 372 #define SD_DAT2_STATUS 0x08
362 #define SD_DAT1_STATUS 0x04 373 #define SD_DAT1_STATUS 0x04
363 #define SD_DAT0_STATUS 0x02 374 #define SD_DAT0_STATUS 0x02
364 #define SD_CMD_STATUS 0x01 375 #define SD_CMD_STATUS 0x01
365 376
366 /* SD_PAD_CTL */ 377 /* SD_PAD_CTL */
367 #define SD_IO_USING_1V8 0x80 378 #define SD_IO_USING_1V8 0x80
368 #define SD_IO_USING_3V3 0x7F 379 #define SD_IO_USING_3V3 0x7F
369 #define TYPE_A_DRIVING 0x00 380 #define TYPE_A_DRIVING 0x00
370 #define TYPE_B_DRIVING 0x01 381 #define TYPE_B_DRIVING 0x01
371 #define TYPE_C_DRIVING 0x02 382 #define TYPE_C_DRIVING 0x02
372 #define TYPE_D_DRIVING 0x03 383 #define TYPE_D_DRIVING 0x03
373 384
374 /* CARD_CLK_EN */ 385 /* CARD_CLK_EN */
375 #define SD_CLK_EN 0x04 386 #define SD_CLK_EN 0x04
376 #define MS_CLK_EN 0x08 387 #define MS_CLK_EN 0x08
377 388
378 /* CARD_SELECT */ 389 /* CARD_SELECT */
379 #define SD_MOD_SEL 2 390 #define SD_MOD_SEL 2
380 #define MS_MOD_SEL 3 391 #define MS_MOD_SEL 3
381 392
382 /* CARD_SHARE_MODE */ 393 /* CARD_SHARE_MODE */
383 #define CARD_SHARE_LQFP48 0x04 394 #define CARD_SHARE_LQFP48 0x04
384 #define CARD_SHARE_QFN24 0x00 395 #define CARD_SHARE_QFN24 0x00
385 #define CARD_SHARE_LQFP_SEL 0x04 396 #define CARD_SHARE_LQFP_SEL 0x04
386 #define CARD_SHARE_XD 0x00 397 #define CARD_SHARE_XD 0x00
387 #define CARD_SHARE_SD 0x01 398 #define CARD_SHARE_SD 0x01
388 #define CARD_SHARE_MS 0x02 399 #define CARD_SHARE_MS 0x02
389 #define CARD_SHARE_MASK 0x03 400 #define CARD_SHARE_MASK 0x03
390 401
391 /* SSC_CTL1 */ 402 /* SSC_CTL1 */
392 #define SSC_RSTB 0x80 403 #define SSC_RSTB 0x80
393 #define SSC_8X_EN 0x40 404 #define SSC_8X_EN 0x40
394 #define SSC_FIX_FRAC 0x20 405 #define SSC_FIX_FRAC 0x20
395 #define SSC_SEL_1M 0x00 406 #define SSC_SEL_1M 0x00
396 #define SSC_SEL_2M 0x08 407 #define SSC_SEL_2M 0x08
397 #define SSC_SEL_4M 0x10 408 #define SSC_SEL_4M 0x10
398 #define SSC_SEL_8M 0x18 409 #define SSC_SEL_8M 0x18
399 410
400 /* SSC_CTL2 */ 411 /* SSC_CTL2 */
401 #define SSC_DEPTH_MASK 0x03 412 #define SSC_DEPTH_MASK 0x03
402 #define SSC_DEPTH_DISALBE 0x00 413 #define SSC_DEPTH_DISALBE 0x00
403 #define SSC_DEPTH_2M 0x01 414 #define SSC_DEPTH_2M 0x01
404 #define SSC_DEPTH_1M 0x02 415 #define SSC_DEPTH_1M 0x02
405 #define SSC_DEPTH_512K 0x03 416 #define SSC_DEPTH_512K 0x03
406 417
407 /* SD_VPCLK0_CTL */ 418 /* SD_VPCLK0_CTL */
408 #define PHASE_CHANGE 0x80 419 #define PHASE_CHANGE 0x80
409 #define PHASE_NOT_RESET 0x40 420 #define PHASE_NOT_RESET 0x40
410 421
411 /* SD_TRANSFER */ 422 /* SD_TRANSFER */
412 #define SD_TRANSFER_START 0x80 423 #define SD_TRANSFER_START 0x80
413 #define SD_TRANSFER_END 0x40 424 #define SD_TRANSFER_END 0x40
414 #define SD_STAT_IDLE 0x20 425 #define SD_STAT_IDLE 0x20
415 #define SD_TRANSFER_ERR 0x10 426 #define SD_TRANSFER_ERR 0x10
416 #define SD_TM_NORMAL_WRITE 0x00 427 #define SD_TM_NORMAL_WRITE 0x00
417 #define SD_TM_AUTO_WRITE_3 0x01 428 #define SD_TM_AUTO_WRITE_3 0x01
418 #define SD_TM_AUTO_WRITE_4 0x02 429 #define SD_TM_AUTO_WRITE_4 0x02
419 #define SD_TM_AUTO_READ_3 0x05 430 #define SD_TM_AUTO_READ_3 0x05
420 #define SD_TM_AUTO_READ_4 0x06 431 #define SD_TM_AUTO_READ_4 0x06
421 #define SD_TM_CMD_RSP 0x08 432 #define SD_TM_CMD_RSP 0x08
422 #define SD_TM_AUTO_WRITE_1 0x09 433 #define SD_TM_AUTO_WRITE_1 0x09
423 #define SD_TM_AUTO_WRITE_2 0x0A 434 #define SD_TM_AUTO_WRITE_2 0x0A
424 #define SD_TM_NORMAL_READ 0x0C 435 #define SD_TM_NORMAL_READ 0x0C
425 #define SD_TM_AUTO_READ_1 0x0D 436 #define SD_TM_AUTO_READ_1 0x0D
426 #define SD_TM_AUTO_READ_2 0x0E 437 #define SD_TM_AUTO_READ_2 0x0E
427 #define SD_TM_AUTO_TUNING 0x0F 438 #define SD_TM_AUTO_TUNING 0x0F
428 439
429 /* SD_CFG1 */ 440 /* SD_CFG1 */
430 #define SD_CLK_DIVIDE_0 0x00 441 #define SD_CLK_DIVIDE_0 0x00
431 #define SD_CLK_DIVIDE_256 0xC0 442 #define SD_CLK_DIVIDE_256 0xC0
432 #define SD_CLK_DIVIDE_128 0x80 443 #define SD_CLK_DIVIDE_128 0x80
433 #define SD_CLK_DIVIDE_MASK 0xC0 444 #define SD_CLK_DIVIDE_MASK 0xC0
434 #define SD_BUS_WIDTH_1BIT 0x00 445 #define SD_BUS_WIDTH_1BIT 0x00
435 #define SD_BUS_WIDTH_4BIT 0x01 446 #define SD_BUS_WIDTH_4BIT 0x01
436 #define SD_BUS_WIDTH_8BIT 0x02 447 #define SD_BUS_WIDTH_8BIT 0x02
437 #define SD_ASYNC_FIFO_RST 0x10 448 #define SD_ASYNC_FIFO_RST 0x10
438 #define SD_20_MODE 0x00 449 #define SD_20_MODE 0x00
439 #define SD_DDR_MODE 0x04 450 #define SD_DDR_MODE 0x04
440 #define SD_30_MODE 0x08 451 #define SD_30_MODE 0x08
441 452
442 /* SD_CFG2 */ 453 /* SD_CFG2 */
443 #define SD_CALCULATE_CRC7 0x00 454 #define SD_CALCULATE_CRC7 0x00
444 #define SD_NO_CALCULATE_CRC7 0x80 455 #define SD_NO_CALCULATE_CRC7 0x80
445 #define SD_CHECK_CRC16 0x00 456 #define SD_CHECK_CRC16 0x00
446 #define SD_NO_CHECK_CRC16 0x40 457 #define SD_NO_CHECK_CRC16 0x40
447 #define SD_WAIT_CRC_TO_EN 0x20 458 #define SD_WAIT_CRC_TO_EN 0x20
448 #define SD_WAIT_BUSY_END 0x08 459 #define SD_WAIT_BUSY_END 0x08
449 #define SD_NO_WAIT_BUSY_END 0x00 460 #define SD_NO_WAIT_BUSY_END 0x00
450 #define SD_CHECK_CRC7 0x00 461 #define SD_CHECK_CRC7 0x00
451 #define SD_NO_CHECK_CRC7 0x04 462 #define SD_NO_CHECK_CRC7 0x04
452 #define SD_RSP_LEN_0 0x00 463 #define SD_RSP_LEN_0 0x00
453 #define SD_RSP_LEN_6 0x01 464 #define SD_RSP_LEN_6 0x01
454 #define SD_RSP_LEN_17 0x02 465 #define SD_RSP_LEN_17 0x02
455 #define SD_RSP_TYPE_R0 0x04 466 #define SD_RSP_TYPE_R0 0x04
456 #define SD_RSP_TYPE_R1 0x01 467 #define SD_RSP_TYPE_R1 0x01
457 #define SD_RSP_TYPE_R1b 0x09 468 #define SD_RSP_TYPE_R1b 0x09
458 #define SD_RSP_TYPE_R2 0x02 469 #define SD_RSP_TYPE_R2 0x02
459 #define SD_RSP_TYPE_R3 0x05 470 #define SD_RSP_TYPE_R3 0x05
460 #define SD_RSP_TYPE_R4 0x05 471 #define SD_RSP_TYPE_R4 0x05
461 #define SD_RSP_TYPE_R5 0x01 472 #define SD_RSP_TYPE_R5 0x01
462 #define SD_RSP_TYPE_R6 0x01 473 #define SD_RSP_TYPE_R6 0x01
463 #define SD_RSP_TYPE_R7 0x01 474 #define SD_RSP_TYPE_R7 0x01
464 475
465 /* SD_STAT1 */ 476 /* SD_STAT1 */
466 #define SD_CRC7_ERR 0x80 477 #define SD_CRC7_ERR 0x80
467 #define SD_CRC16_ERR 0x40 478 #define SD_CRC16_ERR 0x40
468 #define SD_CRC_WRITE_ERR 0x20 479 #define SD_CRC_WRITE_ERR 0x20
469 #define SD_CRC_WRITE_ERR_MASK 0x1C 480 #define SD_CRC_WRITE_ERR_MASK 0x1C
470 #define GET_CRC_TIME_OUT 0x02 481 #define GET_CRC_TIME_OUT 0x02
471 #define SD_TUNING_COMPARE_ERR 0x01 482 #define SD_TUNING_COMPARE_ERR 0x01
472 483
473 /* SD_DATA_STATE */ 484 /* SD_DATA_STATE */
474 #define SD_DATA_IDLE 0x80 485 #define SD_DATA_IDLE 0x80
475 486
476 /* CARD_DATA_SOURCE */ 487 /* CARD_DATA_SOURCE */
477 #define PINGPONG_BUFFER 0x01 488 #define PINGPONG_BUFFER 0x01
478 #define RING_BUFFER 0x00 489 #define RING_BUFFER 0x00
479 490
480 /* CARD_OE */ 491 /* CARD_OE */
481 #define SD_OUTPUT_EN 0x04 492 #define SD_OUTPUT_EN 0x04
482 #define MS_OUTPUT_EN 0x08 493 #define MS_OUTPUT_EN 0x08
483 494
484 /* CARD_STOP */ 495 /* CARD_STOP */
485 #define SD_STOP 0x04 496 #define SD_STOP 0x04
486 #define MS_STOP 0x08 497 #define MS_STOP 0x08
487 #define SD_CLR_ERR 0x40 498 #define SD_CLR_ERR 0x40
488 #define MS_CLR_ERR 0x80 499 #define MS_CLR_ERR 0x80
489 500
490 /* CARD_CLK_SOURCE */ 501 /* CARD_CLK_SOURCE */
491 #define CRC_FIX_CLK (0x00 502 #define CRC_FIX_CLK (0x00 << 0)
492 #define CRC_VAR_CLK0 (0x01 503 #define CRC_VAR_CLK0 (0x01 << 0)
493 #define CRC_VAR_CLK1 (0x02 504 #define CRC_VAR_CLK1 (0x02 << 0)
494 #define SD30_FIX_CLK (0x00 505 #define SD30_FIX_CLK (0x00 << 2)
495 #define SD30_VAR_CLK0 (0x01 506 #define SD30_VAR_CLK0 (0x01 << 2)
496 #define SD30_VAR_CLK1 (0x02 507 #define SD30_VAR_CLK1 (0x02 << 2)
497 #define SAMPLE_FIX_CLK (0x00 508 #define SAMPLE_FIX_CLK (0x00 << 4)
498 #define SAMPLE_VAR_CLK0 (0x01 509 #define SAMPLE_VAR_CLK0 (0x01 << 4)
499 #define SAMPLE_VAR_CLK1 (0x02 510 #define SAMPLE_VAR_CLK1 (0x02 << 4)
500 511
501 /* SD_SAMPLE_POINT_CTL */ 512 /* SD_SAMPLE_POINT_CTL */
502 #define DDR_FIX_RX_DAT 0x00 513 #define DDR_FIX_RX_DAT 0x00
503 #define DDR_VAR_RX_DAT 0x80 514 #define DDR_VAR_RX_DAT 0x80
504 #define DDR_FIX_RX_DAT_EDGE 0x00 515 #define DDR_FIX_RX_DAT_EDGE 0x00
505 #define DDR_FIX_RX_DAT_14_DELAY 0x40 516 #define DDR_FIX_RX_DAT_14_DELAY 0x40
506 #define DDR_FIX_RX_CMD 0x00 517 #define DDR_FIX_RX_CMD 0x00
507 #define DDR_VAR_RX_CMD 0x20 518 #define DDR_VAR_RX_CMD 0x20
508 #define DDR_FIX_RX_CMD_POS_EDGE 0x00 519 #define DDR_FIX_RX_CMD_POS_EDGE 0x00
509 #define DDR_FIX_RX_CMD_14_DELAY 0x10 520 #define DDR_FIX_RX_CMD_14_DELAY 0x10
510 #define SD20_RX_POS_EDGE 0x00 521 #define SD20_RX_POS_EDGE 0x00
511 #define SD20_RX_14_DELAY 0x08 522 #define SD20_RX_14_DELAY 0x08
512 #define SD20_RX_SEL_MASK 0x08 523 #define SD20_RX_SEL_MASK 0x08
513 524
514 /* SD_PUSH_POINT_CTL */ 525 /* SD_PUSH_POINT_CTL */
515 #define DDR_FIX_TX_CMD_DAT 0x00 526 #define DDR_FIX_TX_CMD_DAT 0x00
516 #define DDR_VAR_TX_CMD_DAT 0x80 527 #define DDR_VAR_TX_CMD_DAT 0x80
517 #define DDR_FIX_TX_DAT_14_TSU 0x00 528 #define DDR_FIX_TX_DAT_14_TSU 0x00
518 #define DDR_FIX_TX_DAT_12_TSU 0x40 529 #define DDR_FIX_TX_DAT_12_TSU 0x40
519 #define DDR_FIX_TX_CMD_NEG_EDGE 0x00 530 #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
520 #define DDR_FIX_TX_CMD_14_AHEAD 0x20 531 #define DDR_FIX_TX_CMD_14_AHEAD 0x20
521 #define SD20_TX_NEG_EDGE 0x00 532 #define SD20_TX_NEG_EDGE 0x00
522 #define SD20_TX_14_AHEAD 0x10 533 #define SD20_TX_14_AHEAD 0x10
523 #define SD20_TX_SEL_MASK 0x10 534 #define SD20_TX_SEL_MASK 0x10
524 #define DDR_VAR_SDCLK_POL_SWAP 0x01 535 #define DDR_VAR_SDCLK_POL_SWAP 0x01
525 536
526 /* MS_CFG */ 537 /* MS_CFG */
527 #define SAMPLE_TIME_RISING 0x00 538 #define SAMPLE_TIME_RISING 0x00
528 #define SAMPLE_TIME_FALLING 0x80 539 #define SAMPLE_TIME_FALLING 0x80
529 #define PUSH_TIME_DEFAULT 0x00 540 #define PUSH_TIME_DEFAULT 0x00
530 #define PUSH_TIME_ODD 0x40 541 #define PUSH_TIME_ODD 0x40
531 #define NO_EXTEND_TOGGLE 0x00 542 #define NO_EXTEND_TOGGLE 0x00
532 #define EXTEND_TOGGLE_CHK 0x20 543 #define EXTEND_TOGGLE_CHK 0x20
533 #define MS_BUS_WIDTH_1 0x00 544 #define MS_BUS_WIDTH_1 0x00
534 #define MS_BUS_WIDTH_4 0x10 545 #define MS_BUS_WIDTH_4 0x10
535 #define MS_BUS_WIDTH_8 0x18 546 #define MS_BUS_WIDTH_8 0x18
536 #define MS_2K_SECTOR_MODE 0x04 547 #define MS_2K_SECTOR_MODE 0x04
537 #define MS_512_SECTOR_MODE 0x00 548 #define MS_512_SECTOR_MODE 0x00
538 #define MS_TOGGLE_TIMEOUT_EN 0x00 549 #define MS_TOGGLE_TIMEOUT_EN 0x00
539 #define MS_TOGGLE_TIMEOUT_DISEN 0x01 550 #define MS_TOGGLE_TIMEOUT_DISEN 0x01
540 #define MS_NO_CHECK_INT 0x02 551 #define MS_NO_CHECK_INT 0x02
541 552
542 /* MS_TRANS_CFG */ 553 /* MS_TRANS_CFG */
543 #define WAIT_INT 0x80 554 #define WAIT_INT 0x80
544 #define NO_WAIT_INT 0x00 555 #define NO_WAIT_INT 0x00
545 #define NO_AUTO_READ_INT_REG 0x00 556 #define NO_AUTO_READ_INT_REG 0x00
546 #define AUTO_READ_INT_REG 0x40 557 #define AUTO_READ_INT_REG 0x40
547 #define MS_CRC16_ERR 0x20 558 #define MS_CRC16_ERR 0x20
548 #define MS_RDY_TIMEOUT 0x10 559 #define MS_RDY_TIMEOUT 0x10
549 #define MS_INT_CMDNK 0x08 560 #define MS_INT_CMDNK 0x08
550 #define MS_INT_BREQ 0x04 561 #define MS_INT_BREQ 0x04
551 #define MS_INT_ERR 0x02 562 #define MS_INT_ERR 0x02
552 #define MS_INT_CED 0x01 563 #define MS_INT_CED 0x01
553 564
554 /* MS_TRANSFER */ 565 /* MS_TRANSFER */
555 #define MS_TRANSFER_START 0x80 566 #define MS_TRANSFER_START 0x80
556 #define MS_TRANSFER_END 0x40 567 #define MS_TRANSFER_END 0x40
557 #define MS_TRANSFER_ERR 0x20 568 #define MS_TRANSFER_ERR 0x20
558 #define MS_BS_STATE 0x10 569 #define MS_BS_STATE 0x10
559 #define MS_TM_READ_BYTES 0x00 570 #define MS_TM_READ_BYTES 0x00
560 #define MS_TM_NORMAL_READ 0x01 571 #define MS_TM_NORMAL_READ 0x01
561 #define MS_TM_WRITE_BYTES 0x04 572 #define MS_TM_WRITE_BYTES 0x04
562 #define MS_TM_NORMAL_WRITE 0x05 573 #define MS_TM_NORMAL_WRITE 0x05
563 #define MS_TM_AUTO_READ 0x08 574 #define MS_TM_AUTO_READ 0x08
564 #define MS_TM_AUTO_WRITE 0x0C 575 #define MS_TM_AUTO_WRITE 0x0C
565 #define MS_TM_SET_CMD 0x06 576 #define MS_TM_SET_CMD 0x06
566 #define MS_TM_COPY_PAGE 0x07 577 #define MS_TM_COPY_PAGE 0x07
567 #define MS_TM_MULTI_READ 0x02 578 #define MS_TM_MULTI_READ 0x02
568 #define MS_TM_MULTI_WRITE 0x03 579 #define MS_TM_MULTI_WRITE 0x03
569 580
570 /* MC_FIFO_CTL */ 581 /* MC_FIFO_CTL */
571 #define FIFO_FLUSH 0x01 582 #define FIFO_FLUSH 0x01
572 583
573 /* MC_DMA_RST */ 584 /* MC_DMA_RST */
574 #define DMA_RESET 0x01 585 #define DMA_RESET 0x01
575 586
576 /* MC_DMA_CTL */ 587 /* MC_DMA_CTL */
577 #define DMA_TC_EQ_0 0x80 588 #define DMA_TC_EQ_0 0x80
578 #define DMA_DIR_TO_CARD 0x00 589 #define DMA_DIR_TO_CARD 0x00
579 #define DMA_DIR_FROM_CARD 0x02 590 #define DMA_DIR_FROM_CARD 0x02
580 #define DMA_EN 0x01 591 #define DMA_EN 0x01
581 #define DMA_128 (0 << 592 #define DMA_128 (0 << 2)
582 #define DMA_256 (1 << 593 #define DMA_256 (1 << 2)
583 #define DMA_512 (2 << 594 #define DMA_512 (2 << 2)
584 #define DMA_1024 (3 << 595 #define DMA_1024 (3 << 2)
585 #define DMA_PACK_SIZE_MASK 0x0C 596 #define DMA_PACK_SIZE_MASK 0x0C
586 597
587 /* CARD_INT_PEND */ 598 /* CARD_INT_PEND */
588 #define XD_INT 0x10 599 #define XD_INT 0x10
589 #define MS_INT 0x08 600 #define MS_INT 0x08
590 #define SD_INT 0x04 601 #define SD_INT 0x04
591 602
592 /* LED operations*/ 603 /* LED operations*/
593 static inline int rtsx_usb_turn_on_led(struct 604 static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
594 { 605 {
595 return rtsx_usb_ep0_write_register(uc 606 return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
596 } 607 }
597 608
598 static inline int rtsx_usb_turn_off_led(struct 609 static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
599 { 610 {
600 return rtsx_usb_ep0_write_register(ucr 611 return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
601 } 612 }
602 613
603 /* HW error clearing */ 614 /* HW error clearing */
604 static inline void rtsx_usb_clear_fsm_err(stru 615 static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
605 { 616 {
606 rtsx_usb_ep0_write_register(ucr, SFSM_ 617 rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
607 } 618 }
608 619
609 static inline void rtsx_usb_clear_dma_err(stru 620 static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
610 { 621 {
611 rtsx_usb_ep0_write_register(ucr, MC_FI 622 rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
612 FIFO_FLUSH, FIFO_FLUSH 623 FIFO_FLUSH, FIFO_FLUSH);
613 rtsx_usb_ep0_write_register(ucr, MC_DM 624 rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
614 } 625 }
615 #endif /* __RTS51139_H */ 626 #endif /* __RTS51139_H */
616 627
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