1 /* SPDX-License-Identifier: GPL-2.0+ */ <<
2 /* 1 /*
3 * Internal header file for Samsung S3C2410 s 2 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
4 * 3 *
5 * Copyright (C) 2002 Shane Nay (shane@minirl 4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * 5 *
7 * Additional defines, Copyright 2003 Simtec 6 * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
8 * 7 *
9 * Adapted from: 8 * Adapted from:
10 * 9 *
11 * Internal header file for MX1ADS serial por 10 * Internal header file for MX1ADS serial ports (UART1 & 2)
12 * 11 *
13 * Copyright (C) 2002 Shane Nay (shane@minirl 12 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
14 */ !! 13 *
>> 14 * This program is free software; you can redistribute it and/or modify
>> 15 * it under the terms of the GNU General Public License as published by
>> 16 * the Free Software Foundation; either version 2 of the License, or
>> 17 * (at your option) any later version.
>> 18 *
>> 19 * This program is distributed in the hope that it will be useful,
>> 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 22 * GNU General Public License for more details.
>> 23 *
>> 24 * You should have received a copy of the GNU General Public License
>> 25 * along with this program; if not, write to the Free Software
>> 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> 27 */
15 28
16 #ifndef __ASM_ARM_REGS_SERIAL_H 29 #ifndef __ASM_ARM_REGS_SERIAL_H
17 #define __ASM_ARM_REGS_SERIAL_H 30 #define __ASM_ARM_REGS_SERIAL_H
18 31
19 #define S3C2410_URXH (0x24) 32 #define S3C2410_URXH (0x24)
20 #define S3C2410_UTXH (0x20) 33 #define S3C2410_UTXH (0x20)
21 #define S3C2410_ULCON (0x00) 34 #define S3C2410_ULCON (0x00)
22 #define S3C2410_UCON (0x04) 35 #define S3C2410_UCON (0x04)
23 #define S3C2410_UFCON (0x08) 36 #define S3C2410_UFCON (0x08)
24 #define S3C2410_UMCON (0x0C) 37 #define S3C2410_UMCON (0x0C)
25 #define S3C2410_UBRDIV (0x28) 38 #define S3C2410_UBRDIV (0x28)
26 #define S3C2410_UTRSTAT (0x10) 39 #define S3C2410_UTRSTAT (0x10)
27 #define S3C2410_UERSTAT (0x14) 40 #define S3C2410_UERSTAT (0x14)
28 #define S3C2410_UFSTAT (0x18) 41 #define S3C2410_UFSTAT (0x18)
29 #define S3C2410_UMSTAT (0x1C) 42 #define S3C2410_UMSTAT (0x1C)
30 43
31 #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0 44 #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
32 45
33 #define S3C2410_LCON_CS5 (0x0) 46 #define S3C2410_LCON_CS5 (0x0)
34 #define S3C2410_LCON_CS6 (0x1) 47 #define S3C2410_LCON_CS6 (0x1)
35 #define S3C2410_LCON_CS7 (0x2) 48 #define S3C2410_LCON_CS7 (0x2)
36 #define S3C2410_LCON_CS8 (0x3) 49 #define S3C2410_LCON_CS8 (0x3)
37 #define S3C2410_LCON_CSMASK (0x3) 50 #define S3C2410_LCON_CSMASK (0x3)
38 51
39 #define S3C2410_LCON_PNONE (0x0) 52 #define S3C2410_LCON_PNONE (0x0)
40 #define S3C2410_LCON_PEVEN (0x5 << 3) 53 #define S3C2410_LCON_PEVEN (0x5 << 3)
41 #define S3C2410_LCON_PODD (0x4 << 3) 54 #define S3C2410_LCON_PODD (0x4 << 3)
42 #define S3C2410_LCON_PMASK (0x7 << 3) 55 #define S3C2410_LCON_PMASK (0x7 << 3)
43 56
44 #define S3C2410_LCON_STOPB (1<<2) 57 #define S3C2410_LCON_STOPB (1<<2)
45 #define S3C2410_LCON_IRM (1<<6) 58 #define S3C2410_LCON_IRM (1<<6)
46 59
47 #define S3C2440_UCON_CLKMASK (3<<10) 60 #define S3C2440_UCON_CLKMASK (3<<10)
48 #define S3C2440_UCON_CLKSHIFT (10) 61 #define S3C2440_UCON_CLKSHIFT (10)
49 #define S3C2440_UCON_PCLK (0<<10) 62 #define S3C2440_UCON_PCLK (0<<10)
50 #define S3C2440_UCON_UCLK (1<<10) 63 #define S3C2440_UCON_UCLK (1<<10)
51 #define S3C2440_UCON_PCLK2 (2<<10) 64 #define S3C2440_UCON_PCLK2 (2<<10)
52 #define S3C2440_UCON_FCLK (3<<10) 65 #define S3C2440_UCON_FCLK (3<<10)
53 #define S3C2443_UCON_EPLL (3<<10) 66 #define S3C2443_UCON_EPLL (3<<10)
54 67
55 #define S3C6400_UCON_CLKMASK (3<<10) 68 #define S3C6400_UCON_CLKMASK (3<<10)
56 #define S3C6400_UCON_CLKSHIFT (10) 69 #define S3C6400_UCON_CLKSHIFT (10)
57 #define S3C6400_UCON_PCLK (0<<10) 70 #define S3C6400_UCON_PCLK (0<<10)
58 #define S3C6400_UCON_PCLK2 (2<<10) 71 #define S3C6400_UCON_PCLK2 (2<<10)
59 #define S3C6400_UCON_UCLK0 (1<<10) 72 #define S3C6400_UCON_UCLK0 (1<<10)
60 #define S3C6400_UCON_UCLK1 (3<<10) 73 #define S3C6400_UCON_UCLK1 (3<<10)
61 74
62 #define S3C2440_UCON2_FCLK_EN (1<<15) 75 #define S3C2440_UCON2_FCLK_EN (1<<15)
63 #define S3C2440_UCON0_DIVMASK (15 << 12) 76 #define S3C2440_UCON0_DIVMASK (15 << 12)
64 #define S3C2440_UCON1_DIVMASK (15 << 12) 77 #define S3C2440_UCON1_DIVMASK (15 << 12)
65 #define S3C2440_UCON2_DIVMASK (7 << 12) 78 #define S3C2440_UCON2_DIVMASK (7 << 12)
66 #define S3C2440_UCON_DIVSHIFT (12) 79 #define S3C2440_UCON_DIVSHIFT (12)
67 80
68 #define S3C2412_UCON_CLKMASK (3<<10) 81 #define S3C2412_UCON_CLKMASK (3<<10)
69 #define S3C2412_UCON_CLKSHIFT (10) 82 #define S3C2412_UCON_CLKSHIFT (10)
70 #define S3C2412_UCON_UCLK (1<<10) 83 #define S3C2412_UCON_UCLK (1<<10)
71 #define S3C2412_UCON_USYSCLK (3<<10) 84 #define S3C2412_UCON_USYSCLK (3<<10)
72 #define S3C2412_UCON_PCLK (0<<10) 85 #define S3C2412_UCON_PCLK (0<<10)
73 #define S3C2412_UCON_PCLK2 (2<<10) 86 #define S3C2412_UCON_PCLK2 (2<<10)
74 87
75 #define S3C2410_UCON_CLKMASK (1 << 10) 88 #define S3C2410_UCON_CLKMASK (1 << 10)
76 #define S3C2410_UCON_CLKSHIFT (10) 89 #define S3C2410_UCON_CLKSHIFT (10)
77 #define S3C2410_UCON_UCLK (1<<10) 90 #define S3C2410_UCON_UCLK (1<<10)
78 #define S3C2410_UCON_SBREAK (1<<4) 91 #define S3C2410_UCON_SBREAK (1<<4)
79 92
80 #define S3C2410_UCON_TXILEVEL (1<<9) 93 #define S3C2410_UCON_TXILEVEL (1<<9)
81 #define S3C2410_UCON_RXILEVEL (1<<8) 94 #define S3C2410_UCON_RXILEVEL (1<<8)
82 #define S3C2410_UCON_TXIRQMODE (1<<2) 95 #define S3C2410_UCON_TXIRQMODE (1<<2)
83 #define S3C2410_UCON_RXIRQMODE (1<<0) 96 #define S3C2410_UCON_RXIRQMODE (1<<0)
84 #define S3C2410_UCON_RXFIFO_TOI (1<<7) 97 #define S3C2410_UCON_RXFIFO_TOI (1<<7)
85 #define S3C2443_UCON_RXERR_IRQEN (1<<6) 98 #define S3C2443_UCON_RXERR_IRQEN (1<<6)
86 #define S3C2410_UCON_LOOPBACK (1<<5) !! 99 #define S3C2443_UCON_LOOPBACK (1<<5)
87 100
88 #define S3C2410_UCON_DEFAULT (S3C2410_UCO 101 #define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
89 S3C2410_UCO 102 S3C2410_UCON_RXILEVEL | \
90 S3C2410_UCO 103 S3C2410_UCON_TXIRQMODE | \
91 S3C2410_UCO 104 S3C2410_UCON_RXIRQMODE | \
92 S3C2410_UCO 105 S3C2410_UCON_RXFIFO_TOI)
93 106
94 #define S3C64XX_UCON_TXBURST_1 (0<<20 <<
95 #define S3C64XX_UCON_TXBURST_4 (1<<20 <<
96 #define S3C64XX_UCON_TXBURST_8 (2<<20 <<
97 #define S3C64XX_UCON_TXBURST_16 (3<<20 <<
98 #define S3C64XX_UCON_TXBURST_MASK (0xf<< <<
99 #define S3C64XX_UCON_RXBURST_1 (0<<16 <<
100 #define S3C64XX_UCON_RXBURST_4 (1<<16 <<
101 #define S3C64XX_UCON_RXBURST_8 (2<<16 <<
102 #define S3C64XX_UCON_RXBURST_16 (3<<16 <<
103 #define S3C64XX_UCON_RXBURST_MASK (0xf<< <<
104 #define S3C64XX_UCON_TIMEOUT_SHIFT (12) <<
105 #define S3C64XX_UCON_TIMEOUT_MASK (0xf<< <<
106 #define S3C64XX_UCON_EMPTYINT_EN (1<<11 <<
107 #define S3C64XX_UCON_DMASUS_EN (1<<10 <<
108 #define S3C64XX_UCON_TXINT_LEVEL (1<<9) <<
109 #define S3C64XX_UCON_RXINT_LEVEL (1<<8) <<
110 #define S3C64XX_UCON_TIMEOUT_EN (1<<7) <<
111 #define S3C64XX_UCON_ERRINT_EN (1<<6) <<
112 #define S3C64XX_UCON_TXMODE_DMA (2<<2) <<
113 #define S3C64XX_UCON_TXMODE_CPU (1<<2) <<
114 #define S3C64XX_UCON_TXMODE_MASK (3<<2) <<
115 #define S3C64XX_UCON_RXMODE_DMA (2<<0) <<
116 #define S3C64XX_UCON_RXMODE_CPU (1<<0) <<
117 #define S3C64XX_UCON_RXMODE_MASK (3<<0) <<
118 <<
119 #define S3C2410_UFCON_FIFOMODE (1<<0) 107 #define S3C2410_UFCON_FIFOMODE (1<<0)
120 #define S3C2410_UFCON_TXTRIG0 (0<<6) 108 #define S3C2410_UFCON_TXTRIG0 (0<<6)
121 #define S3C2410_UFCON_RXTRIG8 (1<<4) 109 #define S3C2410_UFCON_RXTRIG8 (1<<4)
122 #define S3C2410_UFCON_RXTRIG12 (2<<4) 110 #define S3C2410_UFCON_RXTRIG12 (2<<4)
123 111
124 /* S3C2440 FIFO trigger levels */ 112 /* S3C2440 FIFO trigger levels */
125 #define S3C2440_UFCON_RXTRIG1 (0<<4) 113 #define S3C2440_UFCON_RXTRIG1 (0<<4)
126 #define S3C2440_UFCON_RXTRIG8 (1<<4) 114 #define S3C2440_UFCON_RXTRIG8 (1<<4)
127 #define S3C2440_UFCON_RXTRIG16 (2<<4) 115 #define S3C2440_UFCON_RXTRIG16 (2<<4)
128 #define S3C2440_UFCON_RXTRIG32 (3<<4) 116 #define S3C2440_UFCON_RXTRIG32 (3<<4)
129 117
130 #define S3C2440_UFCON_TXTRIG0 (0<<6) 118 #define S3C2440_UFCON_TXTRIG0 (0<<6)
131 #define S3C2440_UFCON_TXTRIG16 (1<<6) 119 #define S3C2440_UFCON_TXTRIG16 (1<<6)
132 #define S3C2440_UFCON_TXTRIG32 (2<<6) 120 #define S3C2440_UFCON_TXTRIG32 (2<<6)
133 #define S3C2440_UFCON_TXTRIG48 (3<<6) 121 #define S3C2440_UFCON_TXTRIG48 (3<<6)
134 122
135 #define S3C2410_UFCON_RESETBOTH (3<<1) 123 #define S3C2410_UFCON_RESETBOTH (3<<1)
136 #define S3C2410_UFCON_RESETTX (1<<2) 124 #define S3C2410_UFCON_RESETTX (1<<2)
137 #define S3C2410_UFCON_RESETRX (1<<1) 125 #define S3C2410_UFCON_RESETRX (1<<1)
138 126
139 #define S3C2410_UFCON_DEFAULT (S3C2410_UFC 127 #define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
140 S3C2410_UFC 128 S3C2410_UFCON_TXTRIG0 | \
141 S3C2410_UFC 129 S3C2410_UFCON_RXTRIG8 )
142 130
143 #define S3C2410_UMCOM_AFC (1<<4) 131 #define S3C2410_UMCOM_AFC (1<<4)
144 #define S3C2410_UMCOM_RTS_LOW (1<<0) 132 #define S3C2410_UMCOM_RTS_LOW (1<<0)
145 133
146 #define S3C2412_UMCON_AFC_63 (0<<5) 134 #define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
147 #define S3C2412_UMCON_AFC_56 (1<<5) 135 #define S3C2412_UMCON_AFC_56 (1<<5)
148 #define S3C2412_UMCON_AFC_48 (2<<5) 136 #define S3C2412_UMCON_AFC_48 (2<<5)
149 #define S3C2412_UMCON_AFC_40 (3<<5) 137 #define S3C2412_UMCON_AFC_40 (3<<5)
150 #define S3C2412_UMCON_AFC_32 (4<<5) 138 #define S3C2412_UMCON_AFC_32 (4<<5)
151 #define S3C2412_UMCON_AFC_24 (5<<5) 139 #define S3C2412_UMCON_AFC_24 (5<<5)
152 #define S3C2412_UMCON_AFC_16 (6<<5) 140 #define S3C2412_UMCON_AFC_16 (6<<5)
153 #define S3C2412_UMCON_AFC_8 (7<<5) 141 #define S3C2412_UMCON_AFC_8 (7<<5)
154 142
155 #define S3C2410_UFSTAT_TXFULL (1<<9) 143 #define S3C2410_UFSTAT_TXFULL (1<<9)
156 #define S3C2410_UFSTAT_RXFULL (1<<8) 144 #define S3C2410_UFSTAT_RXFULL (1<<8)
157 #define S3C2410_UFSTAT_TXMASK (15<<4) 145 #define S3C2410_UFSTAT_TXMASK (15<<4)
158 #define S3C2410_UFSTAT_TXSHIFT (4) 146 #define S3C2410_UFSTAT_TXSHIFT (4)
159 #define S3C2410_UFSTAT_RXMASK (15<<0) 147 #define S3C2410_UFSTAT_RXMASK (15<<0)
160 #define S3C2410_UFSTAT_RXSHIFT (0) 148 #define S3C2410_UFSTAT_RXSHIFT (0)
161 149
162 /* UFSTAT S3C2443 same as S3C2440 */ 150 /* UFSTAT S3C2443 same as S3C2440 */
163 #define S3C2440_UFSTAT_TXFULL (1<<14) 151 #define S3C2440_UFSTAT_TXFULL (1<<14)
164 #define S3C2440_UFSTAT_RXFULL (1<<6) 152 #define S3C2440_UFSTAT_RXFULL (1<<6)
165 #define S3C2440_UFSTAT_TXSHIFT (8) 153 #define S3C2440_UFSTAT_TXSHIFT (8)
166 #define S3C2440_UFSTAT_RXSHIFT (0) 154 #define S3C2440_UFSTAT_RXSHIFT (0)
167 #define S3C2440_UFSTAT_TXMASK (63<<8) 155 #define S3C2440_UFSTAT_TXMASK (63<<8)
168 #define S3C2440_UFSTAT_RXMASK (63) 156 #define S3C2440_UFSTAT_RXMASK (63)
169 157
170 #define S3C2410_UTRSTAT_TIMEOUT (1<<3) <<
171 #define S3C2410_UTRSTAT_TXE (1<<2) 158 #define S3C2410_UTRSTAT_TXE (1<<2)
172 #define S3C2410_UTRSTAT_TXFE (1<<1) 159 #define S3C2410_UTRSTAT_TXFE (1<<1)
173 #define S3C2410_UTRSTAT_RXDR (1<<0) 160 #define S3C2410_UTRSTAT_RXDR (1<<0)
174 161
175 #define S3C2410_UERSTAT_OVERRUN (1<<0) 162 #define S3C2410_UERSTAT_OVERRUN (1<<0)
176 #define S3C2410_UERSTAT_FRAME (1<<2) 163 #define S3C2410_UERSTAT_FRAME (1<<2)
177 #define S3C2410_UERSTAT_BREAK (1<<3) 164 #define S3C2410_UERSTAT_BREAK (1<<3)
178 #define S3C2443_UERSTAT_PARITY (1<<1) 165 #define S3C2443_UERSTAT_PARITY (1<<1)
179 166
180 #define S3C2410_UERSTAT_ANY (S3C2410_UER 167 #define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
181 S3C2410_UER 168 S3C2410_UERSTAT_FRAME | \
182 S3C2410_UER 169 S3C2410_UERSTAT_BREAK)
183 170
184 #define S3C2410_UMSTAT_CTS (1<<0) 171 #define S3C2410_UMSTAT_CTS (1<<0)
185 #define S3C2410_UMSTAT_DeltaCTS (1<<2) 172 #define S3C2410_UMSTAT_DeltaCTS (1<<2)
186 173
187 #define S3C2443_DIVSLOT (0x2C) 174 #define S3C2443_DIVSLOT (0x2C)
188 175
189 /* S3C64XX interrupt registers. */ 176 /* S3C64XX interrupt registers. */
190 #define S3C64XX_UINTP 0x30 177 #define S3C64XX_UINTP 0x30
191 #define S3C64XX_UINTSP 0x34 178 #define S3C64XX_UINTSP 0x34
192 #define S3C64XX_UINTM 0x38 179 #define S3C64XX_UINTM 0x38
193 180
194 #define S3C64XX_UINTM_RXD (0) 181 #define S3C64XX_UINTM_RXD (0)
195 #define S3C64XX_UINTM_ERROR (1) <<
196 #define S3C64XX_UINTM_TXD (2) 182 #define S3C64XX_UINTM_TXD (2)
197 #define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_ 183 #define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
198 #define S3C64XX_UINTM_ERR_MSK (1 << S3C64XX_ <<
199 #define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_ 184 #define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
200 185
201 /* Following are specific to S5PV210 */ 186 /* Following are specific to S5PV210 */
202 #define S5PV210_UCON_CLKMASK (1<<10) 187 #define S5PV210_UCON_CLKMASK (1<<10)
203 #define S5PV210_UCON_CLKSHIFT (10) 188 #define S5PV210_UCON_CLKSHIFT (10)
204 #define S5PV210_UCON_PCLK (0<<10) 189 #define S5PV210_UCON_PCLK (0<<10)
205 #define S5PV210_UCON_UCLK (1<<10) 190 #define S5PV210_UCON_UCLK (1<<10)
206 191
207 #define S5PV210_UFCON_TXTRIG0 (0<<8) 192 #define S5PV210_UFCON_TXTRIG0 (0<<8)
208 #define S5PV210_UFCON_TXTRIG4 (1<<8) 193 #define S5PV210_UFCON_TXTRIG4 (1<<8)
209 #define S5PV210_UFCON_TXTRIG8 (2<<8) 194 #define S5PV210_UFCON_TXTRIG8 (2<<8)
210 #define S5PV210_UFCON_TXTRIG16 (3<<8) 195 #define S5PV210_UFCON_TXTRIG16 (3<<8)
211 #define S5PV210_UFCON_TXTRIG32 (4<<8) 196 #define S5PV210_UFCON_TXTRIG32 (4<<8)
212 #define S5PV210_UFCON_TXTRIG64 (5<<8) 197 #define S5PV210_UFCON_TXTRIG64 (5<<8)
213 #define S5PV210_UFCON_TXTRIG128 (6<<8) 198 #define S5PV210_UFCON_TXTRIG128 (6<<8)
214 #define S5PV210_UFCON_TXTRIG256 (7<<8) 199 #define S5PV210_UFCON_TXTRIG256 (7<<8)
215 200
216 #define S5PV210_UFCON_RXTRIG1 (0<<4) 201 #define S5PV210_UFCON_RXTRIG1 (0<<4)
217 #define S5PV210_UFCON_RXTRIG4 (1<<4) 202 #define S5PV210_UFCON_RXTRIG4 (1<<4)
218 #define S5PV210_UFCON_RXTRIG8 (2<<4) 203 #define S5PV210_UFCON_RXTRIG8 (2<<4)
219 #define S5PV210_UFCON_RXTRIG16 (3<<4) 204 #define S5PV210_UFCON_RXTRIG16 (3<<4)
220 #define S5PV210_UFCON_RXTRIG32 (4<<4) 205 #define S5PV210_UFCON_RXTRIG32 (4<<4)
221 #define S5PV210_UFCON_RXTRIG64 (5<<4) 206 #define S5PV210_UFCON_RXTRIG64 (5<<4)
222 #define S5PV210_UFCON_RXTRIG128 (6<<4) 207 #define S5PV210_UFCON_RXTRIG128 (6<<4)
223 #define S5PV210_UFCON_RXTRIG256 (7<<4) 208 #define S5PV210_UFCON_RXTRIG256 (7<<4)
224 209
225 #define S5PV210_UFSTAT_TXFULL (1<<24) 210 #define S5PV210_UFSTAT_TXFULL (1<<24)
226 #define S5PV210_UFSTAT_RXFULL (1<<8) 211 #define S5PV210_UFSTAT_RXFULL (1<<8)
227 #define S5PV210_UFSTAT_TXMASK (255<<16) 212 #define S5PV210_UFSTAT_TXMASK (255<<16)
228 #define S5PV210_UFSTAT_TXSHIFT (16) 213 #define S5PV210_UFSTAT_TXSHIFT (16)
229 #define S5PV210_UFSTAT_RXMASK (255<<0) 214 #define S5PV210_UFSTAT_RXMASK (255<<0)
230 #define S5PV210_UFSTAT_RXSHIFT (0) 215 #define S5PV210_UFSTAT_RXSHIFT (0)
231 216
232 #define S3C2410_UCON_CLKSEL0 (1 << 0) 217 #define S3C2410_UCON_CLKSEL0 (1 << 0)
233 #define S3C2410_UCON_CLKSEL1 (1 << 1) 218 #define S3C2410_UCON_CLKSEL1 (1 << 1)
234 #define S3C2410_UCON_CLKSEL2 (1 << 2) 219 #define S3C2410_UCON_CLKSEL2 (1 << 2)
235 #define S3C2410_UCON_CLKSEL3 (1 << 3) 220 #define S3C2410_UCON_CLKSEL3 (1 << 3)
236 221
237 /* Default values for s5pv210 UCON and UFCON u 222 /* Default values for s5pv210 UCON and UFCON uart registers */
238 #define S5PV210_UCON_DEFAULT (S3C2410_UCON_ 223 #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
239 S3C2410_UCON_ 224 S3C2410_UCON_RXILEVEL | \
240 S3C2410_UCON_ 225 S3C2410_UCON_TXIRQMODE | \
241 S3C2410_UCON_ 226 S3C2410_UCON_RXIRQMODE | \
242 S3C2410_UCON_ 227 S3C2410_UCON_RXFIFO_TOI | \
243 S3C2443_UCON_ 228 S3C2443_UCON_RXERR_IRQEN)
244 229
245 #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON 230 #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
246 S5PV210_UFCON 231 S5PV210_UFCON_TXTRIG4 | \
247 S5PV210_UFCON 232 S5PV210_UFCON_RXTRIG4)
248 233
249 #define APPLE_S5L_UCON_RXTO_ENA <<
250 #define APPLE_S5L_UCON_RXTO_LEGACY_ENA <<
251 #define APPLE_S5L_UCON_RXTHRESH_ENA <<
252 #define APPLE_S5L_UCON_TXTHRESH_ENA <<
253 #define APPLE_S5L_UCON_RXTO_ENA_MSK <<
254 #define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK <<
255 #define APPLE_S5L_UCON_RXTHRESH_ENA_MSK <<
256 #define APPLE_S5L_UCON_TXTHRESH_ENA_MSK <<
257 <<
258 #define APPLE_S5L_UCON_DEFAULT (S3C24 <<
259 S3C24 <<
260 S3C24 <<
261 #define APPLE_S5L_UCON_MASK (APPLE <<
262 APPLE <<
263 APPLE <<
264 APPLE <<
265 <<
266 #define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3) <<
267 #define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4) <<
268 #define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5) <<
269 #define APPLE_S5L_UTRSTAT_RXTO BIT(9) <<
270 #define APPLE_S5L_UTRSTAT_ALL_FLAGS GENMAS <<
271 <<
272 #ifndef __ASSEMBLY__ 234 #ifndef __ASSEMBLY__
273 235
274 #include <linux/serial_core.h> <<
275 <<
276 /* configuration structure for per-machine con 236 /* configuration structure for per-machine configurations for the
277 * serial port 237 * serial port
278 * 238 *
279 * the pointer is setup by the machine specifi 239 * the pointer is setup by the machine specific initialisation from the
280 * arch/arm/mach-s3c/ directory. !! 240 * arch/arm/mach-s3c2410/ directory.
281 */ 241 */
282 242
283 struct s3c2410_uartcfg { 243 struct s3c2410_uartcfg {
284 unsigned char hwport; /* ha 244 unsigned char hwport; /* hardware port number */
285 unsigned char unused; 245 unsigned char unused;
286 unsigned short flags; 246 unsigned short flags;
287 upf_t uart_flags; /* de 247 upf_t uart_flags; /* default uart flags */
288 unsigned int clk_sel; 248 unsigned int clk_sel;
289 249
290 unsigned int has_fracval; 250 unsigned int has_fracval;
291 251
292 unsigned long ucon; /* va 252 unsigned long ucon; /* value of ucon for port */
293 unsigned long ulcon; /* va 253 unsigned long ulcon; /* value of ulcon for port */
294 unsigned long ufcon; /* va 254 unsigned long ufcon; /* value of ufcon for port */
295 }; 255 };
296 256
297 #endif /* __ASSEMBLY__ */ 257 #endif /* __ASSEMBLY__ */
298 258
299 #endif /* __ASM_ARM_REGS_SERIAL_H */ 259 #endif /* __ASM_ARM_REGS_SERIAL_H */
300 260
301 261
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