1 /* SPDX-License-Identifier: GPL-2.0 */ <<
2 #ifndef __LINUX_SERIAL_SCI_H 1 #ifndef __LINUX_SERIAL_SCI_H
3 #define __LINUX_SERIAL_SCI_H 2 #define __LINUX_SERIAL_SCI_H
4 3
5 #include <linux/bitops.h> <<
6 #include <linux/serial_core.h> 4 #include <linux/serial_core.h>
7 #include <linux/sh_dma.h> 5 #include <linux/sh_dma.h>
8 6
9 /* 7 /*
10 * Generic header for SuperH (H)SCI(F) (used b !! 8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
11 */ 9 */
12 10
13 /* Serial Control Register (@ = not supported !! 11 #define SCIx_NOT_SUPPORTED (-1)
14 #define SCSCR_TIE BIT(7) /* Transmit In <<
15 #define SCSCR_RIE BIT(6) /* Receive Int <<
16 #define SCSCR_TE BIT(5) /* Transmit En <<
17 #define SCSCR_RE BIT(4) /* Receive Ena <<
18 #define SCSCR_REIE BIT(3) /* Receive Err <<
19 #define SCSCR_TOIE BIT(2) /* Timeout Int <<
20 #define SCSCR_CKE1 BIT(1) /* Clock Enabl <<
21 #define SCSCR_CKE0 BIT(0) /* Clock Enabl <<
22 12
>> 13 enum {
>> 14 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
>> 15 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
>> 16 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
>> 17 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
>> 18 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
>> 19 };
>> 20
>> 21 #define SCSCR_TIE (1 << 7)
>> 22 #define SCSCR_RIE (1 << 6)
>> 23 #define SCSCR_TE (1 << 5)
>> 24 #define SCSCR_RE (1 << 4)
>> 25 #define SCSCR_REIE (1 << 3) /* not supported by all parts */
>> 26 #define SCSCR_TOIE (1 << 2) /* not supported by all parts */
>> 27 #define SCSCR_CKE1 (1 << 1)
>> 28 #define SCSCR_CKE0 (1 << 0)
>> 29
>> 30 /* SCxSR SCI */
>> 31 #define SCI_TDRE 0x80
>> 32 #define SCI_RDRF 0x40
>> 33 #define SCI_ORER 0x20
>> 34 #define SCI_FER 0x10
>> 35 #define SCI_PER 0x08
>> 36 #define SCI_TEND 0x04
>> 37
>> 38 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
>> 39
>> 40 /* SCxSR SCIF */
>> 41 #define SCIF_ER 0x0080
>> 42 #define SCIF_TEND 0x0040
>> 43 #define SCIF_TDFE 0x0020
>> 44 #define SCIF_BRK 0x0010
>> 45 #define SCIF_FER 0x0008
>> 46 #define SCIF_PER 0x0004
>> 47 #define SCIF_RDF 0x0002
>> 48 #define SCIF_DR 0x0001
>> 49
>> 50 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
>> 51
>> 52 /* SCSPTR, optional */
>> 53 #define SCSPTR_RTSIO (1 << 7)
>> 54 #define SCSPTR_CTSIO (1 << 5)
>> 55 #define SCSPTR_SPB2IO (1 << 1)
>> 56 #define SCSPTR_SPB2DT (1 << 0)
>> 57
>> 58 /* Offsets into the sci_port->irqs array */
>> 59 enum {
>> 60 SCIx_ERI_IRQ,
>> 61 SCIx_RXI_IRQ,
>> 62 SCIx_TXI_IRQ,
>> 63 SCIx_BRI_IRQ,
>> 64 SCIx_NR_IRQS,
>> 65
>> 66 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
>> 67 };
>> 68
>> 69 /* Offsets into the sci_port->gpios array */
>> 70 enum {
>> 71 SCIx_SCK,
>> 72 SCIx_RXD,
>> 73 SCIx_TXD,
>> 74 SCIx_CTS,
>> 75 SCIx_RTS,
>> 76
>> 77 SCIx_NR_FNS,
>> 78 };
23 79
24 enum { 80 enum {
25 SCIx_PROBE_REGTYPE, 81 SCIx_PROBE_REGTYPE,
26 82
27 SCIx_SCI_REGTYPE, 83 SCIx_SCI_REGTYPE,
28 SCIx_IRDA_REGTYPE, 84 SCIx_IRDA_REGTYPE,
29 SCIx_SCIFA_REGTYPE, 85 SCIx_SCIFA_REGTYPE,
30 SCIx_SCIFB_REGTYPE, 86 SCIx_SCIFB_REGTYPE,
31 SCIx_SH2_SCIF_FIFODATA_REGTYPE, 87 SCIx_SH2_SCIF_FIFODATA_REGTYPE,
32 SCIx_SH3_SCIF_REGTYPE, 88 SCIx_SH3_SCIF_REGTYPE,
33 SCIx_SH4_SCIF_REGTYPE, 89 SCIx_SH4_SCIF_REGTYPE,
34 SCIx_SH4_SCIF_BRG_REGTYPE, <<
35 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 90 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
36 SCIx_SH4_SCIF_FIFODATA_REGTYPE, 91 SCIx_SH4_SCIF_FIFODATA_REGTYPE,
37 SCIx_SH7705_SCIF_REGTYPE, 92 SCIx_SH7705_SCIF_REGTYPE,
38 SCIx_HSCIF_REGTYPE, <<
39 SCIx_RZ_SCIFA_REGTYPE, <<
40 SCIx_RZV2H_SCIF_REGTYPE, <<
41 93
42 SCIx_NR_REGTYPES, 94 SCIx_NR_REGTYPES,
43 }; 95 };
44 96
>> 97 #define SCIx_IRQ_MUXED(irq) \
>> 98 { \
>> 99 [SCIx_ERI_IRQ] = (irq), \
>> 100 [SCIx_RXI_IRQ] = (irq), \
>> 101 [SCIx_TXI_IRQ] = (irq), \
>> 102 [SCIx_BRI_IRQ] = (irq), \
>> 103 }
>> 104
>> 105 #define SCIx_IRQ_IS_MUXED(port) \
>> 106 ((port)->cfg->irqs[SCIx_ERI_IRQ] == \
>> 107 (port)->cfg->irqs[SCIx_RXI_IRQ]) || \
>> 108 ((port)->cfg->irqs[SCIx_ERI_IRQ] && \
>> 109 !(port)->cfg->irqs[SCIx_RXI_IRQ])
>> 110 /*
>> 111 * SCI register subset common for all port types.
>> 112 * Not all registers will exist on all parts.
>> 113 */
>> 114 enum {
>> 115 SCSMR, SCBRR, SCSCR, SCxSR,
>> 116 SCFCR, SCFDR, SCxTDR, SCxRDR,
>> 117 SCLSR, SCTFDR, SCRFDR, SCSPTR,
>> 118
>> 119 SCIx_NR_REGS,
>> 120 };
>> 121
>> 122 struct device;
>> 123
45 struct plat_sci_port_ops { 124 struct plat_sci_port_ops {
46 void (*init_pins)(struct uart_port *, 125 void (*init_pins)(struct uart_port *, unsigned int cflag);
47 }; 126 };
48 127
49 /* 128 /*
>> 129 * Port-specific capabilities
>> 130 */
>> 131 #define SCIx_HAVE_RTSCTS (1 << 0)
>> 132
>> 133 /*
50 * Platform device specific platform_data stru 134 * Platform device specific platform_data struct
51 */ 135 */
52 struct plat_sci_port { 136 struct plat_sci_port {
53 unsigned int type; !! 137 unsigned long mapbase; /* resource base */
>> 138 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
>> 139 unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */
>> 140 unsigned int type; /* SCI / SCIF / IRDA */
54 upf_t flags; 141 upf_t flags; /* UPF_* flags */
>> 142 unsigned long capabilities; /* Port features/capabilities */
55 143
56 unsigned int sampling_rate; !! 144 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
57 unsigned int scscr; 145 unsigned int scscr; /* SCSCR initialization */
58 146
59 /* 147 /*
60 * Platform overrides if necessary, de 148 * Platform overrides if necessary, defaults otherwise.
61 */ 149 */
>> 150 int overrun_bit;
>> 151 unsigned int error_mask;
>> 152
>> 153 int port_reg;
>> 154 unsigned char regshift;
62 unsigned char regtype; 155 unsigned char regtype;
63 156
64 struct plat_sci_port_ops *ops; 157 struct plat_sci_port_ops *ops;
>> 158
>> 159 unsigned int dma_slave_tx;
>> 160 unsigned int dma_slave_rx;
65 }; 161 };
66 162
67 #endif /* __LINUX_SERIAL_SCI_H */ 163 #endif /* __LINUX_SERIAL_SCI_H */
68 164
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