1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_SERIAL_SCI_H 2 #ifndef __LINUX_SERIAL_SCI_H 3 #define __LINUX_SERIAL_SCI_H 3 #define __LINUX_SERIAL_SCI_H 4 4 5 #include <linux/bitops.h> 5 #include <linux/bitops.h> 6 #include <linux/serial_core.h> 6 #include <linux/serial_core.h> 7 #include <linux/sh_dma.h> 7 #include <linux/sh_dma.h> 8 8 9 /* 9 /* 10 * Generic header for SuperH (H)SCI(F) (used b 10 * Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts) 11 */ 11 */ 12 12 13 /* Serial Control Register (@ = not supported 13 /* Serial Control Register (@ = not supported by all parts) */ 14 #define SCSCR_TIE BIT(7) /* Transmit In 14 #define SCSCR_TIE BIT(7) /* Transmit Interrupt Enable */ 15 #define SCSCR_RIE BIT(6) /* Receive Int 15 #define SCSCR_RIE BIT(6) /* Receive Interrupt Enable */ 16 #define SCSCR_TE BIT(5) /* Transmit En 16 #define SCSCR_TE BIT(5) /* Transmit Enable */ 17 #define SCSCR_RE BIT(4) /* Receive Ena 17 #define SCSCR_RE BIT(4) /* Receive Enable */ 18 #define SCSCR_REIE BIT(3) /* Receive Err 18 #define SCSCR_REIE BIT(3) /* Receive Error Interrupt Enable @ */ 19 #define SCSCR_TOIE BIT(2) /* Timeout Int 19 #define SCSCR_TOIE BIT(2) /* Timeout Interrupt Enable @ */ 20 #define SCSCR_CKE1 BIT(1) /* Clock Enabl 20 #define SCSCR_CKE1 BIT(1) /* Clock Enable 1 */ 21 #define SCSCR_CKE0 BIT(0) /* Clock Enabl 21 #define SCSCR_CKE0 BIT(0) /* Clock Enable 0 */ 22 22 23 23 24 enum { 24 enum { 25 SCIx_PROBE_REGTYPE, 25 SCIx_PROBE_REGTYPE, 26 26 27 SCIx_SCI_REGTYPE, 27 SCIx_SCI_REGTYPE, 28 SCIx_IRDA_REGTYPE, 28 SCIx_IRDA_REGTYPE, 29 SCIx_SCIFA_REGTYPE, 29 SCIx_SCIFA_REGTYPE, 30 SCIx_SCIFB_REGTYPE, 30 SCIx_SCIFB_REGTYPE, 31 SCIx_SH2_SCIF_FIFODATA_REGTYPE, 31 SCIx_SH2_SCIF_FIFODATA_REGTYPE, 32 SCIx_SH3_SCIF_REGTYPE, 32 SCIx_SH3_SCIF_REGTYPE, 33 SCIx_SH4_SCIF_REGTYPE, 33 SCIx_SH4_SCIF_REGTYPE, 34 SCIx_SH4_SCIF_BRG_REGTYPE, 34 SCIx_SH4_SCIF_BRG_REGTYPE, 35 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 35 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 36 SCIx_SH4_SCIF_FIFODATA_REGTYPE, 36 SCIx_SH4_SCIF_FIFODATA_REGTYPE, 37 SCIx_SH7705_SCIF_REGTYPE, 37 SCIx_SH7705_SCIF_REGTYPE, 38 SCIx_HSCIF_REGTYPE, 38 SCIx_HSCIF_REGTYPE, 39 SCIx_RZ_SCIFA_REGTYPE, << 40 SCIx_RZV2H_SCIF_REGTYPE, << 41 39 42 SCIx_NR_REGTYPES, 40 SCIx_NR_REGTYPES, 43 }; 41 }; 44 42 45 struct plat_sci_port_ops { 43 struct plat_sci_port_ops { 46 void (*init_pins)(struct uart_port *, 44 void (*init_pins)(struct uart_port *, unsigned int cflag); 47 }; 45 }; 48 46 49 /* 47 /* 50 * Platform device specific platform_data stru 48 * Platform device specific platform_data struct 51 */ 49 */ 52 struct plat_sci_port { 50 struct plat_sci_port { 53 unsigned int type; 51 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ 54 upf_t flags; 52 upf_t flags; /* UPF_* flags */ 55 53 56 unsigned int sampling_rate; 54 unsigned int sampling_rate; 57 unsigned int scscr; 55 unsigned int scscr; /* SCSCR initialization */ 58 56 59 /* 57 /* 60 * Platform overrides if necessary, de 58 * Platform overrides if necessary, defaults otherwise. 61 */ 59 */ 62 unsigned char regtype; 60 unsigned char regtype; 63 61 64 struct plat_sci_port_ops *ops; 62 struct plat_sci_port_ops *ops; 65 }; 63 }; 66 64 67 #endif /* __LINUX_SERIAL_SCI_H */ 65 #endif /* __LINUX_SERIAL_SCI_H */ 68 66
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