1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 #ifndef __SH_CLOCK_H
3 #define __SH_CLOCK_H
4
5 #include <linux/list.h>
6 #include <linux/seq_file.h>
7 #include <linux/cpufreq.h>
8 #include <linux/types.h>
9 #include <linux/kref.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12
13 struct clk;
14
15 struct clk_mapping {
16 phys_addr_t phys;
17 void __iomem *base;
18 unsigned long len;
19 struct kref ref;
20 };
21
22 struct sh_clk_ops {
23 #ifdef CONFIG_SH_CLK_CPG_LEGACY
24 void (*init)(struct clk *clk);
25 #endif
26 int (*enable)(struct clk *clk);
27 void (*disable)(struct clk *clk);
28 unsigned long (*recalc)(struct clk *cl
29 int (*set_rate)(struct clk *clk, unsig
30 int (*set_parent)(struct clk *clk, str
31 long (*round_rate)(struct clk *clk, un
32 };
33
34 #define SH_CLK_DIV_MSK(div) ((1 << (div))
35 #define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK
36 #define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK
37
38 struct clk {
39 struct list_head node;
40 struct clk *parent;
41 struct clk **parent_table
42 unsigned short parent_num;
43 unsigned char src_shift;
44 unsigned char src_width;
45 struct sh_clk_ops *ops;
46
47 struct list_head children;
48 struct list_head sibling;
49
50 int usecount;
51
52 unsigned long rate;
53 unsigned long flags;
54
55 void __iomem *enable_reg;
56 void __iomem *status_reg;
57 unsigned int enable_bit;
58 void __iomem *mapped_reg;
59
60 unsigned int div_mask;
61 unsigned long arch_flags;
62 void *priv;
63 struct clk_mapping *mapping;
64 struct cpufreq_frequency_table *freq_t
65 unsigned int nr_freqs;
66 };
67
68 #define CLK_ENABLE_ON_INIT BIT(0)
69
70 #define CLK_ENABLE_REG_32BIT BIT(1) /* def
71 #define CLK_ENABLE_REG_16BIT BIT(2)
72 #define CLK_ENABLE_REG_8BIT BIT(3)
73
74 #define CLK_MASK_DIV_ON_DISABLE BIT(4)
75
76 #define CLK_ENABLE_REG_MASK (CLK_ENABLE_RE
77 CLK_ENABLE_RE
78 CLK_ENABLE_RE
79
80 /* drivers/sh/clk.c */
81 unsigned long followparent_recalc(struct clk *
82 void recalculate_root_clocks(void);
83 void propagate_rate(struct clk *);
84 int clk_reparent(struct clk *child, struct clk
85 int clk_register(struct clk *);
86 void clk_unregister(struct clk *);
87 void clk_enable_init_clocks(void);
88
89 struct clk_div_mult_table {
90 unsigned int *divisors;
91 unsigned int nr_divisors;
92 unsigned int *multipliers;
93 unsigned int nr_multipliers;
94 };
95
96 struct cpufreq_frequency_table;
97 void clk_rate_table_build(struct clk *clk,
98 struct cpufreq_frequ
99 int nr_freqs,
100 struct clk_div_mult_
101 unsigned long *bitma
102
103 long clk_rate_table_round(struct clk *clk,
104 struct cpufreq_frequ
105 unsigned long rate);
106
107 int clk_rate_table_find(struct clk *clk,
108 struct cpufreq_frequen
109 unsigned long rate);
110
111 long clk_rate_div_range_round(struct clk *clk,
112 unsigned int div
113
114 long clk_rate_mult_range_round(struct clk *clk
115 unsigned int mu
116
117 #define SH_CLK_MSTP(_parent, _enable_reg, _ena
118 {
119 .parent = _parent,
120 .enable_reg = (void __iomem *)_ena
121 .enable_bit = _enable_bit,
122 .status_reg = _status_reg,
123 .flags = _flags,
124 }
125
126 #define SH_CLK_MSTP32(_p, _r, _b, _f)
127 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_EN
128
129 #define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f)
130 SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_E
131
132 #define SH_CLK_MSTP16(_p, _r, _b, _f)
133 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_EN
134
135 #define SH_CLK_MSTP8(_p, _r, _b, _f)
136 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_EN
137
138 int sh_clk_mstp_register(struct clk *clks, int
139
140 /*
141 * MSTP registration never really cared about
142 * original enable/disable pairs assuming a 32
143 * responsible for defining their access sizes
144 * clock definition wrappers.
145 */
146 static inline int __deprecated sh_clk_mstp32_r
147 {
148 return sh_clk_mstp_register(clks, nr);
149 }
150
151 #define SH_CLK_DIV4(_parent, _reg, _shift, _di
152 {
153 .parent = _parent,
154 .enable_reg = (void __iomem *)_reg,
155 .enable_bit = _shift,
156 .arch_flags = _div_bitmap,
157 .div_mask = SH_CLK_DIV4_MSK,
158 .flags = _flags,
159 }
160
161 struct clk_div_table {
162 struct clk_div_mult_table *div_mult_ta
163 void (*kick)(struct clk *clk);
164 };
165
166 #define clk_div4_table clk_div_table
167
168 int sh_clk_div4_register(struct clk *clks, int
169 struct clk_div4_table
170 int sh_clk_div4_enable_register(struct clk *cl
171 struct clk_div4_table
172 int sh_clk_div4_reparent_register(struct clk *
173 struct clk_div4_table
174
175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents
176 _num_parents, _src_shi
177 {
178 .enable_reg = (void __iomem *)_reg,
179 .enable_bit = 0, /* unused */
180 .flags = _flags | CLK_MASK_DIV_ON_DISA
181 .div_mask = SH_CLK_DIV6_MSK,
182 .parent_table = _parents,
183 .parent_num = _num_parents,
184 .src_shift = _src_shift,
185 .src_width = _src_width,
186 }
187
188 #define SH_CLK_DIV6(_parent, _reg, _flags)
189 {
190 .parent = _parent,
191 .enable_reg = (void __iomem *)_reg
192 .enable_bit = 0, /* unused */
193 .div_mask = SH_CLK_DIV6_MSK,
194 .flags = _flags | CLK_MASK_DI
195 }
196
197 int sh_clk_div6_register(struct clk *clks, int
198 int sh_clk_div6_reparent_register(struct clk *
199
200 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _
201 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _
202 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con
203
204 /* .enable_reg will be updated to .mapping on
205 #define SH_CLK_FSIDIV(_reg, _parent)
206 {
207 .enable_reg = (void __iomem *)_reg,
208 .parent = _parent,
209 }
210
211 int sh_clk_fsidiv_register(struct clk *clks, i
212
213 #endif /* __SH_CLOCK_H */
214
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