1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (c) 2010-2015 Samsung Electronics 4 * http://www.samsung.com 5 * 6 * Exynos - Power management unit definition 7 * 8 * Notice: 9 * This is not a list of all Exynos Power Mana 10 * There are too many of them, not mentioning 11 * between SoCs. For now, put here only the us 12 */ 13 14 #ifndef __LINUX_SOC_EXYNOS_REGS_PMU_H 15 #define __LINUX_SOC_EXYNOS_REGS_PMU_H __FILE__ 16 17 #define S5P_CENTRAL_SEQ_CONFIGURATION 18 19 #define S5P_CENTRAL_LOWPWR_CFG 20 21 #define S5P_CENTRAL_SEQ_OPTION 22 23 #define S5P_USE_STANDBY_WFI0 24 #define S5P_USE_STANDBY_WFI1 25 #define S5P_USE_STANDBY_WFI2 26 #define S5P_USE_STANDBY_WFI3 27 #define S5P_USE_STANDBY_WFE0 28 #define S5P_USE_STANDBY_WFE1 29 #define S5P_USE_STANDBY_WFE2 30 #define S5P_USE_STANDBY_WFE3 31 32 #define S5P_USE_STANDBY_WFI_ALL \ 33 (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDB 34 S5P_USE_STANDBY_WFI2 | S5P_USE_STANDB 35 S5P_USE_STANDBY_WFE0 | S5P_USE_STANDB 36 S5P_USE_STANDBY_WFE2 | S5P_USE_STANDB 37 38 #define S5P_USE_DELAYED_RESET_ASSERTION 39 40 #define EXYNOS_CORE_PO_RESET(n) 41 #define EXYNOS_WAKEUP_FROM_LOWPWR 42 #define EXYNOS_SWRESET 43 44 #define S5P_WAKEUP_STAT 45 /* Value for EXYNOS_EINT_WAKEUP_MASK disabling 46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 47 #define EXYNOS_EINT_WAKEUP_MASK 48 #define S5P_WAKEUP_MASK 49 #define S5P_WAKEUP_MASK2 50 51 /* MIPI_PHYn_CONTROL, valid for Exynos3250, Ex 52 #define EXYNOS4_MIPI_PHY_CONTROL(n) 53 /* Phy enable bit, common for all phy register 54 #define EXYNOS4_PHY_ENABLE 55 #define EXYNOS4_MIPI_PHY_SRESETN 56 #define EXYNOS4_MIPI_PHY_MRESETN 57 #define EXYNOS4_MIPI_PHY_RESET_MASK 58 59 #define S5P_INFORM0 60 #define S5P_INFORM1 61 #define S5P_INFORM5 62 #define S5P_INFORM6 63 #define S5P_INFORM7 64 #define S5P_PMU_SPARE2 65 #define S5P_PMU_SPARE3 66 67 #define EXYNOS_IROM_DATA2 68 #define S5P_ARM_CORE0_LOWPWR 69 #define S5P_DIS_IRQ_CORE0 70 #define S5P_DIS_IRQ_CENTRAL0 71 #define S5P_ARM_CORE1_LOWPWR 72 #define S5P_DIS_IRQ_CORE1 73 #define S5P_DIS_IRQ_CENTRAL1 74 #define S5P_ARM_COMMON_LOWPWR 75 #define S5P_L2_0_LOWPWR 76 #define S5P_L2_1_LOWPWR 77 #define S5P_CMU_ACLKSTOP_LOWPWR 78 #define S5P_CMU_SCLKSTOP_LOWPWR 79 #define S5P_CMU_RESET_LOWPWR 80 #define S5P_APLL_SYSCLK_LOWPWR 81 #define S5P_MPLL_SYSCLK_LOWPWR 82 #define S5P_VPLL_SYSCLK_LOWPWR 83 #define S5P_EPLL_SYSCLK_LOWPWR 84 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 85 #define S5P_CMU_RESET_GPSALIVE_LOWPWR 86 #define S5P_CMU_CLKSTOP_CAM_LOWPWR 87 #define S5P_CMU_CLKSTOP_TV_LOWPWR 88 #define S5P_CMU_CLKSTOP_MFC_LOWPWR 89 #define S5P_CMU_CLKSTOP_G3D_LOWPWR 90 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 91 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 92 #define S5P_CMU_CLKSTOP_GPS_LOWPWR 93 #define S5P_CMU_RESET_CAM_LOWPWR 94 #define S5P_CMU_RESET_TV_LOWPWR 95 #define S5P_CMU_RESET_MFC_LOWPWR 96 #define S5P_CMU_RESET_G3D_LOWPWR 97 #define S5P_CMU_RESET_LCD0_LOWPWR 98 #define S5P_CMU_RESET_MAUDIO_LOWPWR 99 #define S5P_CMU_RESET_GPS_LOWPWR 100 #define S5P_TOP_BUS_LOWPWR 101 #define S5P_TOP_RETENTION_LOWPWR 102 #define S5P_TOP_PWR_LOWPWR 103 #define S5P_LOGIC_RESET_LOWPWR 104 #define S5P_ONENAND_MEM_LOWPWR 105 #define S5P_G2D_ACP_MEM_LOWPWR 106 #define S5P_USBOTG_MEM_LOWPWR 107 #define S5P_HSMMC_MEM_LOWPWR 108 #define S5P_CSSYS_MEM_LOWPWR 109 #define S5P_SECSS_MEM_LOWPWR 110 #define S5P_PAD_RETENTION_DRAM_LOWPWR 111 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 112 #define S5P_PAD_RETENTION_GPIO_LOWPWR 113 #define S5P_PAD_RETENTION_UART_LOWPWR 114 #define S5P_PAD_RETENTION_MMCA_LOWPWR 115 #define S5P_PAD_RETENTION_MMCB_LOWPWR 116 #define S5P_PAD_RETENTION_EBIA_LOWPWR 117 #define S5P_PAD_RETENTION_EBIB_LOWPWR 118 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 119 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 120 #define S5P_XUSBXTI_LOWPWR 121 #define S5P_XXTI_LOWPWR 122 #define S5P_EXT_REGULATOR_LOWPWR 123 #define S5P_GPIO_MODE_LOWPWR 124 #define S5P_GPIO_MODE_MAUDIO_LOWPWR 125 #define S5P_CAM_LOWPWR 126 #define S5P_TV_LOWPWR 127 #define S5P_MFC_LOWPWR 128 #define S5P_G3D_LOWPWR 129 #define S5P_LCD0_LOWPWR 130 #define S5P_MAUDIO_LOWPWR 131 #define S5P_GPS_LOWPWR 132 #define S5P_GPS_ALIVE_LOWPWR 133 134 #define EXYNOS_ARM_CORE0_CONFIGURATION 135 #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) 136 (EXYNOS_ARM_CORE0_CONF 137 #define EXYNOS_ARM_CORE_STATUS(_nr) 138 (EXYNOS_ARM_CORE_CONFI 139 #define EXYNOS_ARM_CORE_OPTION(_nr) 140 (EXYNOS_ARM_CORE_CONFI 141 142 #define EXYNOS_ARM_COMMON_CONFIGURATION 143 #define EXYNOS_COMMON_CONFIGURATION(_nr) 144 (EXYNOS_ARM_COMMON_CON 145 #define EXYNOS_COMMON_STATUS(_nr) 146 (EXYNOS_COMMON_CONFIGU 147 #define EXYNOS_COMMON_OPTION(_nr) 148 (EXYNOS_COMMON_CONFIGU 149 150 #define EXYNOS_ARM_L2_CONFIGURATION 151 #define EXYNOS_L2_CONFIGURATION(_nr) 152 (EXYNOS_ARM_L2_CONFIGU 153 #define EXYNOS_L2_STATUS(_nr) 154 (EXYNOS_L2_CONFIGURATI 155 #define EXYNOS_L2_OPTION(_nr) 156 (EXYNOS_L2_CONFIGURATI 157 158 #define EXYNOS_L2_USE_RETENTION 159 160 #define S5P_PAD_RET_MAUDIO_OPTION 161 #define S5P_PAD_RET_MMC2_OPTION 162 #define S5P_PAD_RET_GPIO_OPTION 163 #define S5P_PAD_RET_UART_OPTION 164 #define S5P_PAD_RET_MMCA_OPTION 165 #define S5P_PAD_RET_MMCB_OPTION 166 #define S5P_PAD_RET_EBIA_OPTION 167 #define S5P_PAD_RET_EBIB_OPTION 168 #define S5P_PAD_RET_SPI_OPTION 169 170 #define S5P_PS_HOLD_CONTROL 171 #define S5P_PS_HOLD_EN 172 #define S5P_PS_HOLD_OUTPUT_HIGH 173 174 #define S5P_CAM_OPTION 175 #define S5P_MFC_OPTION 176 #define S5P_G3D_OPTION 177 #define S5P_LCD0_OPTION 178 #define S5P_LCD1_OPTION 179 #define S5P_ISP_OPTION 180 181 #define S5P_CORE_LOCAL_PWR_EN 182 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG 183 #define S5P_CORE_AUTOWAKEUP_EN 184 185 /* Only for S5Pv210 */ 186 #define S5PV210_EINT_WAKEUP_MASK 0xC004 187 188 /* Only for Exynos4210 */ 189 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 190 #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 191 #define S5P_MODIMIF_MEM_LOWPWR 0x11C4 192 #define S5P_PCIE_MEM_LOWPWR 0x11E0 193 #define S5P_SATA_MEM_LOWPWR 0x11E4 194 #define S5P_LCD1_LOWPWR 0x1394 195 196 /* Only for Exynos4x12 */ 197 #define S5P_ISP_ARM_LOWPWR 198 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 199 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 200 #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 201 #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 202 #define S5P_CMU_RESET_COREBLK_LOWPWR 203 #define S5P_MPLLUSER_SYSCLK_LOWPWR 204 #define S5P_CMU_CLKSTOP_ISP_LOWPWR 205 #define S5P_CMU_RESET_ISP_LOWPWR 206 #define S5P_TOP_BUS_COREBLK_LOWPWR 207 #define S5P_TOP_RETENTION_COREBLK_LOWPWR 208 #define S5P_TOP_PWR_COREBLK_LOWPWR 209 #define S5P_OSCCLK_GATE_LOWPWR 210 #define S5P_LOGIC_RESET_COREBLK_LOWPWR 211 #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 212 #define S5P_HSI_MEM_LOWPWR 213 #define S5P_ROTATOR_MEM_LOWPWR 214 #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 215 #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 216 #define S5P_GPIO_MODE_COREBLK_LOWPWR 217 #define S5P_TOP_ASB_RESET_LOWPWR 218 #define S5P_TOP_ASB_ISOLATION_LOWPWR 219 #define S5P_ISP_LOWPWR 220 #define S5P_DRAM_FREQ_DOWN_LOWPWR 221 #define S5P_DDRPHY_DLLOFF_LOWPWR 222 #define S5P_CMU_SYSCLK_ISP_LOWPWR 223 #define S5P_CMU_SYSCLK_GPS_LOWPWR 224 #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 225 226 #define S5P_ARM_L2_0_OPTION 227 #define S5P_ARM_L2_1_OPTION 228 #define S5P_ONENAND_MEM_OPTION 229 #define S5P_HSI_MEM_OPTION 230 #define S5P_G2D_ACP_MEM_OPTION 231 #define S5P_USBOTG_MEM_OPTION 232 #define S5P_HSMMC_MEM_OPTION 233 #define S5P_CSSYS_MEM_OPTION 234 #define S5P_SECSS_MEM_OPTION 235 #define S5P_ROTATOR_MEM_OPTION 236 237 /* Only for Exynos4412 */ 238 #define S5P_ARM_CORE2_LOWPWR 239 #define S5P_DIS_IRQ_CORE2 240 #define S5P_DIS_IRQ_CENTRAL2 241 #define S5P_ARM_CORE3_LOWPWR 242 #define S5P_DIS_IRQ_CORE3 243 #define S5P_DIS_IRQ_CENTRAL3 244 245 /* Only for Exynos3XXX */ 246 #define EXYNOS3_ARM_CORE0_SYS_PWR_REG 247 #define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PW 248 #define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_ 249 #define EXYNOS3_ARM_CORE1_SYS_PWR_REG 250 #define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PW 251 #define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_ 252 #define EXYNOS3_ISP_ARM_SYS_PWR_REG 253 #define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_ 254 #define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PW 255 #define EXYNOS3_ARM_COMMON_SYS_PWR_REG 256 #define EXYNOS3_ARM_L2_SYS_PWR_REG 257 #define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 258 #define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 259 #define EXYNOS3_CMU_RESET_SYS_PWR_REG 260 #define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_R 261 #define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_R 262 #define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 263 #define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 264 #define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 265 #define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 266 #define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 267 #define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 268 #define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 269 #define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 270 #define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 271 #define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 272 #define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 273 #define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 274 #define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 275 #define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 276 #define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 277 #define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 278 #define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 279 #define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 280 #define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 281 #define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 282 #define EXYNOS3_TOP_BUS_SYS_PWR_REG 283 #define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 284 #define EXYNOS3_TOP_PWR_SYS_PWR_REG 285 #define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 286 #define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_ 287 #define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 288 #define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 289 #define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 290 #define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_RE 291 #define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_RE 292 #define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 293 #define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_R 294 #define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 295 #define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 296 #define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 297 #define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 298 #define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 299 #define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 300 #define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 301 #define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 302 #define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 303 #define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 304 #define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 305 #define EXYNOS3_XUSBXTI_SYS_PWR_REG 306 #define EXYNOS3_XXTI_SYS_PWR_REG 307 #define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 308 #define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_ 309 #define EXYNOS3_GPIO_MODE_SYS_PWR_REG 310 #define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 311 #define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 312 #define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 313 #define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_ 314 #define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_ 315 #define EXYNOS3_CAM_SYS_PWR_REG 316 #define EXYNOS3_MFC_SYS_PWR_REG 317 #define EXYNOS3_G3D_SYS_PWR_REG 318 #define EXYNOS3_LCD0_SYS_PWR_REG 319 #define EXYNOS3_ISP_SYS_PWR_REG 320 #define EXYNOS3_MAUDIO_SYS_PWR_REG 321 #define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 322 #define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 323 #define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 324 #define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 325 #define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 326 #define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 327 328 #define EXYNOS3_ARM_CORE0_OPTION 329 #define EXYNOS3_ARM_CORE_OPTION(_nr) \ 330 (EXYNOS3_ARM_CORE0_OPT 331 332 #define EXYNOS3_ARM_COMMON_OPTION 333 #define EXYNOS3_ARM_L2_OPTION 334 #define EXYNOS3_TOP_PWR_OPTION 335 #define EXYNOS3_CORE_TOP_PWR_OPTION 336 #define EXYNOS3_XUSBXTI_DURATION 337 #define EXYNOS3_XXTI_DURATION 338 #define EXYNOS3_EXT_REGULATOR_DURATION 339 #define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 340 #define XUSBXTI_DURATION 341 #define XXTI_DURATION 342 #define EXT_REGULATOR_DURATION 343 #define EXT_REGULATOR_COREBLK_DURATION 344 345 /* for XXX_OPTION */ 346 #define EXYNOS3_OPTION_USE_SC_COUNTER 347 #define EXYNOS3_OPTION_USE_SC_FEEDBACK 348 #define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_ 349 350 /* For Exynos5 */ 351 352 #define EXYNOS5_AUTO_WDTRESET_DISABLE 353 #define EXYNOS5_MASK_WDTRESET_REQUEST 354 #define EXYNOS5_USBDRD_PHY_CONTROL 355 #define EXYNOS5_DPTX_PHY_CONTROL 356 357 #define EXYNOS5_USE_RETENTION 358 #define EXYNOS5_SYS_WDTRESET 359 360 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 361 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PW 362 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_ 363 #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 364 #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PW 365 #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_ 366 #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 367 #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_P 368 #define EXYNOS5_ISP_ARM_SYS_PWR_REG 369 #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_ 370 #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PW 371 #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 372 #define EXYNOS5_ARM_L2_SYS_PWR_REG 373 #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 374 #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 375 #define EXYNOS5_CMU_RESET_SYS_PWR_REG 376 #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_RE 377 #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_RE 378 #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 379 #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 380 #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 381 #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 382 #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 383 #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 384 #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 385 #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 386 #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 387 #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 388 #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 389 #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 390 #define EXYNOS5_TOP_BUS_SYS_PWR_REG 391 #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 392 #define EXYNOS5_TOP_PWR_SYS_PWR_REG 393 #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 394 #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_R 395 #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 396 #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 397 #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 398 #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 399 #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 400 #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 401 #define EXYNOS5_G2D_MEM_SYS_PWR_REG 402 #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 403 #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 404 #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 405 #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 406 #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 407 #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 408 #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 409 #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 410 #define EXYNOS5_HSI_MEM_SYS_PWR_REG 411 #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 412 #define EXYNOS5_SATA_MEM_SYS_PWR_REG 413 #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 414 #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 415 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 416 #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 417 #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 418 #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 419 #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 420 #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 421 #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 422 #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_ 423 #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 424 #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_R 425 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 426 #define EXYNOS5_XUSBXTI_SYS_PWR_REG 427 #define EXYNOS5_XXTI_SYS_PWR_REG 428 #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 429 #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 430 #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 431 #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 432 #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 433 #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 434 #define EXYNOS5_GSCL_SYS_PWR_REG 435 #define EXYNOS5_ISP_SYS_PWR_REG 436 #define EXYNOS5_MFC_SYS_PWR_REG 437 #define EXYNOS5_G3D_SYS_PWR_REG 438 #define EXYNOS5_DISP1_SYS_PWR_REG 439 #define EXYNOS5_MAU_SYS_PWR_REG 440 #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 441 #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 442 #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 443 #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 444 #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 445 #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 446 #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 447 #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 448 #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 449 #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 450 #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 451 #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 452 #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 453 #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 454 #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 455 #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 456 #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 457 #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 458 459 #define EXYNOS5_ARM_CORE0_OPTION 460 #define EXYNOS5_ARM_CORE1_OPTION 461 #define EXYNOS5_FSYS_ARM_OPTION 462 #define EXYNOS5_ISP_ARM_OPTION 463 #define EXYNOS5_ARM_COMMON_OPTION 464 #define EXYNOS5_ARM_L2_OPTION 465 #define EXYNOS5_TOP_PWR_OPTION 466 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 467 #define EXYNOS5_JPEG_MEM_OPTION 468 #define EXYNOS5_GSCL_OPTION 469 #define EXYNOS5_ISP_OPTION 470 #define EXYNOS5_MFC_OPTION 471 #define EXYNOS5_G3D_OPTION 472 #define EXYNOS5_DISP1_OPTION 473 #define EXYNOS5_MAU_OPTION 474 475 #define EXYNOS5_USE_SC_FEEDBACK 476 #define EXYNOS5_USE_SC_COUNTER 477 478 #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN 479 480 #define EXYNOS5_OPTION_USE_STANDBYWFE 481 #define EXYNOS5_OPTION_USE_STANDBYWFI 482 483 #define EXYNOS5_OPTION_USE_RETENTION 484 485 #define EXYNOS5420_SWRESET_KFC_SEL 486 487 /* Only for Exynos5420 */ 488 #define EXYNOS5420_L2RSTDISABLE_VALUE 489 490 #define EXYNOS5420_LPI_MASK 491 #define EXYNOS5420_LPI_MASK1 492 #define EXYNOS5420_UFS 493 #define EXYNOS5420_ATB_KFC 494 #define EXYNOS5420_ATB_ISP_ARM 495 #define EXYNOS5420_EMULATION 496 497 #define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 498 #define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBY 499 #define EXYNOS5420_UP_SCHEDULER 500 #define SPREAD_ENABLE 501 #define SPREAD_USE_STANDWFI 502 503 #define EXYNOS5420_KFC_CORE_RESET0 504 #define EXYNOS5420_KFC_ETM_RESET0 505 506 #define EXYNOS5420_KFC_CORE_RESET(_nr) 507 ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5 508 509 #define EXYNOS5420_USBDRD1_PHY_CONTROL 510 #define EXYNOS5420_MIPI_PHY_CONTROL(n) 511 #define EXYNOS5420_DPTX_PHY_CONTROL 512 #define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 513 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS 514 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_S 515 #define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 516 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS 517 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_S 518 #define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 519 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS 520 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_S 521 #define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 522 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS 523 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_S 524 #define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 525 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS 526 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_S 527 #define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 528 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS 529 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_S 530 #define EXYNOS5420_ISP_ARM_SYS_PWR_REG 531 #define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_P 532 #define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS 533 #define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 534 #define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 535 #define EXYNOS5420_KFC_L2_SYS_PWR_REG 536 #define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 537 #define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 538 #define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 539 #define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 540 #define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 541 #define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 542 #define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 543 #define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_ 544 #define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_ 545 #define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_ 546 #define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_ 547 #define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_ 548 #define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_ 549 #define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_R 550 #define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_ 551 #define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_ 552 #define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_R 553 #define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_ 554 #define EXYNOS5420_DISP1_SYS_PWR_REG 555 #define EXYNOS5420_MAU_SYS_PWR_REG 556 #define EXYNOS5420_G2D_SYS_PWR_REG 557 #define EXYNOS5420_MSC_SYS_PWR_REG 558 #define EXYNOS5420_FSYS_SYS_PWR_REG 559 #define EXYNOS5420_FSYS2_SYS_PWR_REG 560 #define EXYNOS5420_PSGEN_SYS_PWR_REG 561 #define EXYNOS5420_PERIC_SYS_PWR_REG 562 #define EXYNOS5420_WCORE_SYS_PWR_REG 563 #define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_R 564 #define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 565 #define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 566 #define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 567 #define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_RE 568 #define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_R 569 #define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_R 570 #define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_R 571 #define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_R 572 #define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_R 573 #define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_RE 574 #define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 575 #define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 576 #define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 577 #define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 578 #define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_RE 579 #define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_RE 580 #define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_RE 581 #define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_RE 582 #define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SY 583 #define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 584 #define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 585 #define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 586 #define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 587 #define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 588 #define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 589 #define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 590 #define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 591 #define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 592 #define EXYNOS5420_SFR_AXI_CGDIS1 593 #define EXYNOS5420_ARM_COMMON_OPTION 594 #define EXYNOS5420_KFC_COMMON_OPTION 595 #define EXYNOS5420_LOGIC_RESET_DURATION3 596 597 #define EXYNOS5420_PAD_RET_GPIO_OPTION 598 #define EXYNOS5420_PAD_RET_UART_OPTION 599 #define EXYNOS5420_PAD_RET_MMCA_OPTION 600 #define EXYNOS5420_PAD_RET_MMCB_OPTION 601 #define EXYNOS5420_PAD_RET_MMCC_OPTION 602 #define EXYNOS5420_PAD_RET_HSI_OPTION 603 #define EXYNOS5420_PAD_RET_SPI_OPTION 604 #define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 605 #define EXYNOS_PAD_RET_DRAM_OPTION 606 #define EXYNOS_PAD_RET_MAUDIO_OPTION 607 #define EXYNOS_PAD_RET_JTAG_OPTION 608 #define EXYNOS_PAD_RET_EBIA_OPTION 609 #define EXYNOS_PAD_RET_EBIB_OPTION 610 611 #define EXYNOS5420_FSYS2_OPTION 612 #define EXYNOS5420_PSGEN_OPTION 613 614 #define EXYNOS5420_ARM_USE_STANDBY_WFI0 615 #define EXYNOS5420_ARM_USE_STANDBY_WFI1 616 #define EXYNOS5420_ARM_USE_STANDBY_WFI2 617 #define EXYNOS5420_ARM_USE_STANDBY_WFI3 618 #define EXYNOS5420_KFC_USE_STANDBY_WFI0 619 #define EXYNOS5420_KFC_USE_STANDBY_WFI1 620 #define EXYNOS5420_KFC_USE_STANDBY_WFI2 621 #define EXYNOS5420_KFC_USE_STANDBY_WFI3 622 #define EXYNOS5420_ARM_USE_STANDBY_WFE0 623 #define EXYNOS5420_ARM_USE_STANDBY_WFE1 624 #define EXYNOS5420_ARM_USE_STANDBY_WFE2 625 #define EXYNOS5420_ARM_USE_STANDBY_WFE3 626 #define EXYNOS5420_KFC_USE_STANDBY_WFE0 627 #define EXYNOS5420_KFC_USE_STANDBY_WFE1 628 #define EXYNOS5420_KFC_USE_STANDBY_WFE2 629 #define EXYNOS5420_KFC_USE_STANDBY_WFE3 630 631 #define DUR_WAIT_RESET 632 633 #define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNO 634 | EXY 635 | EXY 636 | EXY 637 | EXY 638 | EXY 639 | EXY 640 | EXY 641 642 /* For Exynos5433 */ 643 #define EXYNOS5433_EINT_WAKEUP_MASK 644 #define EXYNOS5433_USBHOST30_PHY_CONTROL 645 #define EXYNOS5433_PAD_RETENTION_AUD_OPTION 646 #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION 647 #define EXYNOS5433_PAD_RETENTION_TOP_OPTION 648 #define EXYNOS5433_PAD_RETENTION_UART_OPTION 649 #define EXYNOS5433_PAD_RETENTION_MMC0_OPTION 650 #define EXYNOS5433_PAD_RETENTION_MMC1_OPTION 651 #define EXYNOS5433_PAD_RETENTION_EBIA_OPTION 652 #define EXYNOS5433_PAD_RETENTION_EBIB_OPTION 653 #define EXYNOS5433_PAD_RETENTION_SPI_OPTION 654 #define EXYNOS5433_PAD_RETENTION_MIF_OPTION 655 #define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION 656 #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTIO 657 #define EXYNOS5433_PAD_RETENTION_UFS_OPTION 658 #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPT 659 660 /* For Tensor GS101 */ 661 #define GS101_SYSIP_DAT0 662 #define GS101_SYSTEM_CONFIGURATION 663 #define GS101_PHY_CTRL_USB20 664 #define GS101_PHY_CTRL_USBDP 665 666 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ 667
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