1 /* SPDX-License-Identifier: GPL-2.0 */ <<
2 /* 1 /*
3 * Copyright (c) 2010-2015 Samsung Electronics !! 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * Exynos - Power management unit definition !! 5 * EXYNOS - Power management unit definition
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify
>> 8 * it under the terms of the GNU General Public License version 2 as
>> 9 * published by the Free Software Foundation.
>> 10 *
7 * 11 *
8 * Notice: 12 * Notice:
9 * This is not a list of all Exynos Power Mana 13 * This is not a list of all Exynos Power Management Unit SFRs.
10 * There are too many of them, not mentioning 14 * There are too many of them, not mentioning subtle differences
11 * between SoCs. For now, put here only the us 15 * between SoCs. For now, put here only the used registers.
12 */ 16 */
13 17
14 #ifndef __LINUX_SOC_EXYNOS_REGS_PMU_H 18 #ifndef __LINUX_SOC_EXYNOS_REGS_PMU_H
15 #define __LINUX_SOC_EXYNOS_REGS_PMU_H __FILE__ 19 #define __LINUX_SOC_EXYNOS_REGS_PMU_H __FILE__
16 20
17 #define S5P_CENTRAL_SEQ_CONFIGURATION 21 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
18 22
19 #define S5P_CENTRAL_LOWPWR_CFG 23 #define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
20 24
21 #define S5P_CENTRAL_SEQ_OPTION 25 #define S5P_CENTRAL_SEQ_OPTION 0x0208
22 26
23 #define S5P_USE_STANDBY_WFI0 27 #define S5P_USE_STANDBY_WFI0 (1 << 16)
24 #define S5P_USE_STANDBY_WFI1 28 #define S5P_USE_STANDBY_WFI1 (1 << 17)
25 #define S5P_USE_STANDBY_WFI2 29 #define S5P_USE_STANDBY_WFI2 (1 << 19)
26 #define S5P_USE_STANDBY_WFI3 30 #define S5P_USE_STANDBY_WFI3 (1 << 20)
27 #define S5P_USE_STANDBY_WFE0 31 #define S5P_USE_STANDBY_WFE0 (1 << 24)
28 #define S5P_USE_STANDBY_WFE1 32 #define S5P_USE_STANDBY_WFE1 (1 << 25)
29 #define S5P_USE_STANDBY_WFE2 33 #define S5P_USE_STANDBY_WFE2 (1 << 27)
30 #define S5P_USE_STANDBY_WFE3 34 #define S5P_USE_STANDBY_WFE3 (1 << 28)
31 35
32 #define S5P_USE_STANDBY_WFI_ALL \ 36 #define S5P_USE_STANDBY_WFI_ALL \
33 (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDB 37 (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \
34 S5P_USE_STANDBY_WFI2 | S5P_USE_STANDB 38 S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \
35 S5P_USE_STANDBY_WFE0 | S5P_USE_STANDB 39 S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \
36 S5P_USE_STANDBY_WFE2 | S5P_USE_STANDB 40 S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3)
37 41
38 #define S5P_USE_DELAYED_RESET_ASSERTION 42 #define S5P_USE_DELAYED_RESET_ASSERTION BIT(12)
39 43
40 #define EXYNOS_CORE_PO_RESET(n) 44 #define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n)
41 #define EXYNOS_WAKEUP_FROM_LOWPWR 45 #define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28)
42 #define EXYNOS_SWRESET 46 #define EXYNOS_SWRESET 0x0400
43 47
44 #define S5P_WAKEUP_STAT 48 #define S5P_WAKEUP_STAT 0x0600
45 /* Value for EXYNOS_EINT_WAKEUP_MASK disabling !! 49 #define S5P_EINT_WAKEUP_MASK 0x0604
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED <<
47 #define EXYNOS_EINT_WAKEUP_MASK <<
48 #define S5P_WAKEUP_MASK 50 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 51 #define S5P_WAKEUP_MASK2 0x0614
50 52
51 /* MIPI_PHYn_CONTROL, valid for Exynos3250, Ex <<
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) <<
53 /* Phy enable bit, common for all phy register <<
54 #define EXYNOS4_PHY_ENABLE <<
55 #define EXYNOS4_MIPI_PHY_SRESETN <<
56 #define EXYNOS4_MIPI_PHY_MRESETN <<
57 #define EXYNOS4_MIPI_PHY_RESET_MASK <<
58 <<
59 #define S5P_INFORM0 53 #define S5P_INFORM0 0x0800
60 #define S5P_INFORM1 54 #define S5P_INFORM1 0x0804
61 #define S5P_INFORM5 55 #define S5P_INFORM5 0x0814
62 #define S5P_INFORM6 56 #define S5P_INFORM6 0x0818
63 #define S5P_INFORM7 57 #define S5P_INFORM7 0x081C
64 #define S5P_PMU_SPARE2 58 #define S5P_PMU_SPARE2 0x0908
65 #define S5P_PMU_SPARE3 59 #define S5P_PMU_SPARE3 0x090C
66 60
67 #define EXYNOS_IROM_DATA2 61 #define EXYNOS_IROM_DATA2 0x0988
68 #define S5P_ARM_CORE0_LOWPWR 62 #define S5P_ARM_CORE0_LOWPWR 0x1000
69 #define S5P_DIS_IRQ_CORE0 63 #define S5P_DIS_IRQ_CORE0 0x1004
70 #define S5P_DIS_IRQ_CENTRAL0 64 #define S5P_DIS_IRQ_CENTRAL0 0x1008
71 #define S5P_ARM_CORE1_LOWPWR 65 #define S5P_ARM_CORE1_LOWPWR 0x1010
72 #define S5P_DIS_IRQ_CORE1 66 #define S5P_DIS_IRQ_CORE1 0x1014
73 #define S5P_DIS_IRQ_CENTRAL1 67 #define S5P_DIS_IRQ_CENTRAL1 0x1018
74 #define S5P_ARM_COMMON_LOWPWR 68 #define S5P_ARM_COMMON_LOWPWR 0x1080
75 #define S5P_L2_0_LOWPWR 69 #define S5P_L2_0_LOWPWR 0x10C0
76 #define S5P_L2_1_LOWPWR 70 #define S5P_L2_1_LOWPWR 0x10C4
77 #define S5P_CMU_ACLKSTOP_LOWPWR 71 #define S5P_CMU_ACLKSTOP_LOWPWR 0x1100
78 #define S5P_CMU_SCLKSTOP_LOWPWR 72 #define S5P_CMU_SCLKSTOP_LOWPWR 0x1104
79 #define S5P_CMU_RESET_LOWPWR 73 #define S5P_CMU_RESET_LOWPWR 0x110C
80 #define S5P_APLL_SYSCLK_LOWPWR 74 #define S5P_APLL_SYSCLK_LOWPWR 0x1120
81 #define S5P_MPLL_SYSCLK_LOWPWR 75 #define S5P_MPLL_SYSCLK_LOWPWR 0x1124
82 #define S5P_VPLL_SYSCLK_LOWPWR 76 #define S5P_VPLL_SYSCLK_LOWPWR 0x1128
83 #define S5P_EPLL_SYSCLK_LOWPWR 77 #define S5P_EPLL_SYSCLK_LOWPWR 0x112C
84 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 78 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138
85 #define S5P_CMU_RESET_GPSALIVE_LOWPWR 79 #define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C
86 #define S5P_CMU_CLKSTOP_CAM_LOWPWR 80 #define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140
87 #define S5P_CMU_CLKSTOP_TV_LOWPWR 81 #define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144
88 #define S5P_CMU_CLKSTOP_MFC_LOWPWR 82 #define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148
89 #define S5P_CMU_CLKSTOP_G3D_LOWPWR 83 #define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C
90 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 84 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150
91 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 85 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158
92 #define S5P_CMU_CLKSTOP_GPS_LOWPWR 86 #define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C
93 #define S5P_CMU_RESET_CAM_LOWPWR 87 #define S5P_CMU_RESET_CAM_LOWPWR 0x1160
94 #define S5P_CMU_RESET_TV_LOWPWR 88 #define S5P_CMU_RESET_TV_LOWPWR 0x1164
95 #define S5P_CMU_RESET_MFC_LOWPWR 89 #define S5P_CMU_RESET_MFC_LOWPWR 0x1168
96 #define S5P_CMU_RESET_G3D_LOWPWR 90 #define S5P_CMU_RESET_G3D_LOWPWR 0x116C
97 #define S5P_CMU_RESET_LCD0_LOWPWR 91 #define S5P_CMU_RESET_LCD0_LOWPWR 0x1170
98 #define S5P_CMU_RESET_MAUDIO_LOWPWR 92 #define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178
99 #define S5P_CMU_RESET_GPS_LOWPWR 93 #define S5P_CMU_RESET_GPS_LOWPWR 0x117C
100 #define S5P_TOP_BUS_LOWPWR 94 #define S5P_TOP_BUS_LOWPWR 0x1180
101 #define S5P_TOP_RETENTION_LOWPWR 95 #define S5P_TOP_RETENTION_LOWPWR 0x1184
102 #define S5P_TOP_PWR_LOWPWR 96 #define S5P_TOP_PWR_LOWPWR 0x1188
103 #define S5P_LOGIC_RESET_LOWPWR 97 #define S5P_LOGIC_RESET_LOWPWR 0x11A0
104 #define S5P_ONENAND_MEM_LOWPWR 98 #define S5P_ONENAND_MEM_LOWPWR 0x11C0
105 #define S5P_G2D_ACP_MEM_LOWPWR 99 #define S5P_G2D_ACP_MEM_LOWPWR 0x11C8
106 #define S5P_USBOTG_MEM_LOWPWR 100 #define S5P_USBOTG_MEM_LOWPWR 0x11CC
107 #define S5P_HSMMC_MEM_LOWPWR 101 #define S5P_HSMMC_MEM_LOWPWR 0x11D0
108 #define S5P_CSSYS_MEM_LOWPWR 102 #define S5P_CSSYS_MEM_LOWPWR 0x11D4
109 #define S5P_SECSS_MEM_LOWPWR 103 #define S5P_SECSS_MEM_LOWPWR 0x11D8
110 #define S5P_PAD_RETENTION_DRAM_LOWPWR 104 #define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200
111 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 105 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204
112 #define S5P_PAD_RETENTION_GPIO_LOWPWR 106 #define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220
113 #define S5P_PAD_RETENTION_UART_LOWPWR 107 #define S5P_PAD_RETENTION_UART_LOWPWR 0x1224
114 #define S5P_PAD_RETENTION_MMCA_LOWPWR 108 #define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228
115 #define S5P_PAD_RETENTION_MMCB_LOWPWR 109 #define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C
116 #define S5P_PAD_RETENTION_EBIA_LOWPWR 110 #define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230
117 #define S5P_PAD_RETENTION_EBIB_LOWPWR 111 #define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234
118 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 112 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240
119 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 113 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260
120 #define S5P_XUSBXTI_LOWPWR 114 #define S5P_XUSBXTI_LOWPWR 0x1280
121 #define S5P_XXTI_LOWPWR 115 #define S5P_XXTI_LOWPWR 0x1284
122 #define S5P_EXT_REGULATOR_LOWPWR 116 #define S5P_EXT_REGULATOR_LOWPWR 0x12C0
123 #define S5P_GPIO_MODE_LOWPWR 117 #define S5P_GPIO_MODE_LOWPWR 0x1300
124 #define S5P_GPIO_MODE_MAUDIO_LOWPWR 118 #define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340
125 #define S5P_CAM_LOWPWR 119 #define S5P_CAM_LOWPWR 0x1380
126 #define S5P_TV_LOWPWR 120 #define S5P_TV_LOWPWR 0x1384
127 #define S5P_MFC_LOWPWR 121 #define S5P_MFC_LOWPWR 0x1388
128 #define S5P_G3D_LOWPWR 122 #define S5P_G3D_LOWPWR 0x138C
129 #define S5P_LCD0_LOWPWR 123 #define S5P_LCD0_LOWPWR 0x1390
130 #define S5P_MAUDIO_LOWPWR 124 #define S5P_MAUDIO_LOWPWR 0x1398
131 #define S5P_GPS_LOWPWR 125 #define S5P_GPS_LOWPWR 0x139C
132 #define S5P_GPS_ALIVE_LOWPWR 126 #define S5P_GPS_ALIVE_LOWPWR 0x13A0
133 127
134 #define EXYNOS_ARM_CORE0_CONFIGURATION 128 #define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000
135 #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) 129 #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \
136 (EXYNOS_ARM_CORE0_CONF 130 (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
137 #define EXYNOS_ARM_CORE_STATUS(_nr) 131 #define EXYNOS_ARM_CORE_STATUS(_nr) \
138 (EXYNOS_ARM_CORE_CONFI 132 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
139 #define EXYNOS_ARM_CORE_OPTION(_nr) 133 #define EXYNOS_ARM_CORE_OPTION(_nr) \
140 (EXYNOS_ARM_CORE_CONFI 134 (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8)
141 135
142 #define EXYNOS_ARM_COMMON_CONFIGURATION 136 #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500
143 #define EXYNOS_COMMON_CONFIGURATION(_nr) 137 #define EXYNOS_COMMON_CONFIGURATION(_nr) \
144 (EXYNOS_ARM_COMMON_CON 138 (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
145 #define EXYNOS_COMMON_STATUS(_nr) 139 #define EXYNOS_COMMON_STATUS(_nr) \
146 (EXYNOS_COMMON_CONFIGU 140 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
147 #define EXYNOS_COMMON_OPTION(_nr) 141 #define EXYNOS_COMMON_OPTION(_nr) \
148 (EXYNOS_COMMON_CONFIGU 142 (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
149 143
150 #define EXYNOS_ARM_L2_CONFIGURATION 144 #define EXYNOS_ARM_L2_CONFIGURATION 0x2600
151 #define EXYNOS_L2_CONFIGURATION(_nr) 145 #define EXYNOS_L2_CONFIGURATION(_nr) \
152 (EXYNOS_ARM_L2_CONFIGU 146 (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80))
153 #define EXYNOS_L2_STATUS(_nr) 147 #define EXYNOS_L2_STATUS(_nr) \
154 (EXYNOS_L2_CONFIGURATI 148 (EXYNOS_L2_CONFIGURATION(_nr) + 0x4)
155 #define EXYNOS_L2_OPTION(_nr) 149 #define EXYNOS_L2_OPTION(_nr) \
156 (EXYNOS_L2_CONFIGURATI 150 (EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
157 151
158 #define EXYNOS_L2_USE_RETENTION 152 #define EXYNOS_L2_USE_RETENTION BIT(4)
159 153
160 #define S5P_PAD_RET_MAUDIO_OPTION 154 #define S5P_PAD_RET_MAUDIO_OPTION 0x3028
161 #define S5P_PAD_RET_MMC2_OPTION 155 #define S5P_PAD_RET_MMC2_OPTION 0x30c8
162 #define S5P_PAD_RET_GPIO_OPTION 156 #define S5P_PAD_RET_GPIO_OPTION 0x3108
163 #define S5P_PAD_RET_UART_OPTION 157 #define S5P_PAD_RET_UART_OPTION 0x3128
164 #define S5P_PAD_RET_MMCA_OPTION 158 #define S5P_PAD_RET_MMCA_OPTION 0x3148
165 #define S5P_PAD_RET_MMCB_OPTION 159 #define S5P_PAD_RET_MMCB_OPTION 0x3168
166 #define S5P_PAD_RET_EBIA_OPTION 160 #define S5P_PAD_RET_EBIA_OPTION 0x3188
167 #define S5P_PAD_RET_EBIB_OPTION 161 #define S5P_PAD_RET_EBIB_OPTION 0x31A8
168 #define S5P_PAD_RET_SPI_OPTION 162 #define S5P_PAD_RET_SPI_OPTION 0x31c8
169 163
170 #define S5P_PS_HOLD_CONTROL 164 #define S5P_PS_HOLD_CONTROL 0x330C
171 #define S5P_PS_HOLD_EN 165 #define S5P_PS_HOLD_EN (1 << 31)
172 #define S5P_PS_HOLD_OUTPUT_HIGH 166 #define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8)
173 167
174 #define S5P_CAM_OPTION 168 #define S5P_CAM_OPTION 0x3C08
175 #define S5P_MFC_OPTION 169 #define S5P_MFC_OPTION 0x3C48
176 #define S5P_G3D_OPTION 170 #define S5P_G3D_OPTION 0x3C68
177 #define S5P_LCD0_OPTION 171 #define S5P_LCD0_OPTION 0x3C88
178 #define S5P_LCD1_OPTION 172 #define S5P_LCD1_OPTION 0x3CA8
179 #define S5P_ISP_OPTION 173 #define S5P_ISP_OPTION S5P_LCD1_OPTION
180 174
181 #define S5P_CORE_LOCAL_PWR_EN 175 #define S5P_CORE_LOCAL_PWR_EN 0x3
182 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG 176 #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8)
183 #define S5P_CORE_AUTOWAKEUP_EN 177 #define S5P_CORE_AUTOWAKEUP_EN (1 << 31)
184 178
185 /* Only for S5Pv210 */ !! 179 /* Only for EXYNOS4210 */
186 #define S5PV210_EINT_WAKEUP_MASK 0xC004 <<
187 <<
188 /* Only for Exynos4210 */ <<
189 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 180 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
190 #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 181 #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
191 #define S5P_MODIMIF_MEM_LOWPWR 0x11C4 182 #define S5P_MODIMIF_MEM_LOWPWR 0x11C4
192 #define S5P_PCIE_MEM_LOWPWR 0x11E0 183 #define S5P_PCIE_MEM_LOWPWR 0x11E0
193 #define S5P_SATA_MEM_LOWPWR 0x11E4 184 #define S5P_SATA_MEM_LOWPWR 0x11E4
194 #define S5P_LCD1_LOWPWR 0x1394 185 #define S5P_LCD1_LOWPWR 0x1394
195 186
196 /* Only for Exynos4x12 */ !! 187 /* Only for EXYNOS4x12 */
197 #define S5P_ISP_ARM_LOWPWR 188 #define S5P_ISP_ARM_LOWPWR 0x1050
198 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 189 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054
199 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 190 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058
200 #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 191 #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110
201 #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 192 #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114
202 #define S5P_CMU_RESET_COREBLK_LOWPWR 193 #define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C
203 #define S5P_MPLLUSER_SYSCLK_LOWPWR 194 #define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130
204 #define S5P_CMU_CLKSTOP_ISP_LOWPWR 195 #define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154
205 #define S5P_CMU_RESET_ISP_LOWPWR 196 #define S5P_CMU_RESET_ISP_LOWPWR 0x1174
206 #define S5P_TOP_BUS_COREBLK_LOWPWR 197 #define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190
207 #define S5P_TOP_RETENTION_COREBLK_LOWPWR 198 #define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194
208 #define S5P_TOP_PWR_COREBLK_LOWPWR 199 #define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198
209 #define S5P_OSCCLK_GATE_LOWPWR 200 #define S5P_OSCCLK_GATE_LOWPWR 0x11A4
210 #define S5P_LOGIC_RESET_COREBLK_LOWPWR 201 #define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0
211 #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 202 #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4
212 #define S5P_HSI_MEM_LOWPWR 203 #define S5P_HSI_MEM_LOWPWR 0x11C4
213 #define S5P_ROTATOR_MEM_LOWPWR 204 #define S5P_ROTATOR_MEM_LOWPWR 0x11DC
214 #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 205 #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C
215 #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 206 #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250
216 #define S5P_GPIO_MODE_COREBLK_LOWPWR 207 #define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320
217 #define S5P_TOP_ASB_RESET_LOWPWR 208 #define S5P_TOP_ASB_RESET_LOWPWR 0x1344
218 #define S5P_TOP_ASB_ISOLATION_LOWPWR 209 #define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348
219 #define S5P_ISP_LOWPWR 210 #define S5P_ISP_LOWPWR 0x1394
220 #define S5P_DRAM_FREQ_DOWN_LOWPWR 211 #define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0
221 #define S5P_DDRPHY_DLLOFF_LOWPWR 212 #define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4
222 #define S5P_CMU_SYSCLK_ISP_LOWPWR 213 #define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8
223 #define S5P_CMU_SYSCLK_GPS_LOWPWR 214 #define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC
224 #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 215 #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0
225 216
226 #define S5P_ARM_L2_0_OPTION 217 #define S5P_ARM_L2_0_OPTION 0x2608
227 #define S5P_ARM_L2_1_OPTION 218 #define S5P_ARM_L2_1_OPTION 0x2628
228 #define S5P_ONENAND_MEM_OPTION 219 #define S5P_ONENAND_MEM_OPTION 0x2E08
229 #define S5P_HSI_MEM_OPTION 220 #define S5P_HSI_MEM_OPTION 0x2E28
230 #define S5P_G2D_ACP_MEM_OPTION 221 #define S5P_G2D_ACP_MEM_OPTION 0x2E48
231 #define S5P_USBOTG_MEM_OPTION 222 #define S5P_USBOTG_MEM_OPTION 0x2E68
232 #define S5P_HSMMC_MEM_OPTION 223 #define S5P_HSMMC_MEM_OPTION 0x2E88
233 #define S5P_CSSYS_MEM_OPTION 224 #define S5P_CSSYS_MEM_OPTION 0x2EA8
234 #define S5P_SECSS_MEM_OPTION 225 #define S5P_SECSS_MEM_OPTION 0x2EC8
235 #define S5P_ROTATOR_MEM_OPTION 226 #define S5P_ROTATOR_MEM_OPTION 0x2F48
236 227
237 /* Only for Exynos4412 */ !! 228 /* Only for EXYNOS4412 */
238 #define S5P_ARM_CORE2_LOWPWR 229 #define S5P_ARM_CORE2_LOWPWR 0x1020
239 #define S5P_DIS_IRQ_CORE2 230 #define S5P_DIS_IRQ_CORE2 0x1024
240 #define S5P_DIS_IRQ_CENTRAL2 231 #define S5P_DIS_IRQ_CENTRAL2 0x1028
241 #define S5P_ARM_CORE3_LOWPWR 232 #define S5P_ARM_CORE3_LOWPWR 0x1030
242 #define S5P_DIS_IRQ_CORE3 233 #define S5P_DIS_IRQ_CORE3 0x1034
243 #define S5P_DIS_IRQ_CENTRAL3 234 #define S5P_DIS_IRQ_CENTRAL3 0x1038
244 235
245 /* Only for Exynos3XXX */ !! 236 /* Only for EXYNOS3XXX */
246 #define EXYNOS3_ARM_CORE0_SYS_PWR_REG 237 #define EXYNOS3_ARM_CORE0_SYS_PWR_REG 0x1000
247 #define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PW 238 #define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
248 #define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_ 239 #define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
249 #define EXYNOS3_ARM_CORE1_SYS_PWR_REG 240 #define EXYNOS3_ARM_CORE1_SYS_PWR_REG 0x1010
250 #define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PW 241 #define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
251 #define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_ 242 #define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
252 #define EXYNOS3_ISP_ARM_SYS_PWR_REG 243 #define EXYNOS3_ISP_ARM_SYS_PWR_REG 0x1050
253 #define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_ 244 #define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
254 #define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PW 245 #define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
255 #define EXYNOS3_ARM_COMMON_SYS_PWR_REG 246 #define EXYNOS3_ARM_COMMON_SYS_PWR_REG 0x1080
256 #define EXYNOS3_ARM_L2_SYS_PWR_REG 247 #define EXYNOS3_ARM_L2_SYS_PWR_REG 0x10C0
257 #define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 248 #define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
258 #define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 249 #define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
259 #define EXYNOS3_CMU_RESET_SYS_PWR_REG 250 #define EXYNOS3_CMU_RESET_SYS_PWR_REG 0x110C
260 #define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_R 251 #define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG 0x1110
261 #define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_R 252 #define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG 0x1114
262 #define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 253 #define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 0x111C
263 #define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 254 #define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 0x1120
264 #define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 255 #define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 0x1124
265 #define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 256 #define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 0x1128
266 #define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 257 #define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 0x112C
267 #define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 258 #define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1130
268 #define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 259 #define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1134
269 #define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 260 #define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 0x1138
270 #define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 261 #define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140
271 #define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 262 #define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148
272 #define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 263 #define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C
273 #define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 264 #define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150
274 #define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 265 #define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1154
275 #define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 266 #define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158
276 #define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 267 #define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 0x1160
277 #define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 268 #define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 0x1168
278 #define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 269 #define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 0x116C
279 #define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 270 #define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 0x1170
280 #define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 271 #define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 0x1174
281 #define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 272 #define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178
282 #define EXYNOS3_TOP_BUS_SYS_PWR_REG 273 #define EXYNOS3_TOP_BUS_SYS_PWR_REG 0x1180
283 #define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 274 #define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 0x1184
284 #define EXYNOS3_TOP_PWR_SYS_PWR_REG 275 #define EXYNOS3_TOP_PWR_SYS_PWR_REG 0x1188
285 #define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 276 #define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 0x1190
286 #define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_ 277 #define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG 0x1194
287 #define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 278 #define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 0x1198
288 #define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 279 #define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 0x11A0
289 #define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 280 #define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 0x11A4
290 #define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_RE 281 #define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG 0x11B0
291 #define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_RE 282 #define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG 0x11B4
292 #define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 283 #define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
293 #define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_R 284 #define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204
294 #define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 285 #define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 0x1208
295 #define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 286 #define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218
296 #define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 287 #define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
297 #define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 288 #define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
298 #define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 289 #define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228
299 #define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 290 #define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C
300 #define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 291 #define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
301 #define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 292 #define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
302 #define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 293 #define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1238
303 #define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 294 #define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 0x1240
304 #define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 295 #define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 0x1260
305 #define EXYNOS3_XUSBXTI_SYS_PWR_REG 296 #define EXYNOS3_XUSBXTI_SYS_PWR_REG 0x1280
306 #define EXYNOS3_XXTI_SYS_PWR_REG 297 #define EXYNOS3_XXTI_SYS_PWR_REG 0x1284
307 #define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 298 #define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 0x12C0
308 #define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_ 299 #define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG 0x12C4
309 #define EXYNOS3_GPIO_MODE_SYS_PWR_REG 300 #define EXYNOS3_GPIO_MODE_SYS_PWR_REG 0x1300
310 #define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 301 #define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340
311 #define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 302 #define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 0x1344
312 #define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 303 #define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
313 #define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_ 304 #define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG 0x1350
314 #define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_ 305 #define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG 0x1354
315 #define EXYNOS3_CAM_SYS_PWR_REG 306 #define EXYNOS3_CAM_SYS_PWR_REG 0x1380
316 #define EXYNOS3_MFC_SYS_PWR_REG 307 #define EXYNOS3_MFC_SYS_PWR_REG 0x1388
317 #define EXYNOS3_G3D_SYS_PWR_REG 308 #define EXYNOS3_G3D_SYS_PWR_REG 0x138C
318 #define EXYNOS3_LCD0_SYS_PWR_REG 309 #define EXYNOS3_LCD0_SYS_PWR_REG 0x1390
319 #define EXYNOS3_ISP_SYS_PWR_REG 310 #define EXYNOS3_ISP_SYS_PWR_REG 0x1394
320 #define EXYNOS3_MAUDIO_SYS_PWR_REG 311 #define EXYNOS3_MAUDIO_SYS_PWR_REG 0x1398
321 #define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 312 #define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 0x13B0
322 #define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 313 #define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 0x13B4
323 #define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 314 #define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13B8
324 #define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 315 #define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 0x13C0
325 #define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 316 #define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 0x13C4
326 #define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 317 #define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 0x13C8
327 318
328 #define EXYNOS3_ARM_CORE0_OPTION 319 #define EXYNOS3_ARM_CORE0_OPTION 0x2008
329 #define EXYNOS3_ARM_CORE_OPTION(_nr) \ 320 #define EXYNOS3_ARM_CORE_OPTION(_nr) \
330 (EXYNOS3_ARM_CORE0_OPT 321 (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
331 322
332 #define EXYNOS3_ARM_COMMON_OPTION 323 #define EXYNOS3_ARM_COMMON_OPTION 0x2408
333 #define EXYNOS3_ARM_L2_OPTION 324 #define EXYNOS3_ARM_L2_OPTION 0x2608
334 #define EXYNOS3_TOP_PWR_OPTION 325 #define EXYNOS3_TOP_PWR_OPTION 0x2C48
335 #define EXYNOS3_CORE_TOP_PWR_OPTION 326 #define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8
336 #define EXYNOS3_XUSBXTI_DURATION 327 #define EXYNOS3_XUSBXTI_DURATION 0x341C
337 #define EXYNOS3_XXTI_DURATION 328 #define EXYNOS3_XXTI_DURATION 0x343C
338 #define EXYNOS3_EXT_REGULATOR_DURATION 329 #define EXYNOS3_EXT_REGULATOR_DURATION 0x361C
339 #define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 330 #define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 0x363C
340 #define XUSBXTI_DURATION 331 #define XUSBXTI_DURATION 0x00000BB8
341 #define XXTI_DURATION 332 #define XXTI_DURATION XUSBXTI_DURATION
342 #define EXT_REGULATOR_DURATION 333 #define EXT_REGULATOR_DURATION 0x00001D4C
343 #define EXT_REGULATOR_COREBLK_DURATION 334 #define EXT_REGULATOR_COREBLK_DURATION EXT_REGULATOR_DURATION
344 335
345 /* for XXX_OPTION */ 336 /* for XXX_OPTION */
346 #define EXYNOS3_OPTION_USE_SC_COUNTER 337 #define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0)
347 #define EXYNOS3_OPTION_USE_SC_FEEDBACK 338 #define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1)
348 #define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_ 339 #define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
349 340
350 /* For Exynos5 */ !! 341 /* For EXYNOS5 */
351 342
352 #define EXYNOS5_AUTO_WDTRESET_DISABLE 343 #define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408
353 #define EXYNOS5_MASK_WDTRESET_REQUEST 344 #define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C
354 #define EXYNOS5_USBDRD_PHY_CONTROL <<
355 #define EXYNOS5_DPTX_PHY_CONTROL <<
356 345
357 #define EXYNOS5_USE_RETENTION 346 #define EXYNOS5_USE_RETENTION BIT(4)
358 #define EXYNOS5_SYS_WDTRESET 347 #define EXYNOS5_SYS_WDTRESET (1 << 20)
359 348
360 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 349 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000
361 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PW 350 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004
362 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_ 351 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008
363 #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 352 #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010
364 #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PW 353 #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014
365 #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_ 354 #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018
366 #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 355 #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040
367 #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_P 356 #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048
368 #define EXYNOS5_ISP_ARM_SYS_PWR_REG 357 #define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050
369 #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_ 358 #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054
370 #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PW 359 #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058
371 #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 360 #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080
372 #define EXYNOS5_ARM_L2_SYS_PWR_REG 361 #define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0
373 #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 362 #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100
374 #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 363 #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104
375 #define EXYNOS5_CMU_RESET_SYS_PWR_REG 364 #define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C
376 #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_RE 365 #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120
377 #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_RE 366 #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124
378 #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 367 #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C
379 #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 368 #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130
380 #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 369 #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134
381 #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 370 #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138
382 #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 371 #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140
383 #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 372 #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144
384 #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 373 #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148
385 #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 374 #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C
386 #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 375 #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150
387 #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 376 #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154
388 #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 377 #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164
389 #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 378 #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170
390 #define EXYNOS5_TOP_BUS_SYS_PWR_REG 379 #define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180
391 #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 380 #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184
392 #define EXYNOS5_TOP_PWR_SYS_PWR_REG 381 #define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188
393 #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 382 #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190
394 #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_R 383 #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194
395 #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 384 #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198
396 #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 385 #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0
397 #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 386 #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4
398 #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 387 #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0
399 #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 388 #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4
400 #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 389 #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0
401 #define EXYNOS5_G2D_MEM_SYS_PWR_REG 390 #define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8
402 #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 391 #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC
403 #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 392 #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0
404 #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 393 #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4
405 #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 394 #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8
406 #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 395 #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC
407 #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 396 #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0
408 #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 397 #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4
409 #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 398 #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8
410 #define EXYNOS5_HSI_MEM_SYS_PWR_REG 399 #define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC
411 #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 400 #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4
412 #define EXYNOS5_SATA_MEM_SYS_PWR_REG 401 #define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC
413 #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 402 #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200
414 #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 403 #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204
415 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 404 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220
416 #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 405 #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224
417 #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 406 #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228
418 #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 407 #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C
419 #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 408 #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230
420 #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 409 #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234
421 #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 410 #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238
422 #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_ 411 #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C
423 #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 412 #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240
424 #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_R 413 #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250
425 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 414 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260
426 #define EXYNOS5_XUSBXTI_SYS_PWR_REG 415 #define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280
427 #define EXYNOS5_XXTI_SYS_PWR_REG 416 #define EXYNOS5_XXTI_SYS_PWR_REG 0x1284
428 #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 417 #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0
429 #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 418 #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300
430 #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 419 #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320
431 #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 420 #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340
432 #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 421 #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344
433 #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 422 #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348
434 #define EXYNOS5_GSCL_SYS_PWR_REG 423 #define EXYNOS5_GSCL_SYS_PWR_REG 0x1400
435 #define EXYNOS5_ISP_SYS_PWR_REG 424 #define EXYNOS5_ISP_SYS_PWR_REG 0x1404
436 #define EXYNOS5_MFC_SYS_PWR_REG 425 #define EXYNOS5_MFC_SYS_PWR_REG 0x1408
437 #define EXYNOS5_G3D_SYS_PWR_REG 426 #define EXYNOS5_G3D_SYS_PWR_REG 0x140C
438 #define EXYNOS5_DISP1_SYS_PWR_REG 427 #define EXYNOS5_DISP1_SYS_PWR_REG 0x1414
439 #define EXYNOS5_MAU_SYS_PWR_REG 428 #define EXYNOS5_MAU_SYS_PWR_REG 0x1418
440 #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 429 #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480
441 #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 430 #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484
442 #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 431 #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488
443 #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 432 #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C
444 #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 433 #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494
445 #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 434 #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498
446 #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 435 #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0
447 #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 436 #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4
448 #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 437 #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8
449 #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 438 #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC
450 #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 439 #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4
451 #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 440 #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8
452 #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 441 #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580
453 #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 442 #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584
454 #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 443 #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588
455 #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 444 #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C
456 #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 445 #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594
457 #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 446 #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598
458 447
459 #define EXYNOS5_ARM_CORE0_OPTION 448 #define EXYNOS5_ARM_CORE0_OPTION 0x2008
460 #define EXYNOS5_ARM_CORE1_OPTION 449 #define EXYNOS5_ARM_CORE1_OPTION 0x2088
461 #define EXYNOS5_FSYS_ARM_OPTION 450 #define EXYNOS5_FSYS_ARM_OPTION 0x2208
462 #define EXYNOS5_ISP_ARM_OPTION 451 #define EXYNOS5_ISP_ARM_OPTION 0x2288
463 #define EXYNOS5_ARM_COMMON_OPTION 452 #define EXYNOS5_ARM_COMMON_OPTION 0x2408
464 #define EXYNOS5_ARM_L2_OPTION 453 #define EXYNOS5_ARM_L2_OPTION 0x2608
465 #define EXYNOS5_TOP_PWR_OPTION 454 #define EXYNOS5_TOP_PWR_OPTION 0x2C48
466 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 455 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8
467 #define EXYNOS5_JPEG_MEM_OPTION 456 #define EXYNOS5_JPEG_MEM_OPTION 0x2F48
468 #define EXYNOS5_GSCL_OPTION 457 #define EXYNOS5_GSCL_OPTION 0x4008
469 #define EXYNOS5_ISP_OPTION 458 #define EXYNOS5_ISP_OPTION 0x4028
470 #define EXYNOS5_MFC_OPTION 459 #define EXYNOS5_MFC_OPTION 0x4048
471 #define EXYNOS5_G3D_OPTION 460 #define EXYNOS5_G3D_OPTION 0x4068
472 #define EXYNOS5_DISP1_OPTION 461 #define EXYNOS5_DISP1_OPTION 0x40A8
473 #define EXYNOS5_MAU_OPTION 462 #define EXYNOS5_MAU_OPTION 0x40C8
474 463
475 #define EXYNOS5_USE_SC_FEEDBACK 464 #define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
476 #define EXYNOS5_USE_SC_COUNTER 465 #define EXYNOS5_USE_SC_COUNTER (1 << 0)
477 466
478 #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN 467 #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
479 468
480 #define EXYNOS5_OPTION_USE_STANDBYWFE 469 #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
481 #define EXYNOS5_OPTION_USE_STANDBYWFI 470 #define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
482 471
483 #define EXYNOS5_OPTION_USE_RETENTION 472 #define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
484 473
485 #define EXYNOS5420_SWRESET_KFC_SEL 474 #define EXYNOS5420_SWRESET_KFC_SEL 0x3
486 475
487 /* Only for Exynos5420 */ !! 476 /* Only for EXYNOS5420 */
488 #define EXYNOS5420_L2RSTDISABLE_VALUE 477 #define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3)
489 478
490 #define EXYNOS5420_LPI_MASK 479 #define EXYNOS5420_LPI_MASK 0x0004
491 #define EXYNOS5420_LPI_MASK1 480 #define EXYNOS5420_LPI_MASK1 0x0008
492 #define EXYNOS5420_UFS 481 #define EXYNOS5420_UFS BIT(8)
493 #define EXYNOS5420_ATB_KFC 482 #define EXYNOS5420_ATB_KFC BIT(13)
494 #define EXYNOS5420_ATB_ISP_ARM 483 #define EXYNOS5420_ATB_ISP_ARM BIT(19)
495 #define EXYNOS5420_EMULATION 484 #define EXYNOS5420_EMULATION BIT(31)
496 485
497 #define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 486 #define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100
498 #define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBY 487 #define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104
499 #define EXYNOS5420_UP_SCHEDULER 488 #define EXYNOS5420_UP_SCHEDULER 0x0120
500 #define SPREAD_ENABLE 489 #define SPREAD_ENABLE 0xF
501 #define SPREAD_USE_STANDWFI 490 #define SPREAD_USE_STANDWFI 0xF
502 491
503 #define EXYNOS5420_KFC_CORE_RESET0 492 #define EXYNOS5420_KFC_CORE_RESET0 BIT(8)
504 #define EXYNOS5420_KFC_ETM_RESET0 493 #define EXYNOS5420_KFC_ETM_RESET0 BIT(20)
505 494
506 #define EXYNOS5420_KFC_CORE_RESET(_nr) 495 #define EXYNOS5420_KFC_CORE_RESET(_nr) \
507 ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5 496 ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr))
508 497
509 #define EXYNOS5420_USBDRD1_PHY_CONTROL <<
510 #define EXYNOS5420_MIPI_PHY_CONTROL(n) <<
511 #define EXYNOS5420_DPTX_PHY_CONTROL <<
512 #define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 498 #define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020
513 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS 499 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024
514 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_S 500 #define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028
515 #define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 501 #define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 0x1030
516 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS 502 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG 0x1034
517 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_S 503 #define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG 0x1038
518 #define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 504 #define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 0x1040
519 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS 505 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG 0x1044
520 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_S 506 #define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048
521 #define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 507 #define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 0x1050
522 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS 508 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG 0x1054
523 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_S 509 #define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058
524 #define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 510 #define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 0x1060
525 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS 511 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG 0x1064
526 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_S 512 #define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068
527 #define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 513 #define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 0x1070
528 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS 514 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG 0x1074
529 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_S 515 #define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078
530 #define EXYNOS5420_ISP_ARM_SYS_PWR_REG 516 #define EXYNOS5420_ISP_ARM_SYS_PWR_REG 0x1090
531 #define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_P 517 #define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1094
532 #define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS 518 #define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1098
533 #define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 519 #define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 0x10A0
534 #define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 520 #define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 0x10B0
535 #define EXYNOS5420_KFC_L2_SYS_PWR_REG 521 #define EXYNOS5420_KFC_L2_SYS_PWR_REG 0x10D0
536 #define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 522 #define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 0x1158
537 #define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 523 #define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 0x115C
538 #define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 524 #define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 0x1160
539 #define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 525 #define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 0x1174
540 #define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 526 #define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178
541 #define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 527 #define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8
542 #define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 528 #define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC
543 #define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_ 529 #define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208
544 #define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_ 530 #define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210
545 #define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_ 531 #define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214
546 #define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_ 532 #define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1218
547 #define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_ 533 #define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG 0x121C
548 #define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_ 534 #define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1220
549 #define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_R 535 #define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG 0x1224
550 #define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_ 536 #define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1228
551 #define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_ 537 #define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG 0x122C
552 #define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_R 538 #define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG 0x1230
553 #define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_ 539 #define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG 0x1234
554 #define EXYNOS5420_DISP1_SYS_PWR_REG 540 #define EXYNOS5420_DISP1_SYS_PWR_REG 0x1410
555 #define EXYNOS5420_MAU_SYS_PWR_REG 541 #define EXYNOS5420_MAU_SYS_PWR_REG 0x1414
556 #define EXYNOS5420_G2D_SYS_PWR_REG 542 #define EXYNOS5420_G2D_SYS_PWR_REG 0x1418
557 #define EXYNOS5420_MSC_SYS_PWR_REG 543 #define EXYNOS5420_MSC_SYS_PWR_REG 0x141C
558 #define EXYNOS5420_FSYS_SYS_PWR_REG 544 #define EXYNOS5420_FSYS_SYS_PWR_REG 0x1420
559 #define EXYNOS5420_FSYS2_SYS_PWR_REG 545 #define EXYNOS5420_FSYS2_SYS_PWR_REG 0x1424
560 #define EXYNOS5420_PSGEN_SYS_PWR_REG 546 #define EXYNOS5420_PSGEN_SYS_PWR_REG 0x1428
561 #define EXYNOS5420_PERIC_SYS_PWR_REG 547 #define EXYNOS5420_PERIC_SYS_PWR_REG 0x142C
562 #define EXYNOS5420_WCORE_SYS_PWR_REG 548 #define EXYNOS5420_WCORE_SYS_PWR_REG 0x1430
563 #define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_R 549 #define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1490
564 #define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 550 #define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1494
565 #define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 551 #define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 0x1498
566 #define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 552 #define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 0x149C
567 #define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_RE 553 #define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG 0x14A0
568 #define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_R 554 #define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG 0x14A4
569 #define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_R 555 #define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG 0x14A8
570 #define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_R 556 #define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG 0x14AC
571 #define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_R 557 #define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG 0x14B0
572 #define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_R 558 #define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG 0x14BC
573 #define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_RE 559 #define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D0
574 #define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 560 #define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D4
575 #define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 561 #define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 0x14D8
576 #define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 562 #define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 0x14DC
577 #define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 563 #define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 0x14E0
578 #define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_RE 564 #define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG 0x14E4
579 #define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_RE 565 #define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG 0x14E8
580 #define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_RE 566 #define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG 0x14EC
581 #define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_RE 567 #define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG 0x14F0
582 #define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SY 568 #define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG 0x14F4
583 #define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 569 #define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 0x1570
584 #define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 570 #define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 0x1574
585 #define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 571 #define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 0x1578
586 #define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 572 #define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 0x157C
587 #define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 573 #define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 0x1590
588 #define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 574 #define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 0x1594
589 #define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 575 #define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 0x1598
590 #define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 576 #define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C
591 #define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 577 #define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0
592 #define EXYNOS5420_SFR_AXI_CGDIS1 578 #define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4
593 #define EXYNOS5420_ARM_COMMON_OPTION 579 #define EXYNOS5420_ARM_COMMON_OPTION 0x2508
594 #define EXYNOS5420_KFC_COMMON_OPTION 580 #define EXYNOS5420_KFC_COMMON_OPTION 0x2588
595 #define EXYNOS5420_LOGIC_RESET_DURATION3 581 #define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C
596 582
597 #define EXYNOS5420_PAD_RET_GPIO_OPTION 583 #define EXYNOS5420_PAD_RET_GPIO_OPTION 0x30C8
598 #define EXYNOS5420_PAD_RET_UART_OPTION 584 #define EXYNOS5420_PAD_RET_UART_OPTION 0x30E8
599 #define EXYNOS5420_PAD_RET_MMCA_OPTION 585 #define EXYNOS5420_PAD_RET_MMCA_OPTION 0x3108
600 #define EXYNOS5420_PAD_RET_MMCB_OPTION 586 #define EXYNOS5420_PAD_RET_MMCB_OPTION 0x3128
601 #define EXYNOS5420_PAD_RET_MMCC_OPTION 587 #define EXYNOS5420_PAD_RET_MMCC_OPTION 0x3148
602 #define EXYNOS5420_PAD_RET_HSI_OPTION 588 #define EXYNOS5420_PAD_RET_HSI_OPTION 0x3168
603 #define EXYNOS5420_PAD_RET_SPI_OPTION 589 #define EXYNOS5420_PAD_RET_SPI_OPTION 0x31C8
604 #define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 590 #define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 0x31E8
605 #define EXYNOS_PAD_RET_DRAM_OPTION 591 #define EXYNOS_PAD_RET_DRAM_OPTION 0x3008
606 #define EXYNOS_PAD_RET_MAUDIO_OPTION 592 #define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028
607 #define EXYNOS_PAD_RET_JTAG_OPTION 593 #define EXYNOS_PAD_RET_JTAG_OPTION 0x3048
608 #define EXYNOS_PAD_RET_EBIA_OPTION 594 #define EXYNOS_PAD_RET_EBIA_OPTION 0x3188
609 #define EXYNOS_PAD_RET_EBIB_OPTION 595 #define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8
610 596
611 #define EXYNOS5420_FSYS2_OPTION 597 #define EXYNOS5420_FSYS2_OPTION 0x4168
612 #define EXYNOS5420_PSGEN_OPTION 598 #define EXYNOS5420_PSGEN_OPTION 0x4188
613 599
>> 600 /* For EXYNOS_CENTRAL_SEQ_OPTION */
>> 601 #define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 BIT(16)
>> 602 #define EXYNOS5_USE_STANDBYWFI_ARM_CORE1 BUT(17)
>> 603 #define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 BIT(24)
>> 604 #define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 BIT(25)
>> 605
614 #define EXYNOS5420_ARM_USE_STANDBY_WFI0 606 #define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4)
615 #define EXYNOS5420_ARM_USE_STANDBY_WFI1 607 #define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5)
616 #define EXYNOS5420_ARM_USE_STANDBY_WFI2 608 #define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6)
617 #define EXYNOS5420_ARM_USE_STANDBY_WFI3 609 #define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7)
618 #define EXYNOS5420_KFC_USE_STANDBY_WFI0 610 #define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8)
619 #define EXYNOS5420_KFC_USE_STANDBY_WFI1 611 #define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9)
620 #define EXYNOS5420_KFC_USE_STANDBY_WFI2 612 #define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10)
621 #define EXYNOS5420_KFC_USE_STANDBY_WFI3 613 #define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11)
622 #define EXYNOS5420_ARM_USE_STANDBY_WFE0 614 #define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16)
623 #define EXYNOS5420_ARM_USE_STANDBY_WFE1 615 #define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17)
624 #define EXYNOS5420_ARM_USE_STANDBY_WFE2 616 #define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18)
625 #define EXYNOS5420_ARM_USE_STANDBY_WFE3 617 #define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19)
626 #define EXYNOS5420_KFC_USE_STANDBY_WFE0 618 #define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20)
627 #define EXYNOS5420_KFC_USE_STANDBY_WFE1 619 #define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21)
628 #define EXYNOS5420_KFC_USE_STANDBY_WFE2 620 #define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22)
629 #define EXYNOS5420_KFC_USE_STANDBY_WFE3 621 #define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23)
630 622
631 #define DUR_WAIT_RESET 623 #define DUR_WAIT_RESET 0xF
632 624
633 #define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNO 625 #define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \
634 | EXY 626 | EXYNOS5420_ARM_USE_STANDBY_WFI1 \
635 | EXY 627 | EXYNOS5420_ARM_USE_STANDBY_WFI2 \
636 | EXY 628 | EXYNOS5420_ARM_USE_STANDBY_WFI3 \
637 | EXY 629 | EXYNOS5420_KFC_USE_STANDBY_WFI0 \
638 | EXY 630 | EXYNOS5420_KFC_USE_STANDBY_WFI1 \
639 | EXY 631 | EXYNOS5420_KFC_USE_STANDBY_WFI2 \
640 | EXY 632 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
641 633
642 /* For Exynos5433 */ !! 634 /* For EXYNOS5433 */
643 #define EXYNOS5433_EINT_WAKEUP_MASK <<
644 #define EXYNOS5433_USBHOST30_PHY_CONTROL <<
645 #define EXYNOS5433_PAD_RETENTION_AUD_OPTION 635 #define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028)
646 #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION 636 #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION (0x30C8)
647 #define EXYNOS5433_PAD_RETENTION_TOP_OPTION 637 #define EXYNOS5433_PAD_RETENTION_TOP_OPTION (0x3108)
648 #define EXYNOS5433_PAD_RETENTION_UART_OPTION 638 #define EXYNOS5433_PAD_RETENTION_UART_OPTION (0x3128)
649 #define EXYNOS5433_PAD_RETENTION_MMC0_OPTION 639 #define EXYNOS5433_PAD_RETENTION_MMC0_OPTION (0x3148)
650 #define EXYNOS5433_PAD_RETENTION_MMC1_OPTION 640 #define EXYNOS5433_PAD_RETENTION_MMC1_OPTION (0x3168)
651 #define EXYNOS5433_PAD_RETENTION_EBIA_OPTION 641 #define EXYNOS5433_PAD_RETENTION_EBIA_OPTION (0x3188)
652 #define EXYNOS5433_PAD_RETENTION_EBIB_OPTION 642 #define EXYNOS5433_PAD_RETENTION_EBIB_OPTION (0x31A8)
653 #define EXYNOS5433_PAD_RETENTION_SPI_OPTION 643 #define EXYNOS5433_PAD_RETENTION_SPI_OPTION (0x31C8)
654 #define EXYNOS5433_PAD_RETENTION_MIF_OPTION 644 #define EXYNOS5433_PAD_RETENTION_MIF_OPTION (0x31E8)
655 #define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION 645 #define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION (0x3228)
656 #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTIO 646 #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION (0x3248)
657 #define EXYNOS5433_PAD_RETENTION_UFS_OPTION 647 #define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268)
658 #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPT 648 #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8)
659 <<
660 /* For Tensor GS101 */ <<
661 #define GS101_SYSIP_DAT0 <<
662 #define GS101_SYSTEM_CONFIGURATION <<
663 #define GS101_PHY_CTRL_USB20 <<
664 #define GS101_PHY_CTRL_USBDP <<
665 649
666 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ 650 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
667 651
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