1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1
2 /*
3 * include/linux/spi/mxs-spi.h
4 *
5 * Freescale i.MX233/i.MX28 SPI controller reg
6 *
7 * Copyright 2008 Embedded Alley Solutions, In
8 * Copyright 2009-2011 Freescale Semiconductor
9 */
10
11 #ifndef __LINUX_SPI_MXS_SPI_H__
12 #define __LINUX_SPI_MXS_SPI_H__
13
14 #include <linux/dmaengine.h>
15
16 #define ssp_is_old(host) ((host)->devid
17
18 /* SSP registers */
19 #define HW_SSP_CTRL0
20 #define BM_SSP_CTRL0_RUN
21 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK
22 #define BM_SSP_CTRL0_LOCK_CS
23 #define BM_SSP_CTRL0_IGNORE_CRC
24 #define BM_SSP_CTRL0_READ
25 #define BM_SSP_CTRL0_DATA_XFER
26 #define BP_SSP_CTRL0_BUS_WIDTH
27 #define BM_SSP_CTRL0_BUS_WIDTH
28 #define BM_SSP_CTRL0_WAIT_FOR_IRQ
29 #define BM_SSP_CTRL0_WAIT_FOR_CMD
30 #define BM_SSP_CTRL0_LONG_RESP
31 #define BM_SSP_CTRL0_GET_RESP
32 #define BM_SSP_CTRL0_ENABLE
33 #define BP_SSP_CTRL0_XFER_COUNT
34 #define BM_SSP_CTRL0_XFER_COUNT
35 #define HW_SSP_CMD0
36 #define BM_SSP_CMD0_DBL_DATA_RATE_EN
37 #define BM_SSP_CMD0_SLOW_CLKING_EN
38 #define BM_SSP_CMD0_CONT_CLKING_EN
39 #define BM_SSP_CMD0_APPEND_8CYC
40 #define BP_SSP_CMD0_BLOCK_SIZE
41 #define BM_SSP_CMD0_BLOCK_SIZE
42 #define BP_SSP_CMD0_BLOCK_COUNT
43 #define BM_SSP_CMD0_BLOCK_COUNT
44 #define BP_SSP_CMD0_CMD
45 #define BM_SSP_CMD0_CMD
46 #define HW_SSP_CMD1
47 #define HW_SSP_XFER_SIZE
48 #define HW_SSP_BLOCK_SIZE
49 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT
50 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT
51 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE
52 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE
53 #define HW_SSP_TIMING(h)
54 #define BP_SSP_TIMING_TIMEOUT
55 #define BM_SSP_TIMING_TIMEOUT
56 #define BP_SSP_TIMING_CLOCK_DIVIDE
57 #define BM_SSP_TIMING_CLOCK_DIVIDE
58 #define BF_SSP_TIMING_CLOCK_DIVIDE(v)
59 (((v) << 8) & BM_SSP_T
60 #define BP_SSP_TIMING_CLOCK_RATE
61 #define BM_SSP_TIMING_CLOCK_RATE
62 #define BF_SSP_TIMING_CLOCK_RATE(v)
63 (((v) << 0) & BM_SSP_T
64 #define HW_SSP_CTRL1(h)
65 #define BM_SSP_CTRL1_SDIO_IRQ
66 #define BM_SSP_CTRL1_SDIO_IRQ_EN
67 #define BM_SSP_CTRL1_RESP_ERR_IRQ
68 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN
69 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
70 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
71 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
72 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
73 #define BM_SSP_CTRL1_DATA_CRC_IRQ
74 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN
75 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
76 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN
77 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
78 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
79 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
80 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN
81 #define BM_SSP_CTRL1_DMA_ENABLE
82 #define BM_SSP_CTRL1_PHASE
83 #define BM_SSP_CTRL1_POLARITY
84 #define BP_SSP_CTRL1_WORD_LENGTH
85 #define BM_SSP_CTRL1_WORD_LENGTH
86 #define BF_SSP_CTRL1_WORD_LENGTH(v)
87 (((v) << 4) & BM_SSP_C
88 #define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS
89 #define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS
90 #define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BIT
91 #define BP_SSP_CTRL1_SSP_MODE
92 #define BM_SSP_CTRL1_SSP_MODE
93 #define BF_SSP_CTRL1_SSP_MODE(v)
94 (((v) << 0) & BM_SSP_C
95 #define BV_SSP_CTRL1_SSP_MODE__SPI
96 #define BV_SSP_CTRL1_SSP_MODE__SSI
97 #define BV_SSP_CTRL1_SSP_MODE__SD_MMC
98 #define BV_SSP_CTRL1_SSP_MODE__MS
99
100 #define HW_SSP_DATA(h)
101
102 #define HW_SSP_SDRESP0(h)
103 #define HW_SSP_SDRESP1(h)
104 #define HW_SSP_SDRESP2(h)
105 #define HW_SSP_SDRESP3(h)
106 #define HW_SSP_STATUS(h)
107 #define BM_SSP_STATUS_CARD_DETECT
108 #define BM_SSP_STATUS_SDIO_IRQ
109 #define BM_SSP_STATUS_FIFO_EMPTY
110
111 #define BF_SSP(value, field) (((value) << B
112
113 #define SSP_PIO_NUM 3
114
115 enum mxs_ssp_id {
116 IMX23_SSP,
117 IMX28_SSP,
118 };
119
120 struct mxs_ssp {
121 struct device *dev;
122 void __iomem *base;
123 struct clk *clk;
124 unsigned int clk_ra
125 enum mxs_ssp_id devid;
126
127 struct dma_chan *dmach
128 unsigned int dma_di
129 enum dma_transfer_direction slave_
130 u32 ssp_pi
131 };
132
133 void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp,
134
135 #endif /* __LINUX_SPI_MXS_SPI_H__ */
136
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