1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 #ifndef LINUX_SSB_PCICORE_H_
3 #define LINUX_SSB_PCICORE_H_
4
5 #include <linux/types.h>
6
7 struct pci_dev;
8
9
10 #ifdef CONFIG_SSB_DRIVER_PCICORE
11
12 /* PCI core registers. */
13 #define SSB_PCICORE_CTL 0x0000
14 #define SSB_PCICORE_CTL_RST_OE 0x0000
15 #define SSB_PCICORE_CTL_RST 0x0000
16 #define SSB_PCICORE_CTL_CLK_OE 0x0000
17 #define SSB_PCICORE_CTL_CLK 0x0000
18 #define SSB_PCICORE_ARBCTL 0x0010
19 #define SSB_PCICORE_ARBCTL_INTERN 0x0000
20 #define SSB_PCICORE_ARBCTL_EXTERN 0x0000
21 #define SSB_PCICORE_ARBCTL_PARKID 0x0000
22 #define SSB_PCICORE_ARBCTL_PARKID_LAST
23 #define SSB_PCICORE_ARBCTL_PARKID_4710
24 #define SSB_PCICORE_ARBCTL_PARKID_EXT0
25 #define SSB_PCICORE_ARBCTL_PARKID_EXT1
26 #define SSB_PCICORE_ISTAT 0x0020
27 #define SSB_PCICORE_ISTAT_INTA 0x0000
28 #define SSB_PCICORE_ISTAT_INTB 0x0000
29 #define SSB_PCICORE_ISTAT_SERR 0x0000
30 #define SSB_PCICORE_ISTAT_PERR 0x0000
31 #define SSB_PCICORE_ISTAT_PME 0x0000
32 #define SSB_PCICORE_IMASK 0x0024
33 #define SSB_PCICORE_IMASK_INTA 0x0000
34 #define SSB_PCICORE_IMASK_INTB 0x0000
35 #define SSB_PCICORE_IMASK_SERR 0x0000
36 #define SSB_PCICORE_IMASK_PERR 0x0000
37 #define SSB_PCICORE_IMASK_PME 0x0000
38 #define SSB_PCICORE_MBOX 0x0028
39 #define SSB_PCICORE_MBOX_F0_0 0x0000
40 #define SSB_PCICORE_MBOX_F0_1 0x0000
41 #define SSB_PCICORE_MBOX_F1_0 0x0000
42 #define SSB_PCICORE_MBOX_F1_1 0x0000
43 #define SSB_PCICORE_MBOX_F2_0 0x0000
44 #define SSB_PCICORE_MBOX_F2_1 0x0000
45 #define SSB_PCICORE_MBOX_F3_0 0x0000
46 #define SSB_PCICORE_MBOX_F3_1 0x0000
47 #define SSB_PCICORE_BCAST_ADDR 0x0050
48 #define SSB_PCICORE_BCAST_ADDR_MASK 0x0000
49 #define SSB_PCICORE_BCAST_DATA 0x0054
50 #define SSB_PCICORE_GPIO_IN 0x0060
51 #define SSB_PCICORE_GPIO_OUT 0x0064
52 #define SSB_PCICORE_GPIO_ENABLE 0x0068
53 #define SSB_PCICORE_GPIO_CTL 0x006C
54 #define SSB_PCICORE_SBTOPCI0 0x0100
55 #define SSB_PCICORE_SBTOPCI0_MASK 0xFC00
56 #define SSB_PCICORE_SBTOPCI1 0x0104
57 #define SSB_PCICORE_SBTOPCI1_MASK 0xFC00
58 #define SSB_PCICORE_SBTOPCI2 0x0108
59 #define SSB_PCICORE_SBTOPCI2_MASK 0xC000
60 #define SSB_PCICORE_PCICFG0 0x0400
61 #define SSB_PCICORE_PCICFG1 0x0500
62 #define SSB_PCICORE_PCICFG2 0x0600
63 #define SSB_PCICORE_PCICFG3 0x0700
64 #define SSB_PCICORE_SPROM(wordoffset) (0x080
65
66 /* SBtoPCIx */
67 #define SSB_PCICORE_SBTOPCI_MEM 0x0000
68 #define SSB_PCICORE_SBTOPCI_IO 0x0000
69 #define SSB_PCICORE_SBTOPCI_CFG0 0x0000
70 #define SSB_PCICORE_SBTOPCI_CFG1 0x0000
71 #define SSB_PCICORE_SBTOPCI_PREF 0x0000
72 #define SSB_PCICORE_SBTOPCI_BURST 0x0000
73 #define SSB_PCICORE_SBTOPCI_MRM 0x0000
74 #define SSB_PCICORE_SBTOPCI_RC 0x0000
75 #define SSB_PCICORE_SBTOPCI_RC_READ 0x0000
76 #define SSB_PCICORE_SBTOPCI_RC_READL 0x0000
77 #define SSB_PCICORE_SBTOPCI_RC_READM 0x0000
78
79
80 /* PCIcore specific boardflags */
81 #define SSB_PCICORE_BFL_NOPCI 0x0000
82
83
84 struct ssb_pcicore {
85 struct ssb_device *dev;
86 u8 setup_done:1;
87 u8 hostmode:1;
88 u8 cardbusmode:1;
89 };
90
91 extern void ssb_pcicore_init(struct ssb_pcicor
92
93 /* Enable IRQ routing for a specific device */
94 extern int ssb_pcicore_dev_irqvecs_enable(stru
95 stru
96
97 int ssb_pcicore_plat_dev_init(struct pci_dev *
98 int ssb_pcicore_pcibios_map_irq(const struct p
99
100
101 #else /* CONFIG_SSB_DRIVER_PCICORE */
102
103
104 struct ssb_pcicore {
105 };
106
107 static inline
108 void ssb_pcicore_init(struct ssb_pcicore *pc)
109 {
110 }
111
112 static inline
113 int ssb_pcicore_dev_irqvecs_enable(struct ssb_
114 struct ssb_
115 {
116 return 0;
117 }
118
119 static inline
120 int ssb_pcicore_plat_dev_init(struct pci_dev *
121 {
122 return -ENODEV;
123 }
124 static inline
125 int ssb_pcicore_pcibios_map_irq(const struct p
126 {
127 return -ENODEV;
128 }
129
130 #endif /* CONFIG_SSB_DRIVER_PCICORE */
131 #endif /* LINUX_SSB_PCICORE_H_ */
132
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