1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_T10_PI_H 2 #ifndef _LINUX_T10_PI_H
3 #define _LINUX_T10_PI_H 3 #define _LINUX_T10_PI_H
4 4
5 #include <linux/types.h> 5 #include <linux/types.h>
6 #include <linux/blk-mq.h> !! 6 #include <linux/blkdev.h>
7 7
8 /* 8 /*
9 * A T10 PI-capable target device can be forma 9 * A T10 PI-capable target device can be formatted with different
10 * protection schemes. Currently 0 through 3 10 * protection schemes. Currently 0 through 3 are defined:
11 * 11 *
12 * Type 0 is regular (unprotected) I/O 12 * Type 0 is regular (unprotected) I/O
13 * 13 *
14 * Type 1 defines the contents of the guard an 14 * Type 1 defines the contents of the guard and reference tags
15 * 15 *
16 * Type 2 defines the contents of the guard an 16 * Type 2 defines the contents of the guard and reference tags and
17 * uses 32-byte commands to seed the latter 17 * uses 32-byte commands to seed the latter
18 * 18 *
19 * Type 3 defines the contents of the guard ta 19 * Type 3 defines the contents of the guard tag only
20 */ 20 */
21 enum t10_dif_type { 21 enum t10_dif_type {
22 T10_PI_TYPE0_PROTECTION = 0x0, 22 T10_PI_TYPE0_PROTECTION = 0x0,
23 T10_PI_TYPE1_PROTECTION = 0x1, 23 T10_PI_TYPE1_PROTECTION = 0x1,
24 T10_PI_TYPE2_PROTECTION = 0x2, 24 T10_PI_TYPE2_PROTECTION = 0x2,
25 T10_PI_TYPE3_PROTECTION = 0x3, 25 T10_PI_TYPE3_PROTECTION = 0x3,
26 }; 26 };
27 27
28 /* 28 /*
29 * T10 Protection Information tuple. 29 * T10 Protection Information tuple.
30 */ 30 */
31 struct t10_pi_tuple { 31 struct t10_pi_tuple {
32 __be16 guard_tag; /* Checksum */ 32 __be16 guard_tag; /* Checksum */
33 __be16 app_tag; /* Opaque stor 33 __be16 app_tag; /* Opaque storage */
34 __be32 ref_tag; /* Target LBA 34 __be32 ref_tag; /* Target LBA or indirect LBA */
35 }; 35 };
36 36
37 #define T10_PI_APP_ESCAPE cpu_to_be16(0xffff) 37 #define T10_PI_APP_ESCAPE cpu_to_be16(0xffff)
38 #define T10_PI_REF_ESCAPE cpu_to_be32(0xffffff 38 #define T10_PI_REF_ESCAPE cpu_to_be32(0xffffffff)
39 39
40 static inline u32 t10_pi_ref_tag(struct reques 40 static inline u32 t10_pi_ref_tag(struct request *rq)
41 { 41 {
42 unsigned int shift = ilog2(queue_logic 42 unsigned int shift = ilog2(queue_logical_block_size(rq->q));
43 43
44 if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRIT !! 44 #ifdef CONFIG_BLK_DEV_INTEGRITY
45 rq->q->limits.integrity.interval_e !! 45 if (rq->q->integrity.interval_exp)
46 shift = rq->q->limits.integrit !! 46 shift = rq->q->integrity.interval_exp;
>> 47 #endif
47 return blk_rq_pos(rq) >> (shift - SECT 48 return blk_rq_pos(rq) >> (shift - SECTOR_SHIFT) & 0xffffffff;
48 } 49 }
49 50
50 struct crc64_pi_tuple { !! 51 extern const struct blk_integrity_profile t10_pi_type1_crc;
51 __be64 guard_tag; !! 52 extern const struct blk_integrity_profile t10_pi_type1_ip;
52 __be16 app_tag; !! 53 extern const struct blk_integrity_profile t10_pi_type3_crc;
53 __u8 ref_tag[6]; !! 54 extern const struct blk_integrity_profile t10_pi_type3_ip;
54 }; <<
55 <<
56 /** <<
57 * lower_48_bits() - return bits 0-47 of a num <<
58 * @n: the number we're accessing <<
59 */ <<
60 static inline u64 lower_48_bits(u64 n) <<
61 { <<
62 return n & ((1ull << 48) - 1); <<
63 } <<
64 <<
65 static inline u64 ext_pi_ref_tag(struct reques <<
66 { <<
67 unsigned int shift = ilog2(queue_logic <<
68 <<
69 if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRIT <<
70 rq->q->limits.integrity.interval_e <<
71 shift = rq->q->limits.integrit <<
72 return lower_48_bits(blk_rq_pos(rq) >> <<
73 } <<
74 55
75 #endif 56 #endif
76 57
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