1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * USB 338x super/high/full speed USB device c 3 * USB 338x super/high/full speed USB device controller.
4 * Unlike many such controllers, this one talk 4 * Unlike many such controllers, this one talks PCI.
5 * 5 *
6 * Copyright (C) 2002 NetChip Technology, Inc. 6 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
7 * Copyright (C) 2003 David Brownell 7 * Copyright (C) 2003 David Brownell
8 * Copyright (C) 2014 Ricardo Ribalda - Qtechn 8 * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
>> 9 *
>> 10 * This program is free software; you can redistribute it and/or modify
>> 11 * it under the terms of the GNU General Public License as published by
>> 12 * the Free Software Foundation; either version 2 of the License, or
>> 13 * (at your option) any later version.
>> 14 *
>> 15 * This program is distributed in the hope that it will be useful,
>> 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 18 * GNU General Public License for more details.
>> 19 *
9 */ 20 */
10 21
11 #ifndef __LINUX_USB_USB338X_H 22 #ifndef __LINUX_USB_USB338X_H
12 #define __LINUX_USB_USB338X_H 23 #define __LINUX_USB_USB338X_H
13 24
14 #include <linux/usb/net2280.h> 25 #include <linux/usb/net2280.h>
15 26
16 /* 27 /*
17 * Extra defined bits for net2280 registers 28 * Extra defined bits for net2280 registers
18 */ 29 */
19 #define SCRATCH 30 #define SCRATCH 0x0b
20 31
21 #define DEFECT7374_FSM_FIELD 32 #define DEFECT7374_FSM_FIELD 28
22 #define SUPER_SPEED 33 #define SUPER_SPEED 8
23 #define DMA_REQUEST_OUTSTANDING 34 #define DMA_REQUEST_OUTSTANDING 5
24 #define DMA_PAUSE_DONE_INTERRUPT 35 #define DMA_PAUSE_DONE_INTERRUPT 26
25 #define SET_ISOCHRONOUS_DELAY 36 #define SET_ISOCHRONOUS_DELAY 24
26 #define SET_SEL 37 #define SET_SEL 22
27 #define SUPER_SPEED_MODE 38 #define SUPER_SPEED_MODE 8
28 39
29 /*ep_cfg*/ 40 /*ep_cfg*/
30 #define MAX_BURST_SIZE 41 #define MAX_BURST_SIZE 24
31 #define EP_FIFO_BYTE_COUNT 42 #define EP_FIFO_BYTE_COUNT 16
32 #define IN_ENDPOINT_ENABLE 43 #define IN_ENDPOINT_ENABLE 14
33 #define IN_ENDPOINT_TYPE 44 #define IN_ENDPOINT_TYPE 12
34 #define OUT_ENDPOINT_ENABLE 45 #define OUT_ENDPOINT_ENABLE 10
35 #define OUT_ENDPOINT_TYPE 46 #define OUT_ENDPOINT_TYPE 8
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_END 47 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
37 BIT(IN_ENDPOIN 48 BIT(IN_ENDPOINT_ENABLE))
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_E 49 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
39 BIT(OUT_ENDPOI 50 BIT(OUT_ENDPOINT_ENABLE))
40 51
41 struct usb338x_usb_ext_regs { 52 struct usb338x_usb_ext_regs {
42 u32 usbclass; 53 u32 usbclass;
43 #define DEVICE_PROTOCOL 54 #define DEVICE_PROTOCOL 16
44 #define DEVICE_SUB_CLASS 55 #define DEVICE_SUB_CLASS 8
45 #define DEVICE_CLASS 56 #define DEVICE_CLASS 0
46 u32 ss_sel; 57 u32 ss_sel;
47 #define U2_SYSTEM_EXIT_LATENCY 58 #define U2_SYSTEM_EXIT_LATENCY 8
48 #define U1_SYSTEM_EXIT_LATENCY 59 #define U1_SYSTEM_EXIT_LATENCY 0
49 u32 ss_del; 60 u32 ss_del;
50 #define U2_DEVICE_EXIT_LATENCY 61 #define U2_DEVICE_EXIT_LATENCY 8
51 #define U1_DEVICE_EXIT_LATENCY 62 #define U1_DEVICE_EXIT_LATENCY 0
52 u32 usb2lpm; 63 u32 usb2lpm;
53 #define USB_L1_LPM_HIRD 64 #define USB_L1_LPM_HIRD 2
54 #define USB_L1_LPM_REMOTE_WAKE 65 #define USB_L1_LPM_REMOTE_WAKE 1
55 #define USB_L1_LPM_SUPPORT 66 #define USB_L1_LPM_SUPPORT 0
56 u32 usb3belt; 67 u32 usb3belt;
57 #define BELT_MULTIPLIER 68 #define BELT_MULTIPLIER 10
58 #define BEST_EFFORT_LATENCY_TOLERANCE 69 #define BEST_EFFORT_LATENCY_TOLERANCE 0
59 u32 usbctl2; 70 u32 usbctl2;
60 #define LTM_ENABLE 71 #define LTM_ENABLE 7
61 #define U2_ENABLE 72 #define U2_ENABLE 6
62 #define U1_ENABLE 73 #define U1_ENABLE 5
63 #define FUNCTION_SUSPEND 74 #define FUNCTION_SUSPEND 4
64 #define USB3_CORE_ENABLE 75 #define USB3_CORE_ENABLE 3
65 #define USB2_CORE_ENABLE 76 #define USB2_CORE_ENABLE 2
66 #define SERIAL_NUMBER_STRING_ENABLE 77 #define SERIAL_NUMBER_STRING_ENABLE 0
67 u32 in_timeout; 78 u32 in_timeout;
68 #define GPEP3_TIMEOUT 79 #define GPEP3_TIMEOUT 19
69 #define GPEP2_TIMEOUT 80 #define GPEP2_TIMEOUT 18
70 #define GPEP1_TIMEOUT 81 #define GPEP1_TIMEOUT 17
71 #define GPEP0_TIMEOUT 82 #define GPEP0_TIMEOUT 16
72 #define GPEP3_TIMEOUT_VALUE 83 #define GPEP3_TIMEOUT_VALUE 13
73 #define GPEP3_TIMEOUT_ENABLE 84 #define GPEP3_TIMEOUT_ENABLE 12
74 #define GPEP2_TIMEOUT_VALUE 85 #define GPEP2_TIMEOUT_VALUE 9
75 #define GPEP2_TIMEOUT_ENABLE 86 #define GPEP2_TIMEOUT_ENABLE 8
76 #define GPEP1_TIMEOUT_VALUE 87 #define GPEP1_TIMEOUT_VALUE 5
77 #define GPEP1_TIMEOUT_ENABLE 88 #define GPEP1_TIMEOUT_ENABLE 4
78 #define GPEP0_TIMEOUT_VALUE 89 #define GPEP0_TIMEOUT_VALUE 1
79 #define GPEP0_TIMEOUT_ENABLE 90 #define GPEP0_TIMEOUT_ENABLE 0
80 u32 isodelay; 91 u32 isodelay;
81 #define ISOCHRONOUS_DELAY 92 #define ISOCHRONOUS_DELAY 0
82 } __packed; 93 } __packed;
83 94
84 struct usb338x_fifo_regs { 95 struct usb338x_fifo_regs {
85 /* offset 0x0500, 0x0520, 0x0540, 0x05 96 /* offset 0x0500, 0x0520, 0x0540, 0x0560, 0x0580 */
86 u32 ep_fifo_size_base; 97 u32 ep_fifo_size_base;
87 #define IN_FIFO_BASE_ADDRESS 98 #define IN_FIFO_BASE_ADDRESS 22
88 #define IN_FIFO_SIZE 99 #define IN_FIFO_SIZE 16
89 #define OUT_FIFO_BASE_ADDRESS 100 #define OUT_FIFO_BASE_ADDRESS 6
90 #define OUT_FIFO_SIZE 101 #define OUT_FIFO_SIZE 0
91 u32 ep_fifo_out_wrptr; 102 u32 ep_fifo_out_wrptr;
92 u32 ep_fifo_out_rdptr; 103 u32 ep_fifo_out_rdptr;
93 u32 ep_fifo_in_wrptr; 104 u32 ep_fifo_in_wrptr;
94 u32 ep_fifo_in_rdptr; 105 u32 ep_fifo_in_rdptr;
95 u32 unused[3]; 106 u32 unused[3];
96 } __packed; 107 } __packed;
97 108
98 109
99 /* Link layer */ 110 /* Link layer */
100 struct usb338x_ll_regs { 111 struct usb338x_ll_regs {
101 /* offset 0x700 */ 112 /* offset 0x700 */
102 u32 ll_ltssm_ctrl1; 113 u32 ll_ltssm_ctrl1;
103 u32 ll_ltssm_ctrl2; 114 u32 ll_ltssm_ctrl2;
104 u32 ll_ltssm_ctrl3; 115 u32 ll_ltssm_ctrl3;
105 u32 unused1; !! 116 u32 unused[2];
106 <<
107 /* 0x710 */ <<
108 u32 unused2; <<
109 u32 ll_general_ctrl0; 117 u32 ll_general_ctrl0;
110 u32 ll_general_ctrl1; 118 u32 ll_general_ctrl1;
111 #define PM_U3_AUTO_EXIT 119 #define PM_U3_AUTO_EXIT 29
112 #define PM_U2_AUTO_EXIT 120 #define PM_U2_AUTO_EXIT 28
113 #define PM_U1_AUTO_EXIT 121 #define PM_U1_AUTO_EXIT 27
114 #define PM_FORCE_U2_ENTRY 122 #define PM_FORCE_U2_ENTRY 26
115 #define PM_FORCE_U1_ENTRY 123 #define PM_FORCE_U1_ENTRY 25
116 #define PM_LGO_COLLISION_SEND_LAU 124 #define PM_LGO_COLLISION_SEND_LAU 24
117 #define PM_DIR_LINK_REJECT 125 #define PM_DIR_LINK_REJECT 23
118 #define PM_FORCE_LINK_ACCEPT 126 #define PM_FORCE_LINK_ACCEPT 22
119 #define PM_DIR_ENTRY_U3 127 #define PM_DIR_ENTRY_U3 20
120 #define PM_DIR_ENTRY_U2 128 #define PM_DIR_ENTRY_U2 19
121 #define PM_DIR_ENTRY_U1 129 #define PM_DIR_ENTRY_U1 18
122 #define PM_U2_ENABLE 130 #define PM_U2_ENABLE 17
123 #define PM_U1_ENABLE 131 #define PM_U1_ENABLE 16
124 #define SKP_THRESHOLD_ADJUST_FMW 132 #define SKP_THRESHOLD_ADJUST_FMW 8
125 #define RESEND_DPP_ON_LRTY_FMW 133 #define RESEND_DPP_ON_LRTY_FMW 7
126 #define DL_BIT_VALUE_FMW 134 #define DL_BIT_VALUE_FMW 6
127 #define FORCE_DL_BIT 135 #define FORCE_DL_BIT 5
128 u32 ll_general_ctrl2; 136 u32 ll_general_ctrl2;
129 #define SELECT_INVERT_LANE_POLARITY 137 #define SELECT_INVERT_LANE_POLARITY 7
130 #define FORCE_INVERT_LANE_POLARITY 138 #define FORCE_INVERT_LANE_POLARITY 6
131 <<
132 /* 0x720 */ <<
133 u32 ll_general_ctrl3; 139 u32 ll_general_ctrl3;
134 u32 ll_general_ctrl4; 140 u32 ll_general_ctrl4;
135 u32 ll_error_gen; 141 u32 ll_error_gen;
136 u32 unused3; !! 142 } __packed;
137 <<
138 /* 0x730 */ <<
139 u32 unused4[4]; <<
140 143
141 /* 0x740 */ !! 144 struct usb338x_ll_lfps_regs {
142 u32 unused5[2]; !! 145 /* offset 0x748 */
143 u32 ll_lfps_5; 146 u32 ll_lfps_5;
144 #define TIMER_LFPS_6US 147 #define TIMER_LFPS_6US 16
145 u32 ll_lfps_6; 148 u32 ll_lfps_6;
146 #define TIMER_LFPS_80US 149 #define TIMER_LFPS_80US 0
>> 150 } __packed;
147 151
148 /* 0x750 */ !! 152 struct usb338x_ll_tsn_regs {
149 u32 unused6[8]; !! 153 /* offset 0x77C */
150 <<
151 /* 0x770 */ <<
152 u32 unused7[3]; <<
153 u32 ll_tsn_counters_2; 154 u32 ll_tsn_counters_2;
154 #define HOT_TX_NORESET_TS2 155 #define HOT_TX_NORESET_TS2 24
155 <<
156 /* 0x780 */ <<
157 u32 ll_tsn_counters_3; 156 u32 ll_tsn_counters_3;
158 #define HOT_RX_RESET_TS2 157 #define HOT_RX_RESET_TS2 0
159 u32 unused8[3]; !! 158 } __packed;
160 159
161 /* 0x790 */ !! 160 struct usb338x_ll_chi_regs {
162 u32 unused9; !! 161 /* offset 0x79C */
163 u32 ll_lfps_timers_2; <<
164 #define LFPS_TIMERS_2_WORKAROUND_VALUE <<
165 u32 unused10; <<
166 u32 ll_tsn_chicken_bit; 162 u32 ll_tsn_chicken_bit;
167 #define RECOVERY_IDLE_TO_RECOVER_FMW 163 #define RECOVERY_IDLE_TO_RECOVER_FMW 3
168 } __packed; 164 } __packed;
169 165
170 /* protocol layer */ 166 /* protocol layer */
171 struct usb338x_pl_regs { 167 struct usb338x_pl_regs {
172 /* offset 0x800 */ 168 /* offset 0x800 */
173 u32 pl_reg_1; 169 u32 pl_reg_1;
174 u32 pl_reg_2; 170 u32 pl_reg_2;
175 u32 pl_reg_3; 171 u32 pl_reg_3;
176 u32 pl_reg_4; 172 u32 pl_reg_4;
177 u32 pl_ep_ctrl; 173 u32 pl_ep_ctrl;
178 /* Protocol Layer Endpoint Control*/ 174 /* Protocol Layer Endpoint Control*/
179 #define PL_EP_CTRL 175 #define PL_EP_CTRL 0x810
180 #define ENDPOINT_SELECT 176 #define ENDPOINT_SELECT 0
181 /* [4:0] */ 177 /* [4:0] */
182 #define EP_INITIALIZED 178 #define EP_INITIALIZED 16
183 #define SEQUENCE_NUMBER_RESET 179 #define SEQUENCE_NUMBER_RESET 17
184 #define CLEAR_ACK_ERROR_CODE 180 #define CLEAR_ACK_ERROR_CODE 20
185 u32 pl_reg_6; 181 u32 pl_reg_6;
186 u32 pl_reg_7; 182 u32 pl_reg_7;
187 u32 pl_reg_8; 183 u32 pl_reg_8;
188 u32 pl_ep_status_1; 184 u32 pl_ep_status_1;
189 /* Protocol Layer Endpoint Status 1*/ 185 /* Protocol Layer Endpoint Status 1*/
190 #define PL_EP_STATUS_1 186 #define PL_EP_STATUS_1 0x820
191 #define STATE 187 #define STATE 16
192 #define ACK_GOOD_NORMAL 188 #define ACK_GOOD_NORMAL 0x11
193 #define ACK_GOOD_MORE_ACKS_TO_COME 189 #define ACK_GOOD_MORE_ACKS_TO_COME 0x16
194 u32 pl_ep_status_2; 190 u32 pl_ep_status_2;
195 u32 pl_ep_status_3; 191 u32 pl_ep_status_3;
196 /* Protocol Layer Endpoint Status 3*/ 192 /* Protocol Layer Endpoint Status 3*/
197 #define PL_EP_STATUS_3 193 #define PL_EP_STATUS_3 0x828
198 #define SEQUENCE_NUMBER 194 #define SEQUENCE_NUMBER 0
199 u32 pl_ep_status_4; 195 u32 pl_ep_status_4;
200 /* Protocol Layer Endpoint Status 4*/ 196 /* Protocol Layer Endpoint Status 4*/
201 #define PL_EP_STATUS_4 197 #define PL_EP_STATUS_4 0x82c
202 u32 pl_ep_cfg_4; 198 u32 pl_ep_cfg_4;
203 /* Protocol Layer Endpoint Configurati 199 /* Protocol Layer Endpoint Configuration 4*/
204 #define PL_EP_CFG_4 200 #define PL_EP_CFG_4 0x830
205 #define NON_CTRL_IN_TOLERATE_BAD_DIR 201 #define NON_CTRL_IN_TOLERATE_BAD_DIR 6
206 } __packed; 202 } __packed;
207 203
208 #endif /* __LINUX_USB_USB338X_H */ 204 #endif /* __LINUX_USB_USB338X_H */
209 205
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