1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * adv7604 - Analog Devices ADV7604 video deco 2 * adv7604 - Analog Devices ADV7604 video decoder driver
4 * 3 *
5 * Copyright 2012 Cisco Systems, Inc. and/or i 4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
>> 5 *
>> 6 * This program is free software; you may redistribute it and/or modify
>> 7 * it under the terms of the GNU General Public License as published by
>> 8 * the Free Software Foundation; version 2 of the License.
>> 9 *
>> 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
>> 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
>> 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>> 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
>> 17 * SOFTWARE.
>> 18 *
6 */ 19 */
7 20
8 #ifndef _ADV7604_ 21 #ifndef _ADV7604_
9 #define _ADV7604_ 22 #define _ADV7604_
10 23
11 #include <linux/types.h> 24 #include <linux/types.h>
12 25
13 /* Analog input muxing modes (AFE register 0x0 26 /* Analog input muxing modes (AFE register 0x02, [2:0]) */
14 enum adv7604_ain_sel { 27 enum adv7604_ain_sel {
15 ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0, 28 ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
16 ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1, 29 ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
17 ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2, 30 ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
18 ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3, 31 ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
19 ADV7604_AIN9_4_5_6_SYNC_2_1 = 4, 32 ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
20 }; 33 };
21 34
22 /* 35 /*
23 * Bus rotation and reordering. This is used t 36 * Bus rotation and reordering. This is used to specify component reordering on
24 * the board and describes the components orde 37 * the board and describes the components order on the bus when the ADV7604
25 * outputs RGB. 38 * outputs RGB.
26 */ 39 */
27 enum adv7604_bus_order { 40 enum adv7604_bus_order {
28 ADV7604_BUS_ORDER_RGB, /* No 41 ADV7604_BUS_ORDER_RGB, /* No operation */
29 ADV7604_BUS_ORDER_GRB, /* Swa 42 ADV7604_BUS_ORDER_GRB, /* Swap 1-2 */
30 ADV7604_BUS_ORDER_RBG, /* Swa 43 ADV7604_BUS_ORDER_RBG, /* Swap 2-3 */
31 ADV7604_BUS_ORDER_BGR, /* Swa 44 ADV7604_BUS_ORDER_BGR, /* Swap 1-3 */
32 ADV7604_BUS_ORDER_BRG, /* Rot 45 ADV7604_BUS_ORDER_BRG, /* Rotate right */
33 ADV7604_BUS_ORDER_GBR, /* Rot 46 ADV7604_BUS_ORDER_GBR, /* Rotate left */
34 }; 47 };
35 48
36 /* Input Color Space (IO register 0x02, [7:4]) 49 /* Input Color Space (IO register 0x02, [7:4]) */
37 enum adv76xx_inp_color_space { 50 enum adv76xx_inp_color_space {
38 ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0, 51 ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0,
39 ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1, 52 ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1,
40 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 53 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
41 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 54 ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
42 ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4, 55 ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4,
43 ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5, 56 ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5,
44 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 57 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
45 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 58 ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
46 ADV76XX_INP_COLOR_SPACE_AUTO = 0xf, 59 ADV76XX_INP_COLOR_SPACE_AUTO = 0xf,
47 }; 60 };
48 61
49 /* Select output format (IO register 0x03, [4: 62 /* Select output format (IO register 0x03, [4:2]) */
50 enum adv7604_op_format_mode_sel { 63 enum adv7604_op_format_mode_sel {
51 ADV7604_OP_FORMAT_MODE0 = 0x00, 64 ADV7604_OP_FORMAT_MODE0 = 0x00,
52 ADV7604_OP_FORMAT_MODE1 = 0x04, 65 ADV7604_OP_FORMAT_MODE1 = 0x04,
53 ADV7604_OP_FORMAT_MODE2 = 0x08, 66 ADV7604_OP_FORMAT_MODE2 = 0x08,
54 }; 67 };
55 68
56 enum adv76xx_drive_strength { 69 enum adv76xx_drive_strength {
57 ADV76XX_DR_STR_MEDIUM_LOW = 1, 70 ADV76XX_DR_STR_MEDIUM_LOW = 1,
58 ADV76XX_DR_STR_MEDIUM_HIGH = 2, 71 ADV76XX_DR_STR_MEDIUM_HIGH = 2,
59 ADV76XX_DR_STR_HIGH = 3, 72 ADV76XX_DR_STR_HIGH = 3,
60 }; 73 };
61 74
62 /* INT1 Configuration (IO register 0x40, [1:0] 75 /* INT1 Configuration (IO register 0x40, [1:0]) */
63 enum adv76xx_int1_config { 76 enum adv76xx_int1_config {
64 ADV76XX_INT1_CONFIG_OPEN_DRAIN, 77 ADV76XX_INT1_CONFIG_OPEN_DRAIN,
65 ADV76XX_INT1_CONFIG_ACTIVE_LOW, 78 ADV76XX_INT1_CONFIG_ACTIVE_LOW,
66 ADV76XX_INT1_CONFIG_ACTIVE_HIGH, 79 ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
67 ADV76XX_INT1_CONFIG_DISABLED, 80 ADV76XX_INT1_CONFIG_DISABLED,
68 }; 81 };
69 82
70 enum adv76xx_page { 83 enum adv76xx_page {
71 ADV76XX_PAGE_IO, 84 ADV76XX_PAGE_IO,
72 ADV7604_PAGE_AVLINK, 85 ADV7604_PAGE_AVLINK,
73 ADV76XX_PAGE_CEC, 86 ADV76XX_PAGE_CEC,
74 ADV76XX_PAGE_INFOFRAME, 87 ADV76XX_PAGE_INFOFRAME,
75 ADV7604_PAGE_ESDP, 88 ADV7604_PAGE_ESDP,
76 ADV7604_PAGE_DPP, 89 ADV7604_PAGE_DPP,
77 ADV76XX_PAGE_AFE, 90 ADV76XX_PAGE_AFE,
78 ADV76XX_PAGE_REP, 91 ADV76XX_PAGE_REP,
79 ADV76XX_PAGE_EDID, 92 ADV76XX_PAGE_EDID,
80 ADV76XX_PAGE_HDMI, 93 ADV76XX_PAGE_HDMI,
81 ADV76XX_PAGE_TEST, 94 ADV76XX_PAGE_TEST,
82 ADV76XX_PAGE_CP, 95 ADV76XX_PAGE_CP,
83 ADV7604_PAGE_VDP, 96 ADV7604_PAGE_VDP,
84 ADV76XX_PAGE_MAX, 97 ADV76XX_PAGE_MAX,
85 }; 98 };
86 99
87 /* Platform dependent definition */ 100 /* Platform dependent definition */
88 struct adv76xx_platform_data { 101 struct adv76xx_platform_data {
89 /* DIS_PWRDNB: 1 if the PWRDNB pin is 102 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
90 unsigned disable_pwrdnb:1; 103 unsigned disable_pwrdnb:1;
91 104
92 /* DIS_CABLE_DET_RST: 1 if the 5V pins 105 /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
93 unsigned disable_cable_det_rst:1; 106 unsigned disable_cable_det_rst:1;
94 107
95 int default_input; 108 int default_input;
96 109
97 /* Analog input muxing mode */ 110 /* Analog input muxing mode */
98 enum adv7604_ain_sel ain_sel; 111 enum adv7604_ain_sel ain_sel;
99 112
100 /* Bus rotation and reordering */ 113 /* Bus rotation and reordering */
101 enum adv7604_bus_order bus_order; 114 enum adv7604_bus_order bus_order;
102 115
103 /* Select output format mode */ 116 /* Select output format mode */
104 enum adv7604_op_format_mode_sel op_for 117 enum adv7604_op_format_mode_sel op_format_mode_sel;
105 118
106 /* Configuration of the INT1 pin */ 119 /* Configuration of the INT1 pin */
107 enum adv76xx_int1_config int1_config; 120 enum adv76xx_int1_config int1_config;
108 121
109 /* IO register 0x02 */ 122 /* IO register 0x02 */
110 unsigned alt_gamma:1; 123 unsigned alt_gamma:1;
111 124
112 /* IO register 0x05 */ 125 /* IO register 0x05 */
113 unsigned blank_data:1; 126 unsigned blank_data:1;
114 unsigned insert_av_codes:1; 127 unsigned insert_av_codes:1;
115 unsigned replicate_av_codes:1; 128 unsigned replicate_av_codes:1;
116 129
117 /* IO register 0x06 */ 130 /* IO register 0x06 */
118 unsigned inv_vs_pol:1; 131 unsigned inv_vs_pol:1;
119 unsigned inv_hs_pol:1; 132 unsigned inv_hs_pol:1;
120 unsigned inv_llc_pol:1; 133 unsigned inv_llc_pol:1;
121 134
122 /* IO register 0x14 */ 135 /* IO register 0x14 */
123 enum adv76xx_drive_strength dr_str_dat 136 enum adv76xx_drive_strength dr_str_data;
124 enum adv76xx_drive_strength dr_str_clk 137 enum adv76xx_drive_strength dr_str_clk;
125 enum adv76xx_drive_strength dr_str_syn 138 enum adv76xx_drive_strength dr_str_sync;
126 139
127 /* IO register 0x30 */ 140 /* IO register 0x30 */
128 unsigned output_bus_lsb_to_msb:1; 141 unsigned output_bus_lsb_to_msb:1;
129 142
130 /* Free run */ 143 /* Free run */
131 unsigned hdmi_free_run_mode; 144 unsigned hdmi_free_run_mode;
132 145
133 /* i2c addresses: 0 == use default */ 146 /* i2c addresses: 0 == use default */
134 u8 i2c_addresses[ADV76XX_PAGE_MAX]; 147 u8 i2c_addresses[ADV76XX_PAGE_MAX];
135 }; 148 };
136 149
137 enum adv76xx_pad { 150 enum adv76xx_pad {
138 ADV76XX_PAD_HDMI_PORT_A = 0, 151 ADV76XX_PAD_HDMI_PORT_A = 0,
139 ADV7604_PAD_HDMI_PORT_B = 1, 152 ADV7604_PAD_HDMI_PORT_B = 1,
140 ADV7604_PAD_HDMI_PORT_C = 2, 153 ADV7604_PAD_HDMI_PORT_C = 2,
141 ADV7604_PAD_HDMI_PORT_D = 3, 154 ADV7604_PAD_HDMI_PORT_D = 3,
142 ADV7604_PAD_VGA_RGB = 4, 155 ADV7604_PAD_VGA_RGB = 4,
143 ADV7604_PAD_VGA_COMP = 5, 156 ADV7604_PAD_VGA_COMP = 5,
144 /* The source pad is either 1 (ADV7611 157 /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
145 ADV7604_PAD_SOURCE = 6, 158 ADV7604_PAD_SOURCE = 6,
146 ADV7611_PAD_SOURCE = 1, 159 ADV7611_PAD_SOURCE = 1,
147 ADV76XX_PAD_MAX = 7, 160 ADV76XX_PAD_MAX = 7,
148 }; 161 };
149 162
150 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE 163 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
151 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL 164 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
152 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR 165 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
153 166
154 /* notify events */ 167 /* notify events */
155 #define ADV76XX_HOTPLUG 1 168 #define ADV76XX_HOTPLUG 1
156 169
157 #endif 170 #endif
158 171
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