1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 saa7115.h - definition for saa7111/3/4/5 i 2 saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
4 3
5 Copyright (C) 2006 Hans Verkuil (hverkuil@ 4 Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
6 5
>> 6 This program is free software; you can redistribute it and/or modify
>> 7 it under the terms of the GNU General Public License as published by
>> 8 the Free Software Foundation; either version 2 of the License, or
>> 9 (at your option) any later version.
>> 10
>> 11 This program is distributed in the hope that it will be useful,
>> 12 but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 14 GNU General Public License for more details.
>> 15
>> 16 You should have received a copy of the GNU General Public License
>> 17 along with this program; if not, write to the Free Software
>> 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
7 */ 19 */
8 20
9 #ifndef _SAA7115_H_ 21 #ifndef _SAA7115_H_
10 #define _SAA7115_H_ 22 #define _SAA7115_H_
11 23
12 /* s_routing inputs, outputs, and config */ 24 /* s_routing inputs, outputs, and config */
13 25
14 /* SAA7111/3/4/5 HW inputs */ 26 /* SAA7111/3/4/5 HW inputs */
15 #define SAA7115_COMPOSITE0 0 27 #define SAA7115_COMPOSITE0 0
16 #define SAA7115_COMPOSITE1 1 28 #define SAA7115_COMPOSITE1 1
17 #define SAA7115_COMPOSITE2 2 29 #define SAA7115_COMPOSITE2 2
18 #define SAA7115_COMPOSITE3 3 30 #define SAA7115_COMPOSITE3 3
19 #define SAA7115_COMPOSITE4 4 /* not available 31 #define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */
20 #define SAA7115_COMPOSITE5 5 /* not available 32 #define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */
21 #define SAA7115_SVIDEO0 6 33 #define SAA7115_SVIDEO0 6
22 #define SAA7115_SVIDEO1 7 34 #define SAA7115_SVIDEO1 7
23 #define SAA7115_SVIDEO2 8 35 #define SAA7115_SVIDEO2 8
24 #define SAA7115_SVIDEO3 9 36 #define SAA7115_SVIDEO3 9
25 37
26 /* outputs */ 38 /* outputs */
27 #define SAA7115_IPORT_ON 1 39 #define SAA7115_IPORT_ON 1
28 #define SAA7115_IPORT_OFF 0 40 #define SAA7115_IPORT_OFF 0
29 41
30 /* SAA7111 specific outputs. */ 42 /* SAA7111 specific outputs. */
31 #define SAA7111_VBI_BYPASS 2 43 #define SAA7111_VBI_BYPASS 2
32 #define SAA7111_FMT_YUV422 0x00 44 #define SAA7111_FMT_YUV422 0x00
33 #define SAA7111_FMT_RGB 0x40 45 #define SAA7111_FMT_RGB 0x40
34 #define SAA7111_FMT_CCIR 0x80 46 #define SAA7111_FMT_CCIR 0x80
35 #define SAA7111_FMT_YUV411 0xc0 47 #define SAA7111_FMT_YUV411 0xc0
36 48
37 /* config flags */ 49 /* config flags */
38 /* 50 /*
39 * Register 0x85 should set bit 0 to 0 (it's 1 51 * Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit
40 * controls the IDQ signal polarity which is s 52 * controls the IDQ signal polarity which is set to 'inverted' if the bit
41 * it 1 and to 'default' if it is 0. 53 * it 1 and to 'default' if it is 0.
42 */ 54 */
43 #define SAA7115_IDQ_IS_DEFAULT (1 << 0) 55 #define SAA7115_IDQ_IS_DEFAULT (1 << 0)
44 56
45 /* s_crystal_freq values and flags */ 57 /* s_crystal_freq values and flags */
46 58
47 /* SAA7115 v4l2_crystal_freq frequency values 59 /* SAA7115 v4l2_crystal_freq frequency values */
48 #define SAA7115_FREQ_32_11_MHZ 32110000 /* 60 #define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */
49 #define SAA7115_FREQ_24_576_MHZ 24576000 /* 61 #define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */
50 62
51 /* SAA7115 v4l2_crystal_freq audio clock contr 63 /* SAA7115 v4l2_crystal_freq audio clock control flags */
52 #define SAA7115_FREQ_FL_UCGC (1 << 0) 64 #define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
53 #define SAA7115_FREQ_FL_CGCDIV (1 << 1) 65 #define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
54 #define SAA7115_FREQ_FL_APLL (1 << 2) 66 #define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
55 #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) 67 #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */
56 68
57 /* ===== SAA7113 Config enums ===== */ 69 /* ===== SAA7113 Config enums ===== */
58 70
59 /* Register 0x08 "Horizontal time constant" [B 71 /* Register 0x08 "Horizontal time constant" [Bit 3..4]:
60 * Should be set to "Fast Locking Mode" accord 72 * Should be set to "Fast Locking Mode" according to the datasheet,
61 * and that is the default setting in the gm71 73 * and that is the default setting in the gm7113c_init table.
62 * saa7113_init sets this value to "VTR Mode". 74 * saa7113_init sets this value to "VTR Mode". */
63 enum saa7113_r08_htc { 75 enum saa7113_r08_htc {
64 SAA7113_HTC_TV_MODE = 0x00, 76 SAA7113_HTC_TV_MODE = 0x00,
65 SAA7113_HTC_VTR_MODE, 77 SAA7113_HTC_VTR_MODE, /* Default for saa7113_init */
66 SAA7113_HTC_FAST_LOCKING_MODE = 0x03 78 SAA7113_HTC_FAST_LOCKING_MODE = 0x03 /* Default for gm7113c_init */
67 }; 79 };
68 80
69 /* Register 0x10 "Output format selection" [Bi 81 /* Register 0x10 "Output format selection" [Bit 6..7]:
70 * Defaults to ITU_656 as specified in datashe 82 * Defaults to ITU_656 as specified in datasheet. */
71 enum saa7113_r10_ofts { 83 enum saa7113_r10_ofts {
72 SAA7113_OFTS_ITU_656 = 0x0, /* Def 84 SAA7113_OFTS_ITU_656 = 0x0, /* Default */
73 SAA7113_OFTS_VFLAG_BY_VREF, 85 SAA7113_OFTS_VFLAG_BY_VREF,
74 SAA7113_OFTS_VFLAG_BY_DATA_TYPE 86 SAA7113_OFTS_VFLAG_BY_DATA_TYPE
75 }; 87 };
76 88
77 /* 89 /*
78 * Register 0x12 "Output control" [Bit 0..3 Or 90 * Register 0x12 "Output control" [Bit 0..3 Or Bit 4..7]:
79 * This is used to select what data is output 91 * This is used to select what data is output on the RTS0 and RTS1 pins.
80 * RTS1 [Bit 4..7] Defaults to DOT_IN. (This v 92 * RTS1 [Bit 4..7] Defaults to DOT_IN. (This value can not be set for RTS0)
81 * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c 93 * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c_init as specified
82 * in the datasheet, but is set to HREF_HS in 94 * in the datasheet, but is set to HREF_HS in the saa7113_init table.
83 */ 95 */
84 enum saa7113_r12_rts { 96 enum saa7113_r12_rts {
85 SAA7113_RTS_DOT_IN = 0, /* OBS 97 SAA7113_RTS_DOT_IN = 0, /* OBS: Only for RTS1 (Default RTS1) */
86 SAA7113_RTS_VIPB, /* Def 98 SAA7113_RTS_VIPB, /* Default RTS0 For gm7113c_init */
87 SAA7113_RTS_GPSW, 99 SAA7113_RTS_GPSW,
88 SAA7115_RTS_HL, 100 SAA7115_RTS_HL,
89 SAA7113_RTS_VL, 101 SAA7113_RTS_VL,
90 SAA7113_RTS_DL, 102 SAA7113_RTS_DL,
91 SAA7113_RTS_PLIN, 103 SAA7113_RTS_PLIN,
92 SAA7113_RTS_HREF_HS, /* Def 104 SAA7113_RTS_HREF_HS, /* Default RTS0 For saa7113_init */
93 SAA7113_RTS_HS, 105 SAA7113_RTS_HS,
94 SAA7113_RTS_HQ, 106 SAA7113_RTS_HQ,
95 SAA7113_RTS_ODD, 107 SAA7113_RTS_ODD,
96 SAA7113_RTS_VS, 108 SAA7113_RTS_VS,
97 SAA7113_RTS_V123, 109 SAA7113_RTS_V123,
98 SAA7113_RTS_VGATE, 110 SAA7113_RTS_VGATE,
99 SAA7113_RTS_VREF, 111 SAA7113_RTS_VREF,
100 SAA7113_RTS_FID 112 SAA7113_RTS_FID
101 }; 113 };
102 114
103 /** 115 /**
104 * struct saa7115_platform_data - Allow overri 116 * struct saa7115_platform_data - Allow overriding default initialization
105 * 117 *
106 * @saa7113_force_gm7113c_init: Force the use 118 * @saa7113_force_gm7113c_init: Force the use of the gm7113c_init table
107 * instead of saa 119 * instead of saa7113_init table
108 * (saa7113 only) 120 * (saa7113 only)
109 * @saa7113_r08_htc: [R_08 - Bit 3. 121 * @saa7113_r08_htc: [R_08 - Bit 3..4]
110 * @saa7113_r10_vrln: [R_10 - Bit 3] 122 * @saa7113_r10_vrln: [R_10 - Bit 3]
111 * default: Disab 123 * default: Disabled for gm7113c_init
112 * Enabl 124 * Enabled for saa7113c_init
113 * @saa7113_r10_ofts: [R_10 - Bit 6. 125 * @saa7113_r10_ofts: [R_10 - Bit 6..7]
114 * @saa7113_r12_rts0: [R_12 - Bit 0. 126 * @saa7113_r12_rts0: [R_12 - Bit 0..3]
115 * @saa7113_r12_rts1: [R_12 - Bit 4. 127 * @saa7113_r12_rts1: [R_12 - Bit 4..7]
116 * @saa7113_r13_adlsb: [R_13 - Bit 7] 128 * @saa7113_r13_adlsb: [R_13 - Bit 7] - default: disabled
117 */ 129 */
118 struct saa7115_platform_data { 130 struct saa7115_platform_data {
119 bool saa7113_force_gm7113c_init; 131 bool saa7113_force_gm7113c_init;
120 enum saa7113_r08_htc *saa7113_r08_htc; 132 enum saa7113_r08_htc *saa7113_r08_htc;
121 bool *saa7113_r10_vrln; 133 bool *saa7113_r10_vrln;
122 enum saa7113_r10_ofts *saa7113_r10_oft 134 enum saa7113_r10_ofts *saa7113_r10_ofts;
123 enum saa7113_r12_rts *saa7113_r12_rts0 135 enum saa7113_r12_rts *saa7113_r12_rts0;
124 enum saa7113_r12_rts *saa7113_r12_rts1 136 enum saa7113_r12_rts *saa7113_r12_rts1;
125 bool *saa7113_r13_adlsb; 137 bool *saa7113_r13_adlsb;
126 }; 138 };
127 139
128 #endif 140 #endif
129 141
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