1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1
2 /*
3 saa7115.h - definition for saa7111/3/4/5 i
4
5 Copyright (C) 2006 Hans Verkuil (hverkuil@
6
7 */
8
9 #ifndef _SAA7115_H_
10 #define _SAA7115_H_
11
12 /* s_routing inputs, outputs, and config */
13
14 /* SAA7111/3/4/5 HW inputs */
15 #define SAA7115_COMPOSITE0 0
16 #define SAA7115_COMPOSITE1 1
17 #define SAA7115_COMPOSITE2 2
18 #define SAA7115_COMPOSITE3 3
19 #define SAA7115_COMPOSITE4 4 /* not available
20 #define SAA7115_COMPOSITE5 5 /* not available
21 #define SAA7115_SVIDEO0 6
22 #define SAA7115_SVIDEO1 7
23 #define SAA7115_SVIDEO2 8
24 #define SAA7115_SVIDEO3 9
25
26 /* outputs */
27 #define SAA7115_IPORT_ON 1
28 #define SAA7115_IPORT_OFF 0
29
30 /* SAA7111 specific outputs. */
31 #define SAA7111_VBI_BYPASS 2
32 #define SAA7111_FMT_YUV422 0x00
33 #define SAA7111_FMT_RGB 0x40
34 #define SAA7111_FMT_CCIR 0x80
35 #define SAA7111_FMT_YUV411 0xc0
36
37 /* config flags */
38 /*
39 * Register 0x85 should set bit 0 to 0 (it's 1
40 * controls the IDQ signal polarity which is s
41 * it 1 and to 'default' if it is 0.
42 */
43 #define SAA7115_IDQ_IS_DEFAULT (1 << 0)
44
45 /* s_crystal_freq values and flags */
46
47 /* SAA7115 v4l2_crystal_freq frequency values
48 #define SAA7115_FREQ_32_11_MHZ 32110000 /*
49 #define SAA7115_FREQ_24_576_MHZ 24576000 /*
50
51 /* SAA7115 v4l2_crystal_freq audio clock contr
52 #define SAA7115_FREQ_FL_UCGC (1 << 0)
53 #define SAA7115_FREQ_FL_CGCDIV (1 << 1)
54 #define SAA7115_FREQ_FL_APLL (1 << 2)
55 #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3)
56
57 /* ===== SAA7113 Config enums ===== */
58
59 /* Register 0x08 "Horizontal time constant" [B
60 * Should be set to "Fast Locking Mode" accord
61 * and that is the default setting in the gm71
62 * saa7113_init sets this value to "VTR Mode".
63 enum saa7113_r08_htc {
64 SAA7113_HTC_TV_MODE = 0x00,
65 SAA7113_HTC_VTR_MODE,
66 SAA7113_HTC_FAST_LOCKING_MODE = 0x03
67 };
68
69 /* Register 0x10 "Output format selection" [Bi
70 * Defaults to ITU_656 as specified in datashe
71 enum saa7113_r10_ofts {
72 SAA7113_OFTS_ITU_656 = 0x0, /* Def
73 SAA7113_OFTS_VFLAG_BY_VREF,
74 SAA7113_OFTS_VFLAG_BY_DATA_TYPE
75 };
76
77 /*
78 * Register 0x12 "Output control" [Bit 0..3 Or
79 * This is used to select what data is output
80 * RTS1 [Bit 4..7] Defaults to DOT_IN. (This v
81 * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c
82 * in the datasheet, but is set to HREF_HS in
83 */
84 enum saa7113_r12_rts {
85 SAA7113_RTS_DOT_IN = 0, /* OBS
86 SAA7113_RTS_VIPB, /* Def
87 SAA7113_RTS_GPSW,
88 SAA7115_RTS_HL,
89 SAA7113_RTS_VL,
90 SAA7113_RTS_DL,
91 SAA7113_RTS_PLIN,
92 SAA7113_RTS_HREF_HS, /* Def
93 SAA7113_RTS_HS,
94 SAA7113_RTS_HQ,
95 SAA7113_RTS_ODD,
96 SAA7113_RTS_VS,
97 SAA7113_RTS_V123,
98 SAA7113_RTS_VGATE,
99 SAA7113_RTS_VREF,
100 SAA7113_RTS_FID
101 };
102
103 /**
104 * struct saa7115_platform_data - Allow overri
105 *
106 * @saa7113_force_gm7113c_init: Force the use
107 * instead of saa
108 * (saa7113 only)
109 * @saa7113_r08_htc: [R_08 - Bit 3.
110 * @saa7113_r10_vrln: [R_10 - Bit 3]
111 * default: Disab
112 * Enabl
113 * @saa7113_r10_ofts: [R_10 - Bit 6.
114 * @saa7113_r12_rts0: [R_12 - Bit 0.
115 * @saa7113_r12_rts1: [R_12 - Bit 4.
116 * @saa7113_r13_adlsb: [R_13 - Bit 7]
117 */
118 struct saa7115_platform_data {
119 bool saa7113_force_gm7113c_init;
120 enum saa7113_r08_htc *saa7113_r08_htc;
121 bool *saa7113_r10_vrln;
122 enum saa7113_r10_ofts *saa7113_r10_oft
123 enum saa7113_r12_rts *saa7113_r12_rts0
124 enum saa7113_r12_rts *saa7113_r12_rts1
125 bool *saa7113_r13_adlsb;
126 };
127
128 #endif
129
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