1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 saa7115.h - definition for saa7111/3/4/5 i 3 saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
4 4
5 Copyright (C) 2006 Hans Verkuil (hverkuil@ 5 Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
6 6
7 */ 7 */
8 8
9 #ifndef _SAA7115_H_ 9 #ifndef _SAA7115_H_
10 #define _SAA7115_H_ 10 #define _SAA7115_H_
11 11
12 /* s_routing inputs, outputs, and config */ 12 /* s_routing inputs, outputs, and config */
13 13
14 /* SAA7111/3/4/5 HW inputs */ 14 /* SAA7111/3/4/5 HW inputs */
15 #define SAA7115_COMPOSITE0 0 15 #define SAA7115_COMPOSITE0 0
16 #define SAA7115_COMPOSITE1 1 16 #define SAA7115_COMPOSITE1 1
17 #define SAA7115_COMPOSITE2 2 17 #define SAA7115_COMPOSITE2 2
18 #define SAA7115_COMPOSITE3 3 18 #define SAA7115_COMPOSITE3 3
19 #define SAA7115_COMPOSITE4 4 /* not available 19 #define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */
20 #define SAA7115_COMPOSITE5 5 /* not available 20 #define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */
21 #define SAA7115_SVIDEO0 6 21 #define SAA7115_SVIDEO0 6
22 #define SAA7115_SVIDEO1 7 22 #define SAA7115_SVIDEO1 7
23 #define SAA7115_SVIDEO2 8 23 #define SAA7115_SVIDEO2 8
24 #define SAA7115_SVIDEO3 9 24 #define SAA7115_SVIDEO3 9
25 25
26 /* outputs */ 26 /* outputs */
27 #define SAA7115_IPORT_ON 1 27 #define SAA7115_IPORT_ON 1
28 #define SAA7115_IPORT_OFF 0 28 #define SAA7115_IPORT_OFF 0
29 29
30 /* SAA7111 specific outputs. */ 30 /* SAA7111 specific outputs. */
31 #define SAA7111_VBI_BYPASS 2 31 #define SAA7111_VBI_BYPASS 2
32 #define SAA7111_FMT_YUV422 0x00 32 #define SAA7111_FMT_YUV422 0x00
33 #define SAA7111_FMT_RGB 0x40 33 #define SAA7111_FMT_RGB 0x40
34 #define SAA7111_FMT_CCIR 0x80 34 #define SAA7111_FMT_CCIR 0x80
35 #define SAA7111_FMT_YUV411 0xc0 35 #define SAA7111_FMT_YUV411 0xc0
36 36
37 /* config flags */ 37 /* config flags */
38 /* 38 /*
39 * Register 0x85 should set bit 0 to 0 (it's 1 39 * Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit
40 * controls the IDQ signal polarity which is s 40 * controls the IDQ signal polarity which is set to 'inverted' if the bit
41 * it 1 and to 'default' if it is 0. 41 * it 1 and to 'default' if it is 0.
42 */ 42 */
43 #define SAA7115_IDQ_IS_DEFAULT (1 << 0) 43 #define SAA7115_IDQ_IS_DEFAULT (1 << 0)
44 44
45 /* s_crystal_freq values and flags */ 45 /* s_crystal_freq values and flags */
46 46
47 /* SAA7115 v4l2_crystal_freq frequency values 47 /* SAA7115 v4l2_crystal_freq frequency values */
48 #define SAA7115_FREQ_32_11_MHZ 32110000 /* 48 #define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */
49 #define SAA7115_FREQ_24_576_MHZ 24576000 /* 49 #define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */
50 50
51 /* SAA7115 v4l2_crystal_freq audio clock contr 51 /* SAA7115 v4l2_crystal_freq audio clock control flags */
52 #define SAA7115_FREQ_FL_UCGC (1 << 0) 52 #define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
53 #define SAA7115_FREQ_FL_CGCDIV (1 << 1) 53 #define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
54 #define SAA7115_FREQ_FL_APLL (1 << 2) 54 #define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
55 #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) 55 #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */
56 56
57 /* ===== SAA7113 Config enums ===== */ 57 /* ===== SAA7113 Config enums ===== */
58 58
59 /* Register 0x08 "Horizontal time constant" [B 59 /* Register 0x08 "Horizontal time constant" [Bit 3..4]:
60 * Should be set to "Fast Locking Mode" accord 60 * Should be set to "Fast Locking Mode" according to the datasheet,
61 * and that is the default setting in the gm71 61 * and that is the default setting in the gm7113c_init table.
62 * saa7113_init sets this value to "VTR Mode". 62 * saa7113_init sets this value to "VTR Mode". */
63 enum saa7113_r08_htc { 63 enum saa7113_r08_htc {
64 SAA7113_HTC_TV_MODE = 0x00, 64 SAA7113_HTC_TV_MODE = 0x00,
65 SAA7113_HTC_VTR_MODE, 65 SAA7113_HTC_VTR_MODE, /* Default for saa7113_init */
66 SAA7113_HTC_FAST_LOCKING_MODE = 0x03 66 SAA7113_HTC_FAST_LOCKING_MODE = 0x03 /* Default for gm7113c_init */
67 }; 67 };
68 68
69 /* Register 0x10 "Output format selection" [Bi 69 /* Register 0x10 "Output format selection" [Bit 6..7]:
70 * Defaults to ITU_656 as specified in datashe 70 * Defaults to ITU_656 as specified in datasheet. */
71 enum saa7113_r10_ofts { 71 enum saa7113_r10_ofts {
72 SAA7113_OFTS_ITU_656 = 0x0, /* Def 72 SAA7113_OFTS_ITU_656 = 0x0, /* Default */
73 SAA7113_OFTS_VFLAG_BY_VREF, 73 SAA7113_OFTS_VFLAG_BY_VREF,
74 SAA7113_OFTS_VFLAG_BY_DATA_TYPE 74 SAA7113_OFTS_VFLAG_BY_DATA_TYPE
75 }; 75 };
76 76
77 /* 77 /*
78 * Register 0x12 "Output control" [Bit 0..3 Or 78 * Register 0x12 "Output control" [Bit 0..3 Or Bit 4..7]:
79 * This is used to select what data is output 79 * This is used to select what data is output on the RTS0 and RTS1 pins.
80 * RTS1 [Bit 4..7] Defaults to DOT_IN. (This v 80 * RTS1 [Bit 4..7] Defaults to DOT_IN. (This value can not be set for RTS0)
81 * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c 81 * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c_init as specified
82 * in the datasheet, but is set to HREF_HS in 82 * in the datasheet, but is set to HREF_HS in the saa7113_init table.
83 */ 83 */
84 enum saa7113_r12_rts { 84 enum saa7113_r12_rts {
85 SAA7113_RTS_DOT_IN = 0, /* OBS 85 SAA7113_RTS_DOT_IN = 0, /* OBS: Only for RTS1 (Default RTS1) */
86 SAA7113_RTS_VIPB, /* Def 86 SAA7113_RTS_VIPB, /* Default RTS0 For gm7113c_init */
87 SAA7113_RTS_GPSW, 87 SAA7113_RTS_GPSW,
88 SAA7115_RTS_HL, 88 SAA7115_RTS_HL,
89 SAA7113_RTS_VL, 89 SAA7113_RTS_VL,
90 SAA7113_RTS_DL, 90 SAA7113_RTS_DL,
91 SAA7113_RTS_PLIN, 91 SAA7113_RTS_PLIN,
92 SAA7113_RTS_HREF_HS, /* Def 92 SAA7113_RTS_HREF_HS, /* Default RTS0 For saa7113_init */
93 SAA7113_RTS_HS, 93 SAA7113_RTS_HS,
94 SAA7113_RTS_HQ, 94 SAA7113_RTS_HQ,
95 SAA7113_RTS_ODD, 95 SAA7113_RTS_ODD,
96 SAA7113_RTS_VS, 96 SAA7113_RTS_VS,
97 SAA7113_RTS_V123, 97 SAA7113_RTS_V123,
98 SAA7113_RTS_VGATE, 98 SAA7113_RTS_VGATE,
99 SAA7113_RTS_VREF, 99 SAA7113_RTS_VREF,
100 SAA7113_RTS_FID 100 SAA7113_RTS_FID
101 }; 101 };
102 102
103 /** 103 /**
104 * struct saa7115_platform_data - Allow overri 104 * struct saa7115_platform_data - Allow overriding default initialization
105 * 105 *
106 * @saa7113_force_gm7113c_init: Force the use 106 * @saa7113_force_gm7113c_init: Force the use of the gm7113c_init table
107 * instead of saa 107 * instead of saa7113_init table
108 * (saa7113 only) 108 * (saa7113 only)
109 * @saa7113_r08_htc: [R_08 - Bit 3. 109 * @saa7113_r08_htc: [R_08 - Bit 3..4]
110 * @saa7113_r10_vrln: [R_10 - Bit 3] 110 * @saa7113_r10_vrln: [R_10 - Bit 3]
111 * default: Disab 111 * default: Disabled for gm7113c_init
112 * Enabl 112 * Enabled for saa7113c_init
113 * @saa7113_r10_ofts: [R_10 - Bit 6. 113 * @saa7113_r10_ofts: [R_10 - Bit 6..7]
114 * @saa7113_r12_rts0: [R_12 - Bit 0. 114 * @saa7113_r12_rts0: [R_12 - Bit 0..3]
115 * @saa7113_r12_rts1: [R_12 - Bit 4. 115 * @saa7113_r12_rts1: [R_12 - Bit 4..7]
116 * @saa7113_r13_adlsb: [R_13 - Bit 7] 116 * @saa7113_r13_adlsb: [R_13 - Bit 7] - default: disabled
117 */ 117 */
118 struct saa7115_platform_data { 118 struct saa7115_platform_data {
119 bool saa7113_force_gm7113c_init; 119 bool saa7113_force_gm7113c_init;
120 enum saa7113_r08_htc *saa7113_r08_htc; 120 enum saa7113_r08_htc *saa7113_r08_htc;
121 bool *saa7113_r10_vrln; 121 bool *saa7113_r10_vrln;
122 enum saa7113_r10_ofts *saa7113_r10_oft 122 enum saa7113_r10_ofts *saa7113_r10_ofts;
123 enum saa7113_r12_rts *saa7113_r12_rts0 123 enum saa7113_r12_rts *saa7113_r12_rts0;
124 enum saa7113_r12_rts *saa7113_r12_rts1 124 enum saa7113_r12_rts *saa7113_r12_rts1;
125 bool *saa7113_r13_adlsb; 125 bool *saa7113_r13_adlsb;
126 }; 126 };
127 127
128 #endif 128 #endif
129 129
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