1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * ARConnect IP Support (Multi core enabler: C 2 * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...)
4 * 3 *
5 * Copyright (C) 2014-15 Synopsys, Inc. (www.s 4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify
>> 7 * it under the terms of the GNU General Public License version 2 as
>> 8 * published by the Free Software Foundation.
6 */ 9 */
7 10
8 #ifndef __SOC_ARC_MCIP_H 11 #ifndef __SOC_ARC_MCIP_H
9 #define __SOC_ARC_MCIP_H 12 #define __SOC_ARC_MCIP_H
10 13
11 #include <soc/arc/aux.h> 14 #include <soc/arc/aux.h>
12 15
13 #define ARC_REG_MCIP_BCR 0x0d0 16 #define ARC_REG_MCIP_BCR 0x0d0
14 #define ARC_REG_MCIP_IDU_BCR 0x0D5 17 #define ARC_REG_MCIP_IDU_BCR 0x0D5
15 #define ARC_REG_GFRC_BUILD 0x0D6 18 #define ARC_REG_GFRC_BUILD 0x0D6
16 #define ARC_REG_MCIP_CMD 0x600 19 #define ARC_REG_MCIP_CMD 0x600
17 #define ARC_REG_MCIP_WDATA 0x601 20 #define ARC_REG_MCIP_WDATA 0x601
18 #define ARC_REG_MCIP_READBACK 0x602 21 #define ARC_REG_MCIP_READBACK 0x602
19 22
20 struct mcip_cmd { 23 struct mcip_cmd {
21 #ifdef CONFIG_CPU_BIG_ENDIAN 24 #ifdef CONFIG_CPU_BIG_ENDIAN
22 unsigned int pad:8, param:16, cmd:8; 25 unsigned int pad:8, param:16, cmd:8;
23 #else 26 #else
24 unsigned int cmd:8, param:16, pad:8; 27 unsigned int cmd:8, param:16, pad:8;
25 #endif 28 #endif
26 29
27 #define CMD_INTRPT_GENERATE_IRQ 0x01 30 #define CMD_INTRPT_GENERATE_IRQ 0x01
28 #define CMD_INTRPT_GENERATE_ACK 0x02 31 #define CMD_INTRPT_GENERATE_ACK 0x02
29 #define CMD_INTRPT_READ_STATUS 0x03 32 #define CMD_INTRPT_READ_STATUS 0x03
30 #define CMD_INTRPT_CHECK_SOURCE 0x04 33 #define CMD_INTRPT_CHECK_SOURCE 0x04
31 34
32 /* Semaphore Commands */ 35 /* Semaphore Commands */
33 #define CMD_SEMA_CLAIM_AND_READ 0x11 36 #define CMD_SEMA_CLAIM_AND_READ 0x11
34 #define CMD_SEMA_RELEASE 0x12 37 #define CMD_SEMA_RELEASE 0x12
35 38
36 #define CMD_DEBUG_SET_MASK 0x34 39 #define CMD_DEBUG_SET_MASK 0x34
37 #define CMD_DEBUG_READ_MASK 0x35 40 #define CMD_DEBUG_READ_MASK 0x35
38 #define CMD_DEBUG_SET_SELECT 0x36 41 #define CMD_DEBUG_SET_SELECT 0x36
39 #define CMD_DEBUG_READ_SELECT 0x37 42 #define CMD_DEBUG_READ_SELECT 0x37
40 43
41 #define CMD_GFRC_READ_LO 0x42 44 #define CMD_GFRC_READ_LO 0x42
42 #define CMD_GFRC_READ_HI 0x43 45 #define CMD_GFRC_READ_HI 0x43
43 #define CMD_GFRC_SET_CORE 0x47 46 #define CMD_GFRC_SET_CORE 0x47
44 #define CMD_GFRC_READ_CORE 0x48 47 #define CMD_GFRC_READ_CORE 0x48
45 48
46 #define CMD_IDU_ENABLE 0x71 49 #define CMD_IDU_ENABLE 0x71
47 #define CMD_IDU_DISABLE 0x72 50 #define CMD_IDU_DISABLE 0x72
48 #define CMD_IDU_SET_MODE 0x74 51 #define CMD_IDU_SET_MODE 0x74
49 #define CMD_IDU_READ_MODE 0x75 <<
50 #define CMD_IDU_SET_DEST 0x76 52 #define CMD_IDU_SET_DEST 0x76
51 #define CMD_IDU_ACK_CIRQ 0x79 <<
52 #define CMD_IDU_SET_MASK 0x7C 53 #define CMD_IDU_SET_MASK 0x7C
53 54
54 #define IDU_M_TRIG_LEVEL 0x0 55 #define IDU_M_TRIG_LEVEL 0x0
55 #define IDU_M_TRIG_EDGE 0x1 56 #define IDU_M_TRIG_EDGE 0x1
56 57
57 #define IDU_M_DISTRI_RR 0x0 58 #define IDU_M_DISTRI_RR 0x0
58 #define IDU_M_DISTRI_DEST 0x2 59 #define IDU_M_DISTRI_DEST 0x2
59 }; 60 };
60 61
61 struct mcip_bcr { 62 struct mcip_bcr {
62 #ifdef CONFIG_CPU_BIG_ENDIAN 63 #ifdef CONFIG_CPU_BIG_ENDIAN
63 unsigned int pad4:6, pw_dom:1, 64 unsigned int pad4:6, pw_dom:1, pad3:1,
64 idu:1, pad2:1, nu 65 idu:1, pad2:1, num_cores:6,
65 pad:1, gfrc:1, d 66 pad:1, gfrc:1, dbg:1, pw:1,
66 msg:1, sem:1, ipi 67 msg:1, sem:1, ipi:1, slv:1,
67 ver:8; 68 ver:8;
68 #else 69 #else
69 unsigned int ver:8, 70 unsigned int ver:8,
70 slv:1, ipi:1, sem 71 slv:1, ipi:1, sem:1, msg:1,
71 pw:1, dbg:1, gfrc 72 pw:1, dbg:1, gfrc:1, pad:1,
72 num_cores:6, pad2 73 num_cores:6, pad2:1, idu:1,
73 pad3:1, pw_dom:1, 74 pad3:1, pw_dom:1, pad4:6;
74 #endif 75 #endif
75 }; 76 };
76 77
77 struct mcip_idu_bcr { 78 struct mcip_idu_bcr {
78 #ifdef CONFIG_CPU_BIG_ENDIAN 79 #ifdef CONFIG_CPU_BIG_ENDIAN
79 unsigned int pad:21, cirqnum:3, ver:8; 80 unsigned int pad:21, cirqnum:3, ver:8;
80 #else 81 #else
81 unsigned int ver:8, cirqnum:3, pad:21; 82 unsigned int ver:8, cirqnum:3, pad:21;
82 #endif 83 #endif
83 }; 84 };
84 85
85 86
86 /* 87 /*
87 * Build register for IDU contains not an actu 88 * Build register for IDU contains not an actual number of supported common
88 * interrupts but an exponent of 2 which must 89 * interrupts but an exponent of 2 which must be multiplied by 4 to
89 * get a number of supported common interrupts 90 * get a number of supported common interrupts.
90 */ 91 */
91 #define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 < 92 #define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum))
92 93
93 /* 94 /*
94 * MCIP programming model 95 * MCIP programming model
95 * 96 *
96 * - Simple commands write {cmd:8,param:16} to 97 * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg
97 * (param could be irq, common_irq, core_id 98 * (param could be irq, common_irq, core_id ...)
98 * - More involved commands setup MCIP_WDATA w 99 * - More involved commands setup MCIP_WDATA with cmd specific data
99 * before invoking the simple command 100 * before invoking the simple command
100 */ 101 */
101 static inline void __mcip_cmd(unsigned int cmd 102 static inline void __mcip_cmd(unsigned int cmd, unsigned int param)
102 { 103 {
103 struct mcip_cmd buf; 104 struct mcip_cmd buf;
104 105
105 buf.pad = 0; 106 buf.pad = 0;
106 buf.cmd = cmd; 107 buf.cmd = cmd;
107 buf.param = param; 108 buf.param = param;
108 109
109 WRITE_AUX(ARC_REG_MCIP_CMD, buf); 110 WRITE_AUX(ARC_REG_MCIP_CMD, buf);
110 } 111 }
111 112
112 /* 113 /*
113 * Setup additional data for a cmd 114 * Setup additional data for a cmd
114 * Callers need to lock to ensure atomicity 115 * Callers need to lock to ensure atomicity
115 */ 116 */
116 static inline void __mcip_cmd_data(unsigned in 117 static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
117 unsigned in 118 unsigned int data)
118 { 119 {
119 write_aux_reg(ARC_REG_MCIP_WDATA, data 120 write_aux_reg(ARC_REG_MCIP_WDATA, data);
120 121
121 __mcip_cmd(cmd, param); 122 __mcip_cmd(cmd, param);
122 } <<
123 <<
124 /* <<
125 * Read MCIP register <<
126 */ <<
127 static inline unsigned int __mcip_cmd_read(uns <<
128 { <<
129 __mcip_cmd(cmd, param); <<
130 return read_aux_reg(ARC_REG_MCIP_READB <<
131 } 123 }
132 124
133 #endif 125 #endif
134 126
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