1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.s 3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 */ 4 */
5 5
6 #ifndef __SOC_ARC_TIMERS_H 6 #ifndef __SOC_ARC_TIMERS_H
7 #define __SOC_ARC_TIMERS_H 7 #define __SOC_ARC_TIMERS_H
8 8
9 #include <soc/arc/aux.h> 9 #include <soc/arc/aux.h>
10 10
11 /* Timer related Aux registers */ 11 /* Timer related Aux registers */
12 #define ARC_REG_TIMER0_LIMIT 0x23 /* tim 12 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
13 #define ARC_REG_TIMER0_CTRL 0x22 /* tim 13 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
14 #define ARC_REG_TIMER0_CNT 0x21 /* tim 14 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
15 #define ARC_REG_TIMER1_LIMIT 0x102 /* tim 15 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
16 #define ARC_REG_TIMER1_CTRL 0x101 /* tim 16 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
17 #define ARC_REG_TIMER1_CNT 0x100 /* tim 17 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
18 18
19 /* CTRL reg bits */ 19 /* CTRL reg bits */
20 #define ARC_TIMER_CTRL_IE (1 << 0) /* In 20 #define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
21 #define ARC_TIMER_CTRL_NH (1 << 1) /* Co 21 #define ARC_TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
22 22
23 #define ARC_TIMERN_MAX 0xFFFFFFFF 23 #define ARC_TIMERN_MAX 0xFFFFFFFF
24 24
25 #define ARC_REG_TIMERS_BCR 0x75 25 #define ARC_REG_TIMERS_BCR 0x75
26 26
27 struct bcr_timer { 27 struct bcr_timer {
28 #ifdef CONFIG_CPU_BIG_ENDIAN 28 #ifdef CONFIG_CPU_BIG_ENDIAN
29 unsigned int pad2:15, rtsc:1, pad1:5, 29 unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
30 #else 30 #else
31 unsigned int ver:8, t0:1, t1:1, rtc:1, 31 unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
32 #endif 32 #endif
33 }; 33 };
34 34
35 #endif 35 #endif
36 36
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