1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 2 /* 3 * arch/arm/mach-at91/include/mach/at91sam9_sd 4 * 5 * Copyright (C) 2007 Andrew Victor 6 * Copyright (C) 2007 Atmel Corporation. 7 * 8 * SDRAM Controllers (SDRAMC) - System periphe 9 * Based on AT91SAM9261 datasheet revision D. 10 */ 11 12 #ifndef AT91SAM9_SDRAMC_H 13 #define AT91SAM9_SDRAMC_H 14 15 /* SDRAM Controller (SDRAMC) registers */ 16 #define AT91_SDRAMC_MR 0x00 /* SDR 17 #define AT91_SDRAMC_MODE (0xf < 18 #define AT91_SDRAMC_MODE_NORMA 19 #define AT91_SDRAMC_MODE_NOP 20 #define AT91_SDRAMC_MODE_PRECH 21 #define AT91_SDRAMC_MODE_LMR 22 #define AT91_SDRAMC_MODE_REFRE 23 #define AT91_SDRAMC_MODE_EXT_L 24 #define AT91_SDRAMC_MODE_DEEP 25 26 #define AT91_SDRAMC_TR 0x04 /* SDR 27 #define AT91_SDRAMC_COUNT (0xfff 28 29 #define AT91_SDRAMC_CR 0x08 /* SDR 30 #define AT91_SDRAMC_NC (3 << 31 #define AT91_SDRAMC_NC_8 32 #define AT91_SDRAMC_NC_9 33 #define AT91_SDRAMC_NC_10 34 #define AT91_SDRAMC_NC_11 35 #define AT91_SDRAMC_NR (3 << 36 #define AT91_SDRAMC_NR_11 37 #define AT91_SDRAMC_NR_12 38 #define AT91_SDRAMC_NR_13 39 #define AT91_SDRAMC_NB (1 << 40 #define AT91_SDRAMC_NB_2 41 #define AT91_SDRAMC_NB_4 42 #define AT91_SDRAMC_CAS (3 << 43 #define AT91_SDRAMC_CAS_1 44 #define AT91_SDRAMC_CAS_2 45 #define AT91_SDRAMC_CAS_3 46 #define AT91_SDRAMC_DBW (1 << 47 #define AT91_SDRAMC_DBW_32 48 #define AT91_SDRAMC_DBW_16 49 #define AT91_SDRAMC_TWR (0xf < 50 #define AT91_SDRAMC_TRC (0xf < 51 #define AT91_SDRAMC_TRP (0xf < 52 #define AT91_SDRAMC_TRCD (0xf < 53 #define AT91_SDRAMC_TRAS (0xf < 54 #define AT91_SDRAMC_TXSR (0xf < 55 56 #define AT91_SDRAMC_LPR 0x10 /* SDR 57 #define AT91_SDRAMC_LPCB 58 #define AT91_SDRAMC_LPCB_DISAB 59 #define AT91_SDRAMC_LPCB_SELF_ 60 #define AT91_SDRAMC_LPCB_POWER 61 #define AT91_SDRAMC_LPCB_DEEP_ 62 #define AT91_SDRAMC_PASR 63 #define AT91_SDRAMC_TCSR 64 #define AT91_SDRAMC_DS 65 #define AT91_SDRAMC_TIMEOUT 66 #define AT91_SDRAMC_TIMEOUT_0_ 67 #define AT91_SDRAMC_TIMEOUT_64 68 #define AT91_SDRAMC_TIMEOUT_12 69 70 #define AT91_SDRAMC_IER 0x14 /* SDR 71 #define AT91_SDRAMC_IDR 0x18 /* SDR 72 #define AT91_SDRAMC_IMR 0x1C /* SDR 73 #define AT91_SDRAMC_ISR 0x20 /* SDR 74 #define AT91_SDRAMC_RES (1 << 75 76 #define AT91_SDRAMC_MDR 0x24 /* SDR 77 #define AT91_SDRAMC_MD (3 << 78 #define AT91_SDRAMC_MD_SDRAM 79 #define AT91_SDRAMC_MD_LOW_POW 80 81 #endif 82
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