1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Microchip SAMA7 UDDR Controller and DDR3 PH 4 * and bit definitions. 5 * 6 * Copyright (C) [2020] Microchip Technology I 7 * 8 * Author: Claudu Beznea <claudiu.beznea@micro 9 */ 10 11 #ifndef __SAMA7_DDR_H__ 12 #define __SAMA7_DDR_H__ 13 14 /* DDR3PHY */ 15 #define DDR3PHY_PIR 16 #define DDR3PHY_PIR_DLLBYP 17 #define DDR3PHY_PIR_ITMSRST 18 #define DDR3PHY_PIR_DLLLOCK 19 #define DDR3PHY_PIR_DLLSRST 20 #define DDR3PHY_PIR_INIT 21 22 #define DDR3PHY_PGCR 23 #define DDR3PHY_PGCR_CKDV1 24 #define DDR3PHY_PGCR_CKDV0 25 26 #define DDR3PHY_PGSR 27 #define DDR3PHY_PGSR_IDONE 28 29 #define DDR3PHY_ACDLLCR 30 #define DDR3PHY_ACDLLCR_DLLSRST 31 32 #define DDR3PHY_ACIOCR 33 #define DDR3PHY_ACIOCR_CSPDD_CS0 34 #define DDR3PHY_ACIOCR_CKPDD_CK0 35 #define DDR3PHY_ACIORC_ACPDD 36 37 #define DDR3PHY_DXCCR 38 #define DDR3PHY_DXCCR_DXPDR 39 40 #define DDR3PHY_DSGCR 41 #define DDR3PHY_DSGCR_ODTPDD_ODT0 42 43 #define DDR3PHY_ZQ0SR0 44 #define DDR3PHY_ZQ0SR0_PDO_OFF 45 #define DDR3PHY_ZQ0SR0_PUO_OFF 46 #define DDR3PHY_ZQ0SR0_PDODT_OFF 47 #define DDR3PHY_ZQ0SRO_PUODT_OFF 48 49 #define DDR3PHY_DX0DLLCR 50 #define DDR3PHY_DX1DLLCR 51 #define DDR3PHY_DXDLLCR_DLLDIS 52 53 /* UDDRC */ 54 #define UDDRC_STAT 55 #define UDDRC_STAT_SELFREF_TYPE_DIS 56 #define UDDRC_STAT_SELFREF_TYPE_PHY 57 #define UDDRC_STAT_SELFREF_TYPE_SW 58 #define UDDRC_STAT_SELFREF_TYPE_AUTO 59 #define UDDRC_STAT_SELFREF_TYPE_MSK 60 #define UDDRC_STAT_OPMODE_INIT 61 #define UDDRC_STAT_OPMODE_NORMAL 62 #define UDDRC_STAT_OPMODE_PWRDOWN 63 #define UDDRC_STAT_OPMODE_SELF_REFRESH 64 #define UDDRC_STAT_OPMODE_MSK 65 66 #define UDDRC_PWRCTL 67 #define UDDRC_PWRCTL_SELFREF_EN 68 #define UDDRC_PWRCTL_SELFREF_SW 69 70 #define UDDRC_DFIMISC 71 #define UDDRC_DFIMISC_DFI_INIT_COMPLET 72 73 #define UDDRC_SWCTRL 74 #define UDDRC_SWCTRL_SW_DONE 75 76 #define UDDRC_SWSTAT 77 #define UDDRC_SWSTAT_SW_DONE_ACK 78 79 #define UDDRC_PSTAT 80 #define UDDRC_PSTAT_ALL_PORTS 81 82 #define UDDRC_PCTRL_0 83 #define UDDRC_PCTRL_1 84 #define UDDRC_PCTRL_2 85 #define UDDRC_PCTRL_3 86 #define UDDRC_PCTRL_4 87 88 #endif /* __SAMA7_DDR_H__ */ 89
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