1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electro 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Lin Huang <hl@rock-chips.com> 4 * Author: Lin Huang <hl@rock-chips.com> 5 */ 5 */ 6 #ifndef __SOC_ROCKCHIP_SIP_H 6 #ifndef __SOC_ROCKCHIP_SIP_H 7 #define __SOC_ROCKCHIP_SIP_H 7 #define __SOC_ROCKCHIP_SIP_H 8 8 9 #define ROCKCHIP_SIP_DRAM_FREQ 9 #define ROCKCHIP_SIP_DRAM_FREQ 0x82000008 10 #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 10 #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00 11 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 11 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01 12 #define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE 12 #define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE 0x02 13 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR 13 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR 0x03 14 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW 14 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW 0x04 15 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 15 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05 16 #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 16 #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 17 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 17 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 18 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 18 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 19 19 20 #endif 20 #endif 21 21
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