1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Functions and macros to control the flowcon 2 * Functions and macros to control the flowcontroller
4 * 3 *
5 * Copyright (c) 2010-2012, NVIDIA Corporation 4 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms and conditions of the GNU General Public License,
>> 8 * version 2, as published by the Free Software Foundation.
>> 9 *
>> 10 * This program is distributed in the hope that it will be useful, but WITHOUT
>> 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> 13 * more details.
>> 14 *
>> 15 * You should have received a copy of the GNU General Public License
>> 16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
6 */ 17 */
7 18
8 #ifndef __SOC_TEGRA_FLOWCTRL_H__ 19 #ifndef __SOC_TEGRA_FLOWCTRL_H__
9 #define __SOC_TEGRA_FLOWCTRL_H__ 20 #define __SOC_TEGRA_FLOWCTRL_H__
10 21
11 #define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 22 #define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
12 #define FLOW_CTRL_WAITEVENT (2 << 23 #define FLOW_CTRL_WAITEVENT (2 << 29)
13 #define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 24 #define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
14 #define FLOW_CTRL_JTAG_RESUME (1 << 25 #define FLOW_CTRL_JTAG_RESUME (1 << 28)
15 #define FLOW_CTRL_SCLK_RESUME (1 << 26 #define FLOW_CTRL_SCLK_RESUME (1 << 27)
16 #define FLOW_CTRL_HALT_CPU_IRQ (1 << 27 #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
17 #define FLOW_CTRL_HALT_CPU_FIQ (1 << 28 #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
18 #define FLOW_CTRL_HALT_LIC_IRQ (1 << 29 #define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
19 #define FLOW_CTRL_HALT_LIC_FIQ (1 << 30 #define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
20 #define FLOW_CTRL_HALT_GIC_IRQ (1 << 31 #define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
21 #define FLOW_CTRL_HALT_GIC_FIQ (1 << 32 #define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
22 #define FLOW_CTRL_CPU0_CSR 0x8 33 #define FLOW_CTRL_CPU0_CSR 0x8
23 #define FLOW_CTRL_CSR_INTR_FLAG (1 << 34 #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
24 #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 35 #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
25 #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 36 #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
26 #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 37 #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
27 #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ 38 #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
28 FLOW_CTRL_CSR_ENABLE_EXT_NCPU 39 FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
29 FLOW_CTRL_CSR_ENABLE_EXT_CRAIL 40 FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
30 #define FLOW_CTRL_CSR_ENABLE (1 << 41 #define FLOW_CTRL_CSR_ENABLE (1 << 0)
31 #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 42 #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
32 #define FLOW_CTRL_CPU1_CSR 0x18 43 #define FLOW_CTRL_CPU1_CSR 0x18
33 44
34 #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 45 #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
35 #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP 46 #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
36 #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 47 #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
37 48
38 #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 49 #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
39 #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP 50 #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
40 #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP 51 #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
41 52
42 #ifndef __ASSEMBLY__ 53 #ifndef __ASSEMBLY__
43 #ifdef CONFIG_SOC_TEGRA_FLOWCTRL 54 #ifdef CONFIG_SOC_TEGRA_FLOWCTRL
44 u32 flowctrl_read_cpu_csr(unsigned int cpuid); 55 u32 flowctrl_read_cpu_csr(unsigned int cpuid);
45 void flowctrl_write_cpu_csr(unsigned int cpuid 56 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
46 void flowctrl_write_cpu_halt(unsigned int cpui 57 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
47 58
48 void flowctrl_cpu_suspend_enter(unsigned int c 59 void flowctrl_cpu_suspend_enter(unsigned int cpuid);
49 void flowctrl_cpu_suspend_exit(unsigned int cp 60 void flowctrl_cpu_suspend_exit(unsigned int cpuid);
50 #else 61 #else
51 static inline u32 flowctrl_read_cpu_csr(unsign 62 static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
52 { 63 {
53 return 0; 64 return 0;
54 } 65 }
55 66
56 static inline void flowctrl_write_cpu_csr(unsi 67 static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
57 { 68 {
58 } 69 }
59 70
60 static inline void flowctrl_write_cpu_halt(uns 71 static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
61 72
62 static inline void flowctrl_cpu_suspend_enter( 73 static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
63 { 74 {
64 } 75 }
65 76
66 static inline void flowctrl_cpu_suspend_exit(u 77 static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
67 { 78 {
68 } 79 }
69 #endif /* CONFIG_SOC_TEGRA_FLOWCTRL */ 80 #endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
70 #endif /* __ASSEMBLY */ 81 #endif /* __ASSEMBLY */
71 #endif /* __SOC_TEGRA_FLOWCTRL_H__ */ 82 #endif /* __SOC_TEGRA_FLOWCTRL_H__ */
72 83
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