1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * Copyright (c) 2012-2023, NVIDIA CORPORATION !! 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 */ 4 */
5 5
6 #ifndef __SOC_TEGRA_FUSE_H__ 6 #ifndef __SOC_TEGRA_FUSE_H__
7 #define __SOC_TEGRA_FUSE_H__ 7 #define __SOC_TEGRA_FUSE_H__
8 8
9 #include <linux/types.h> 9 #include <linux/types.h>
10 10
11 #define TEGRA20 0x20 11 #define TEGRA20 0x20
12 #define TEGRA30 0x30 12 #define TEGRA30 0x30
13 #define TEGRA114 0x35 13 #define TEGRA114 0x35
14 #define TEGRA124 0x40 14 #define TEGRA124 0x40
15 #define TEGRA132 0x13 15 #define TEGRA132 0x13
16 #define TEGRA210 0x21 16 #define TEGRA210 0x21
17 #define TEGRA186 0x18 17 #define TEGRA186 0x18
18 #define TEGRA194 0x19 18 #define TEGRA194 0x19
19 #define TEGRA234 0x23 19 #define TEGRA234 0x23
20 #define TEGRA241 0x24 <<
21 #define TEGRA264 0x26 <<
22 20
23 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 21 #define TEGRA_FUSE_SKU_CALIB_0 0xf0
24 #define TEGRA30_FUSE_SATA_CALIB 0x124 22 #define TEGRA30_FUSE_SATA_CALIB 0x124
25 #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250 23 #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
26 24
27 #ifndef __ASSEMBLY__ 25 #ifndef __ASSEMBLY__
28 26
29 enum tegra_revision { 27 enum tegra_revision {
30 TEGRA_REVISION_UNKNOWN = 0, 28 TEGRA_REVISION_UNKNOWN = 0,
31 TEGRA_REVISION_A01, 29 TEGRA_REVISION_A01,
32 TEGRA_REVISION_A02, 30 TEGRA_REVISION_A02,
33 TEGRA_REVISION_A03, 31 TEGRA_REVISION_A03,
34 TEGRA_REVISION_A03p, 32 TEGRA_REVISION_A03p,
35 TEGRA_REVISION_A04, 33 TEGRA_REVISION_A04,
36 TEGRA_REVISION_MAX, 34 TEGRA_REVISION_MAX,
37 }; 35 };
38 36
39 enum tegra_platform { <<
40 TEGRA_PLATFORM_SILICON = 0, <<
41 TEGRA_PLATFORM_QT, <<
42 TEGRA_PLATFORM_SYSTEM_FPGA, <<
43 TEGRA_PLATFORM_UNIT_FPGA, <<
44 TEGRA_PLATFORM_ASIM_QT, <<
45 TEGRA_PLATFORM_ASIM_LINSIM, <<
46 TEGRA_PLATFORM_DSIM_ASIM_LINSIM, <<
47 TEGRA_PLATFORM_VERIFICATION_SIMULATION <<
48 TEGRA_PLATFORM_VDK, <<
49 TEGRA_PLATFORM_VSP, <<
50 TEGRA_PLATFORM_MAX, <<
51 }; <<
52 <<
53 struct tegra_sku_info { 37 struct tegra_sku_info {
54 int sku_id; 38 int sku_id;
55 int cpu_process_id; 39 int cpu_process_id;
56 int cpu_speedo_id; 40 int cpu_speedo_id;
57 int cpu_speedo_value; 41 int cpu_speedo_value;
58 int cpu_iddq_value; 42 int cpu_iddq_value;
59 int soc_process_id; 43 int soc_process_id;
60 int soc_speedo_id; 44 int soc_speedo_id;
61 int soc_speedo_value; 45 int soc_speedo_value;
62 int gpu_process_id; 46 int gpu_process_id;
63 int gpu_speedo_id; 47 int gpu_speedo_id;
64 int gpu_speedo_value; 48 int gpu_speedo_value;
65 enum tegra_revision revision; 49 enum tegra_revision revision;
66 enum tegra_platform platform; <<
67 }; 50 };
68 51
69 #ifdef CONFIG_ARCH_TEGRA 52 #ifdef CONFIG_ARCH_TEGRA
70 extern struct tegra_sku_info tegra_sku_info; 53 extern struct tegra_sku_info tegra_sku_info;
71 u32 tegra_read_straps(void); 54 u32 tegra_read_straps(void);
72 u32 tegra_read_ram_code(void); 55 u32 tegra_read_ram_code(void);
73 int tegra_fuse_readl(unsigned long offset, u32 56 int tegra_fuse_readl(unsigned long offset, u32 *value);
74 u32 tegra_read_chipid(void); 57 u32 tegra_read_chipid(void);
75 u8 tegra_get_chip_id(void); 58 u8 tegra_get_chip_id(void);
76 u8 tegra_get_platform(void); 59 u8 tegra_get_platform(void);
77 bool tegra_is_silicon(void); 60 bool tegra_is_silicon(void);
78 int tegra194_miscreg_mask_serror(void); <<
79 #else 61 #else
80 static struct tegra_sku_info tegra_sku_info __ 62 static struct tegra_sku_info tegra_sku_info __maybe_unused;
81 63
82 static inline u32 tegra_read_straps(void) 64 static inline u32 tegra_read_straps(void)
83 { 65 {
84 return 0; 66 return 0;
85 } 67 }
86 68
87 static inline u32 tegra_read_ram_code(void) 69 static inline u32 tegra_read_ram_code(void)
88 { 70 {
89 return 0; 71 return 0;
90 } 72 }
91 73
92 static inline int tegra_fuse_readl(unsigned lo 74 static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
93 { 75 {
94 return -ENODEV; 76 return -ENODEV;
95 } 77 }
96 78
97 static inline u32 tegra_read_chipid(void) 79 static inline u32 tegra_read_chipid(void)
98 { 80 {
99 return 0; 81 return 0;
100 } 82 }
101 83
102 static inline u8 tegra_get_chip_id(void) 84 static inline u8 tegra_get_chip_id(void)
103 { 85 {
104 return 0; 86 return 0;
105 } 87 }
106 88
107 static inline u8 tegra_get_platform(void) 89 static inline u8 tegra_get_platform(void)
108 { 90 {
109 return 0; 91 return 0;
110 } 92 }
111 93
112 static inline bool tegra_is_silicon(void) 94 static inline bool tegra_is_silicon(void)
113 { <<
114 return false; <<
115 } <<
116 <<
117 static inline int tegra194_miscreg_mask_serror <<
118 { 95 {
119 return false; 96 return false;
120 } 97 }
121 #endif 98 #endif
122 99
123 struct device *tegra_soc_device_register(void) 100 struct device *tegra_soc_device_register(void);
124 101
125 #endif /* __ASSEMBLY__ */ 102 #endif /* __ASSEMBLY__ */
126 103
127 #endif /* __SOC_TEGRA_FUSE_H__ */ 104 #endif /* __SOC_TEGRA_FUSE_H__ */
128 105
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