1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1
2 #ifndef __SOUND_AK4117_H
3 #define __SOUND_AK4117_H
4
5 /*
6 * Routines for Asahi Kasei AK4117
7 * Copyright (c) by Jaroslav Kysela <perex@pe
8 */
9
10 #define AK4117_REG_PWRDN 0x00 /* pow
11 #define AK4117_REG_CLOCK 0x01 /* clo
12 #define AK4117_REG_IO 0x02 /* inp
13 #define AK4117_REG_INT0_MASK 0x03 /* int
14 #define AK4117_REG_INT1_MASK 0x04 /* int
15 #define AK4117_REG_RCS0 0x05 /* rec
16 #define AK4117_REG_RCS1 0x06 /* rec
17 #define AK4117_REG_RCS2 0x07 /* rec
18 #define AK4117_REG_RXCSB0 0x08 /* RX
19 #define AK4117_REG_RXCSB1 0x09 /* RX
20 #define AK4117_REG_RXCSB2 0x0a /* RX
21 #define AK4117_REG_RXCSB3 0x0b /* RX
22 #define AK4117_REG_RXCSB4 0x0c /* RX
23 #define AK4117_REG_Pc0 0x0d /* bur
24 #define AK4117_REG_Pc1 0x0e /* bur
25 #define AK4117_REG_Pd0 0x0f /* bur
26 #define AK4117_REG_Pd1 0x10 /* bur
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-s
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-s
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-s
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-s
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-s
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-s
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-s
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-s
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-s
36 #define AK4117_REG_QSUB_ABSFRM 0x1a /* Q-s
37
38 /* sizes */
39 #define AK4117_REG_RXCSB_SIZE ((AK4117_REG_R
40 #define AK4117_REG_QSUB_SIZE ((AK4117_REG_Q
41
42 /* AK4117_REG_PWRDN bits */
43 #define AK4117_EXCT (1<<4) /* 0 =
44 #define AK4117_XTL1 (1<<3) /* XTL
45 #define AK4117_XTL0 (1<<2) /* XTL
46 #define AK4117_XTL_11_2896M (0)
47 #define AK4117_XTL_12_288M AK4117_XTL0
48 #define AK4117_XTL_24_576M AK4117_XTL1
49 #define AK4117_XTL_EXT (AK4117_XTL1|A
50 #define AK4117_PWN (1<<1) /* 0 =
51 #define AK4117_RST (1<<0) /* 0 =
52
53 /* AK4117_REQ_CLOCK bits */
54 #define AK4117_LP (1<<7) /* 0 =
55 #define AK4117_PKCS1 (1<<6) /* mas
56 #define AK4117_PKCS0 (1<<5)
57 #define AK4117_PKCS_512fs (0)
58 #define AK4117_PKCS_256fs AK4117_PKCS0
59 #define AK4117_PKCS_128fs AK4117_PKCS1
60 #define AK4117_DIV (1<<4) /* 0 =
61 #define AK4117_XCKS1 (1<<3) /* mas
62 #define AK4117_XCKS0 (1<<2)
63 #define AK4117_XCKS_128fs (0)
64 #define AK4117_XCKS_256fs AK4117_XCKS0
65 #define AK4117_XCKS_512fs AK4117_XCKS1
66 #define AK4117_XCKS_1024fs (AK4117_XCKS1|
67 #define AK4117_CM1 (1<<1) /* MCK
68 #define AK4117_CM0 (1<<0)
69 #define AK4117_CM_PLL (0)
70 #define AK4117_CM_XTAL (AK4117_CM0)
71 #define AK4117_CM_PLL_XTAL (AK4117_CM1)
72 #define AK4117_CM_MONITOR (AK4117_CM0|AK
73
74 /* AK4117_REG_IO */
75 #define AK4117_IPS (1<<7) /* Inp
76 #define AK4117_UOUTE (1<<6) /* U-b
77 #define AK4117_CS12 (1<<5) /* cha
78 #define AK4117_EFH2 (1<<4) /* INT
79 #define AK4117_EFH1 (1<<3)
80 #define AK4117_EFH_512LRCLK (0)
81 #define AK4117_EFH_1024LRCLK (AK4117_EFH1)
82 #define AK4117_EFH_2048LRCLK (AK4117_EFH2)
83 #define AK4117_EFH_4096LRCLK (AK4117_EFH1|A
84 #define AK4117_DIF2 (1<<2) /* aud
85 #define AK4117_DIF1 (1<<1)
86 #define AK4117_DIF0 (1<<0)
87 #define AK4117_DIF_16R (0)
88 #define AK4117_DIF_18R (AK4117_DIF0)
89 #define AK4117_DIF_20R (AK4117_DIF1)
90 #define AK4117_DIF_24R (AK4117_DIF1|A
91 #define AK4117_DIF_24L (AK4117_DIF2)
92 #define AK4117_DIF_24I2S (AK4117_DIF2|A
93
94 /* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK
95 #define AK4117_MULK (1<<7) /* mas
96 #define AK4117_MPAR (1<<6) /* mas
97 #define AK4117_MAUTO (1<<5) /* mas
98 #define AK4117_MV (1<<4) /* mas
99 #define AK4117_MAUD (1<<3) /* mas
100 #define AK4117_MSTC (1<<2) /* mas
101 #define AK4117_MCIT (1<<1) /* mas
102 #define AK4117_MQIT (1<<0) /* mas
103
104 /* AK4117_REG_RCS0 */
105 #define AK4117_UNLCK (1<<7) /* PLL
106 #define AK4117_PAR (1<<6) /* par
107 #define AK4117_AUTO (1<<5) /* Non
108 #define AK4117_V (1<<4) /* Val
109 #define AK4117_AUDION (1<<3) /* aud
110 #define AK4117_STC (1<<2) /* sam
111 #define AK4117_CINT (1<<1) /* cha
112 #define AK4117_QINT (1<<0) /* Q-s
113
114 /* AK4117_REG_RCS1 */
115 #define AK4117_DTSCD (1<<6) /* DTS
116 #define AK4117_NPCM (1<<5) /* Non
117 #define AK4117_PEM (1<<4) /* Pre
118 #define AK4117_FS3 (1<<3) /* sam
119 #define AK4117_FS2 (1<<2)
120 #define AK4117_FS1 (1<<1)
121 #define AK4117_FS0 (1<<0)
122 #define AK4117_FS_44100HZ (0)
123 #define AK4117_FS_48000HZ (AK4117_FS1)
124 #define AK4117_FS_32000HZ (AK4117_FS1|AK
125 #define AK4117_FS_88200HZ (AK4117_FS3)
126 #define AK4117_FS_96000HZ (AK4117_FS3|AK
127 #define AK4117_FS_176400HZ (AK4117_FS3|AK
128 #define AK4117_FS_192000HZ (AK4117_FS3|AK
129
130 /* AK4117_REG_RCS2 */
131 #define AK4117_CCRC (1<<1) /* CRC
132 #define AK4117_QCRC (1<<0) /* CRC
133
134 /* flags for snd_ak4117_check_rate_and_errors(
135 #define AK4117_CHECK_NO_STAT (1<<0) /* no
136 #define AK4117_CHECK_NO_RATE (1<<1) /* no
137
138 #define AK4117_CONTROLS 13
139
140 typedef void (ak4117_write_t)(void *private_da
141 typedef unsigned char (ak4117_read_t)(void *pr
142
143 enum {
144 AK4117_PARITY_ERRORS,
145 AK4117_V_BIT_ERRORS,
146 AK4117_QCRC_ERRORS,
147 AK4117_CCRC_ERRORS,
148 AK4117_NUM_ERRORS
149 };
150
151 struct ak4117 {
152 struct snd_card *card;
153 ak4117_write_t * write;
154 ak4117_read_t * read;
155 void * private_data;
156 unsigned int init: 1;
157 spinlock_t lock;
158 unsigned char regmap[5];
159 struct snd_kcontrol *kctls[AK4117_CONT
160 struct snd_pcm_substream *substream;
161 unsigned long errors[AK4117_NUM_ERRORS
162 unsigned char rcs0;
163 unsigned char rcs1;
164 unsigned char rcs2;
165 struct timer_list timer; /* sta
166 void *change_callback_private;
167 void (*change_callback)(struct ak4117
168 };
169
170 int snd_ak4117_create(struct snd_card *card, a
171 const unsigned char pgm[
172 void snd_ak4117_reg_write(struct ak4117 *ak411
173 void snd_ak4117_reinit(struct ak4117 *ak4117);
174 int snd_ak4117_build(struct ak4117 *ak4117, st
175 int snd_ak4117_external_rate(struct ak4117 *ak
176 int snd_ak4117_check_rate_and_errors(struct ak
177
178 #endif /* __SOUND_AK4117_H */
179
180
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