1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 * Definitions for CS4271 ASoC codec driver 3 * Definitions for CS4271 ASoC codec driver
4 * 4 *
5 * Copyright (c) 2010 Alexander Sverdlin <suba 5 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
6 */ 6 */
7 7
8 #ifndef __CS4271_H 8 #ifndef __CS4271_H
9 #define __CS4271_H 9 #define __CS4271_H
10 10
11 struct cs4271_platform_data { 11 struct cs4271_platform_data {
>> 12 int gpio_nreset; /* GPIO driving Reset pin, if any */
12 bool amutec_eq_bmutec; /* flag to ena 13 bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */
13 14
14 /* 15 /*
15 * The CS4271 requires its LRCLK and M 16 * The CS4271 requires its LRCLK and MCLK to be stable before its RESET
16 * line is de-asserted. That also mean 17 * line is de-asserted. That also means that clocks cannot be changed
17 * without putting the chip back into 18 * without putting the chip back into hardware reset, which also requires
18 * a complete re-initialization of all 19 * a complete re-initialization of all registers.
19 * 20 *
20 * One (undocumented) workaround is to 21 * One (undocumented) workaround is to assert and de-assert the PDN bit
21 * in the MODE2 register. This workaro 22 * in the MODE2 register. This workaround can be enabled with the
22 * following flag. 23 * following flag.
23 * 24 *
24 * Note that this is not needed in cas 25 * Note that this is not needed in case the clocks are stable
25 * throughout the entire runtime of th 26 * throughout the entire runtime of the codec.
26 */ 27 */
27 bool enable_soft_reset; 28 bool enable_soft_reset;
28 }; 29 };
29 30
30 #endif /* __CS4271_H */ 31 #endif /* __CS4271_H */
31 32
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