1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * linux/sound/cs42l42.h -- Platform data for 4 * 5 * Copyright 2016-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirr 8 * Author: Brian Austin <brian.austin@cirrus.c 9 * Author: Michael White <michael.white@cirrus 10 */ 11 12 #ifndef __CS42L42_H 13 #define __CS42L42_H 14 15 #define CS42L42_PAGE_REGISTER 0x00 /* Pag 16 #define CS42L42_WIN_START 0x00 17 #define CS42L42_WIN_LEN 0x100 18 #define CS42L42_RANGE_MIN 0x00 19 #define CS42L42_RANGE_MAX 0x7F 20 21 #define CS42L42_PAGE_10 0x1000 22 #define CS42L42_PAGE_11 0x1100 23 #define CS42L42_PAGE_12 0x1200 24 #define CS42L42_PAGE_13 0x1300 25 #define CS42L42_PAGE_15 0x1500 26 #define CS42L42_PAGE_19 0x1900 27 #define CS42L42_PAGE_1B 0x1B00 28 #define CS42L42_PAGE_1C 0x1C00 29 #define CS42L42_PAGE_1D 0x1D00 30 #define CS42L42_PAGE_1F 0x1F00 31 #define CS42L42_PAGE_20 0x2000 32 #define CS42L42_PAGE_21 0x2100 33 #define CS42L42_PAGE_23 0x2300 34 #define CS42L42_PAGE_24 0x2400 35 #define CS42L42_PAGE_25 0x2500 36 #define CS42L42_PAGE_26 0x2600 37 #define CS42L42_PAGE_27 0x2700 38 #define CS42L42_PAGE_28 0x2800 39 #define CS42L42_PAGE_29 0x2900 40 #define CS42L42_PAGE_2A 0x2A00 41 #define CS42L42_PAGE_30 0x3000 42 43 #define CS42L42_CHIP_ID 0x42A42 44 #define CS42L83_CHIP_ID 0x42A83 45 46 /* Page 0x10 Global Registers */ 47 #define CS42L42_DEVID_AB (CS42L 48 #define CS42L42_DEVID_CD (CS42L 49 #define CS42L42_DEVID_E (CS42L 50 #define CS42L42_FABID (CS42L 51 #define CS42L42_REVID (CS42L 52 #define CS42L42_FRZ_CTL (CS42L 53 54 #define CS42L42_SRC_CTL (CS42L 55 #define CS42L42_SRC_BYPASS_DAC_SHIFT 1 56 #define CS42L42_SRC_BYPASS_DAC_MASK (1 << 57 58 #define CS42L42_MCLK_STATUS (CS42L 59 60 #define CS42L42_MCLK_CTL (CS42L 61 #define CS42L42_INTERNAL_FS_SHIFT 1 62 #define CS42L42_INTERNAL_FS_MASK (1 << 63 64 #define CS42L42_SFTRAMP_RATE (CS42L 65 #define CS42L42_SLOW_START_ENABLE (CS42L 66 #define CS42L42_SLOW_START_EN_MASK GENMAS 67 #define CS42L42_SLOW_START_EN_SHIFT 4 68 #define CS42L42_I2C_DEBOUNCE (CS42L 69 #define CS42L42_I2C_STRETCH (CS42L 70 #define CS42L42_I2C_TIMEOUT (CS42L 71 72 /* Page 0x11 Power and Headset Detect Register 73 #define CS42L42_PWR_CTL1 (CS42L 74 #define CS42L42_ASP_DAO_PDN_SHIFT 7 75 #define CS42L42_ASP_DAO_PDN_MASK (1 << 76 #define CS42L42_ASP_DAI_PDN_SHIFT 6 77 #define CS42L42_ASP_DAI_PDN_MASK (1 << 78 #define CS42L42_MIXER_PDN_SHIFT 5 79 #define CS42L42_MIXER_PDN_MASK (1 << 80 #define CS42L42_EQ_PDN_SHIFT 4 81 #define CS42L42_EQ_PDN_MASK (1 << 82 #define CS42L42_HP_PDN_SHIFT 3 83 #define CS42L42_HP_PDN_MASK (1 << 84 #define CS42L42_ADC_PDN_SHIFT 2 85 #define CS42L42_ADC_PDN_MASK (1 << 86 #define CS42L42_PDN_ALL_SHIFT 0 87 #define CS42L42_PDN_ALL_MASK (1 << 88 89 #define CS42L42_PWR_CTL2 (CS42L 90 #define CS42L42_ADC_SRC_PDNB_SHIFT 0 91 #define CS42L42_ADC_SRC_PDNB_MASK (1 << 92 #define CS42L42_DAC_SRC_PDNB_SHIFT 1 93 #define CS42L42_DAC_SRC_PDNB_MASK (1 << 94 #define CS42L42_ASP_DAI1_PDN_SHIFT 2 95 #define CS42L42_ASP_DAI1_PDN_MASK (1 << 96 #define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3 97 #define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << 98 #define CS42L42_DISCHARGE_FILT_SHIFT 4 99 #define CS42L42_DISCHARGE_FILT_MASK (1 << 100 101 #define CS42L42_PWR_CTL3 102 #define CS42L42_RING_SENSE_PDNB_SHIFT 103 #define CS42L42_RING_SENSE_PDNB_MASK 104 #define CS42L42_VPMON_PDNB_SHIFT 105 #define CS42L42_VPMON_PDNB_MASK 106 #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 107 #define CS42L42_SW_CLK_STP_STAT_SEL_MASK 108 109 #define CS42L42_RSENSE_CTL1 110 #define CS42L42_RS_TRIM_R_SHIFT 111 #define CS42L42_RS_TRIM_R_MASK 112 #define CS42L42_RS_TRIM_T_SHIFT 113 #define CS42L42_RS_TRIM_T_MASK 114 #define CS42L42_HPREF_RS_SHIFT 115 #define CS42L42_HPREF_RS_MASK 116 #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 117 #define CS42L42_HSBIAS_FILT_REF_RS_MASK 118 #define CS42L42_RING_SENSE_PU_HIZ_SHIFT 119 #define CS42L42_RING_SENSE_PU_HIZ_MASK 120 121 #define CS42L42_RSENSE_CTL2 (CS42L 122 #define CS42L42_TS_RS_GATE_SHIFT 7 123 #define CS42L42_TS_RS_GATE_MAS (1 << 124 125 #define CS42L42_OSC_SWITCH (CS42L 126 #define CS42L42_SCLK_PRESENT_SHIFT 0 127 #define CS42L42_SCLK_PRESENT_MASK (1 << 128 129 #define CS42L42_OSC_SWITCH_STATUS (CS42L 130 #define CS42L42_OSC_SW_SEL_STAT_SHIFT 0 131 #define CS42L42_OSC_SW_SEL_STAT_MASK (3 << 132 #define CS42L42_OSC_PDNB_STAT_SHIFT 2 133 #define CS42L42_OSC_PDNB_STAT_MASK (1 << 134 135 #define CS42L42_RSENSE_CTL3 136 #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 137 #define CS42L42_RS_RISE_DBNCE_TIME_MASK 138 #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 139 #define CS42L42_RS_FALL_DBNCE_TIME_MASK 140 #define CS42L42_RS_PU_EN_SHIFT 141 #define CS42L42_RS_PU_EN_MASK 142 #define CS42L42_RS_INV_SHIFT 143 #define CS42L42_RS_INV_MASK 144 145 #define CS42L42_TSENSE_CTL 146 #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 147 #define CS42L42_TS_RISE_DBNCE_TIME_MASK 148 #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 149 #define CS42L42_TS_FALL_DBNCE_TIME_MASK 150 #define CS42L42_TS_INV_SHIFT 151 #define CS42L42_TS_INV_MASK 152 153 #define CS42L42_TSRS_INT_DISABLE (CS42L 154 #define CS42L42_D_RS_PLUG_DBNC_SHIFT 0 155 #define CS42L42_D_RS_PLUG_DBNC_MASK (1 << 156 #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1 157 #define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << 158 #define CS42L42_D_TS_PLUG_DBNC_SHIFT 2 159 #define CS42L42_D_TS_PLUG_DBNC_MASK (1 << 160 #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3 161 #define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << 162 163 #define CS42L42_TRSENSE_STATUS (CS42L 164 #define CS42L42_RS_PLUG_DBNC_SHIFT 0 165 #define CS42L42_RS_PLUG_DBNC_MASK (1 << 166 #define CS42L42_RS_UNPLUG_DBNC_SHIFT 1 167 #define CS42L42_RS_UNPLUG_DBNC_MASK (1 << 168 #define CS42L42_TS_PLUG_DBNC_SHIFT 2 169 #define CS42L42_TS_PLUG_DBNC_MASK (1 << 170 #define CS42L42_TS_UNPLUG_DBNC_SHIFT 3 171 #define CS42L42_TS_UNPLUG_DBNC_MASK (1 << 172 173 #define CS42L42_HSDET_CTL1 (CS42L 174 #define CS42L42_HSDET_COMP1_LVL_SHIFT 0 175 #define CS42L42_HSDET_COMP1_LVL_MASK (15 << 176 #define CS42L42_HSDET_COMP2_LVL_SHIFT 4 177 #define CS42L42_HSDET_COMP2_LVL_MASK (15 << 178 179 #define CS42L42_HSDET_COMP1_LVL_VAL 12 /* 180 #define CS42L42_HSDET_COMP2_LVL_VAL 2 /* 181 #define CS42L42_HSDET_COMP1_LVL_DEFAULT 7 /* 182 #define CS42L42_HSDET_COMP2_LVL_DEFAULT 7 /* 183 184 #define CS42L42_HSDET_CTL2 (CS42L 185 #define CS42L42_HSDET_AUTO_TIME_SHIFT 0 186 #define CS42L42_HSDET_AUTO_TIME_MASK (3 << 187 #define CS42L42_HSBIAS_REF_SHIFT 3 188 #define CS42L42_HSBIAS_REF_MASK (1 << 189 #define CS42L42_HSDET_SET_SHIFT 4 190 #define CS42L42_HSDET_SET_MASK (3 << 191 #define CS42L42_HSDET_CTRL_SHIFT 6 192 #define CS42L42_HSDET_CTRL_MASK (3 << 193 194 #define CS42L42_HS_SWITCH_CTL (CS42L 195 #define CS42L42_SW_GNDHS_HS4_SHIFT 0 196 #define CS42L42_SW_GNDHS_HS4_MASK (1 << 197 #define CS42L42_SW_GNDHS_HS3_SHIFT 1 198 #define CS42L42_SW_GNDHS_HS3_MASK (1 << 199 #define CS42L42_SW_HSB_HS4_SHIFT 2 200 #define CS42L42_SW_HSB_HS4_MASK (1 << 201 #define CS42L42_SW_HSB_HS3_SHIFT 3 202 #define CS42L42_SW_HSB_HS3_MASK (1 << 203 #define CS42L42_SW_HSB_FILT_HS4_SHIFT 4 204 #define CS42L42_SW_HSB_FILT_HS4_MASK (1 << 205 #define CS42L42_SW_HSB_FILT_HS3_SHIFT 5 206 #define CS42L42_SW_HSB_FILT_HS3_MASK (1 << 207 #define CS42L42_SW_REF_HS4_SHIFT 6 208 #define CS42L42_SW_REF_HS4_MASK (1 << 209 #define CS42L42_SW_REF_HS3_SHIFT 7 210 #define CS42L42_SW_REF_HS3_MASK (1 << 211 212 #define CS42L42_HS_DET_STATUS (CS42L 213 #define CS42L42_HSDET_TYPE_SHIFT 0 214 #define CS42L42_HSDET_TYPE_MASK (3 << 215 #define CS42L42_HSDET_COMP1_OUT_SHIFT 6 216 #define CS42L42_HSDET_COMP1_OUT_MASK (1 << 217 #define CS42L42_HSDET_COMP2_OUT_SHIFT 7 218 #define CS42L42_HSDET_COMP2_OUT_MASK (1 << 219 #define CS42L42_PLUG_CTIA 0 220 #define CS42L42_PLUG_OMTP 1 221 #define CS42L42_PLUG_HEADPHONE 2 222 #define CS42L42_PLUG_INVALID 3 223 224 #define CS42L42_HSDET_SW_COMP1 ((0 << 225 (1 << 226 (1 << 227 (0 << 228 (0 << 229 (1 << 230 (0 << 231 (1 << 232 #define CS42L42_HSDET_SW_COMP2 ((1 << 233 (0 << 234 (0 << 235 (1 << 236 (1 << 237 (0 << 238 (1 << 239 (0 << 240 #define CS42L42_HSDET_SW_TYPE1 ((0 << 241 (1 << 242 (1 << 243 (0 << 244 (0 << 245 (1 << 246 (0 << 247 (1 << 248 #define CS42L42_HSDET_SW_TYPE2 ((1 << 249 (0 << 250 (0 << 251 (1 << 252 (1 << 253 (0 << 254 (1 << 255 (0 << 256 #define CS42L42_HSDET_SW_TYPE3 ((1 << 257 (1 << 258 (0 << 259 (0 << 260 (1 << 261 (1 << 262 (1 << 263 (1 << 264 #define CS42L42_HSDET_SW_TYPE4 ((0 << 265 (1 << 266 (1 << 267 (0 << 268 (0 << 269 (1 << 270 (0 << 271 (1 << 272 273 #define CS42L42_HSDET_COMP_TYPE1 1 274 #define CS42L42_HSDET_COMP_TYPE2 2 275 #define CS42L42_HSDET_COMP_TYPE3 0 276 #define CS42L42_HSDET_COMP_TYPE4 3 277 278 #define CS42L42_HS_CLAMP_DISABLE (CS42L 279 #define CS42L42_HS_CLAMP_DISABLE_SHIFT 0 280 #define CS42L42_HS_CLAMP_DISABLE_MASK (1 << 281 282 /* Page 0x12 Clocking Registers */ 283 #define CS42L42_MCLK_SRC_SEL (CS42L 284 #define CS42L42_MCLKDIV_SHIFT 1 285 #define CS42L42_MCLKDIV_MASK (1 << 286 #define CS42L42_MCLK_SRC_SEL_SHIFT 0 287 #define CS42L42_MCLK_SRC_SEL_MASK (1 << 288 289 #define CS42L42_SPDIF_CLK_CFG (CS42L 290 #define CS42L42_FSYNC_PW_LOWER (CS42L 291 292 #define CS42L42_FSYNC_PW_UPPER 293 #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 294 #define CS42L42_FSYNC_PULSE_WIDTH_MASK 295 CS42L4 296 297 #define CS42L42_FSYNC_P_LOWER (CS42L 298 299 #define CS42L42_FSYNC_P_UPPER (CS42L 300 #define CS42L42_FSYNC_PERIOD_SHIFT 0 301 #define CS42L42_FSYNC_PERIOD_MASK (0xff 302 303 #define CS42L42_ASP_CLK_CFG (CS42L 304 #define CS42L42_ASP_SCLK_EN_SHIFT 5 305 #define CS42L42_ASP_SCLK_EN_MASK (1 << 306 #define CS42L42_ASP_MASTER_MODE 0x01 307 #define CS42L42_ASP_SLAVE_MODE 0x00 308 #define CS42L42_ASP_MODE_SHIFT 4 309 #define CS42L42_ASP_MODE_MASK (1 << 310 #define CS42L42_ASP_SCPOL_SHIFT 2 311 #define CS42L42_ASP_SCPOL_MASK (3 << 312 #define CS42L42_ASP_SCPOL_NOR 3 313 #define CS42L42_ASP_LCPOL_SHIFT 0 314 #define CS42L42_ASP_LCPOL_MASK (3 << 315 #define CS42L42_ASP_LCPOL_INV 3 316 317 #define CS42L42_ASP_FRM_CFG (CS42L 318 #define CS42L42_ASP_STP_SHIFT 4 319 #define CS42L42_ASP_STP_MASK (1 << 320 #define CS42L42_ASP_5050_SHIFT 3 321 #define CS42L42_ASP_5050_MASK (1 << 322 #define CS42L42_ASP_FSD_SHIFT 0 323 #define CS42L42_ASP_FSD_MASK (7 << 324 #define CS42L42_ASP_FSD_0_5 1 325 #define CS42L42_ASP_FSD_1_0 2 326 #define CS42L42_ASP_FSD_1_5 3 327 #define CS42L42_ASP_FSD_2_0 4 328 329 #define CS42L42_FS_RATE_EN (CS42L 330 #define CS42L42_FS_EN_SHIFT 0 331 #define CS42L42_FS_EN_MASK (0xf < 332 #define CS42L42_FS_EN_IASRC_96K 0x1 333 #define CS42L42_FS_EN_OASRC_96K 0x2 334 335 #define CS42L42_IN_ASRC_CLK (CS42L 336 #define CS42L42_CLK_IASRC_SEL_SHIFT 0 337 #define CS42L42_CLK_IASRC_SEL_MASK (1 << 338 #define CS42L42_CLK_IASRC_SEL_6 0 339 #define CS42L42_CLK_IASRC_SEL_12 1 340 341 #define CS42L42_OUT_ASRC_CLK (CS42L 342 #define CS42L42_CLK_OASRC_SEL_SHIFT 0 343 #define CS42L42_CLK_OASRC_SEL_MASK (1 << 344 #define CS42L42_CLK_OASRC_SEL_12 1 345 346 #define CS42L42_PLL_DIV_CFG1 (CS42L 347 #define CS42L42_SCLK_PREDIV_SHIFT 0 348 #define CS42L42_SCLK_PREDIV_MASK (3 << 349 350 /* Page 0x13 Interrupt Registers */ 351 /* Interrupts */ 352 #define CS42L42_ADC_OVFL_STATUS (CS42L 353 #define CS42L42_MIXER_STATUS (CS42L 354 #define CS42L42_SRC_STATUS (CS42L 355 #define CS42L42_ASP_RX_STATUS (CS42L 356 #define CS42L42_ASP_TX_STATUS (CS42L 357 #define CS42L42_CODEC_STATUS (CS42L 358 #define CS42L42_DET_INT_STATUS1 (CS42L 359 #define CS42L42_DET_INT_STATUS2 (CS42L 360 #define CS42L42_SRCPL_INT_STATUS (CS42L 361 #define CS42L42_VPMON_STATUS (CS42L 362 #define CS42L42_PLL_LOCK_STATUS (CS42L 363 #define CS42L42_TSRS_PLUG_STATUS (CS42L 364 /* Masks */ 365 #define CS42L42_ADC_OVFL_INT_MASK (CS42L 366 #define CS42L42_ADC_OVFL_SHIFT 0 367 #define CS42L42_ADC_OVFL_MASK (1 << 368 #define CS42L42_ADC_OVFL_VAL_MASK CS42L4 369 370 #define CS42L42_MIXER_INT_MASK (CS42L 371 #define CS42L42_MIX_CHB_OVFL_SHIFT 0 372 #define CS42L42_MIX_CHB_OVFL_MASK (1 << 373 #define CS42L42_MIX_CHA_OVFL_SHIFT 1 374 #define CS42L42_MIX_CHA_OVFL_MASK (1 << 375 #define CS42L42_EQ_OVFL_SHIFT 2 376 #define CS42L42_EQ_OVFL_MASK (1 << 377 #define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3 378 #define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << 379 #define CS42L42_MIXER_VAL_MASK (CS42L 380 CS42L4 381 CS42L4 382 CS42L4 383 384 #define CS42L42_SRC_INT_MASK (CS42L 385 #define CS42L42_SRC_ILK_SHIFT 0 386 #define CS42L42_SRC_ILK_MASK (1 << 387 #define CS42L42_SRC_OLK_SHIFT 1 388 #define CS42L42_SRC_OLK_MASK (1 << 389 #define CS42L42_SRC_IUNLK_SHIFT 2 390 #define CS42L42_SRC_IUNLK_MASK (1 << 391 #define CS42L42_SRC_OUNLK_SHIFT 3 392 #define CS42L42_SRC_OUNLK_MASK (1 << 393 #define CS42L42_SRC_VAL_MASK (CS42L 394 CS42L4 395 CS42L4 396 CS42L4 397 398 #define CS42L42_ASP_RX_INT_MASK (CS42L 399 #define CS42L42_ASPRX_NOLRCK_SHIFT 0 400 #define CS42L42_ASPRX_NOLRCK_MASK (1 << 401 #define CS42L42_ASPRX_EARLY_SHIFT 1 402 #define CS42L42_ASPRX_EARLY_MASK (1 << 403 #define CS42L42_ASPRX_LATE_SHIFT 2 404 #define CS42L42_ASPRX_LATE_MASK (1 << 405 #define CS42L42_ASPRX_ERROR_SHIFT 3 406 #define CS42L42_ASPRX_ERROR_MASK (1 << 407 #define CS42L42_ASPRX_OVLD_SHIFT 4 408 #define CS42L42_ASPRX_OVLD_MASK (1 << 409 #define CS42L42_ASP_RX_VAL_MASK (CS42L 410 CS42L4 411 CS42L4 412 CS42L4 413 CS42L4 414 415 #define CS42L42_ASP_TX_INT_MASK (CS42L 416 #define CS42L42_ASPTX_NOLRCK_SHIFT 0 417 #define CS42L42_ASPTX_NOLRCK_MASK (1 << 418 #define CS42L42_ASPTX_EARLY_SHIFT 1 419 #define CS42L42_ASPTX_EARLY_MASK (1 << 420 #define CS42L42_ASPTX_LATE_SHIFT 2 421 #define CS42L42_ASPTX_LATE_MASK (1 << 422 #define CS42L42_ASPTX_SMERROR_SHIFT 3 423 #define CS42L42_ASPTX_SMERROR_MASK (1 << 424 #define CS42L42_ASP_TX_VAL_MASK (CS42L 425 CS42L4 426 CS42L4 427 CS42L4 428 429 #define CS42L42_CODEC_INT_MASK (CS42L 430 #define CS42L42_PDN_DONE_SHIFT 0 431 #define CS42L42_PDN_DONE_MASK (1 << 432 #define CS42L42_HSDET_AUTO_DONE_SHIFT 1 433 #define CS42L42_HSDET_AUTO_DONE_MASK (1 << 434 #define CS42L42_CODEC_VAL_MASK (CS42L 435 CS42L4 436 437 #define CS42L42_SRCPL_INT_MASK (CS42L 438 #define CS42L42_SRCPL_ADC_LK_SHIFT 0 439 #define CS42L42_SRCPL_ADC_LK_MASK (1 << 440 #define CS42L42_SRCPL_DAC_LK_SHIFT 2 441 #define CS42L42_SRCPL_DAC_LK_MASK (1 << 442 #define CS42L42_SRCPL_ADC_UNLK_SHIFT 5 443 #define CS42L42_SRCPL_ADC_UNLK_MASK (1 << 444 #define CS42L42_SRCPL_DAC_UNLK_SHIFT 6 445 #define CS42L42_SRCPL_DAC_UNLK_MASK (1 << 446 #define CS42L42_SRCPL_VAL_MASK (CS42L 447 CS42L4 448 CS42L4 449 CS42L4 450 451 #define CS42L42_VPMON_INT_MASK (CS42L 452 #define CS42L42_VPMON_SHIFT 0 453 #define CS42L42_VPMON_MASK (1 << 454 #define CS42L42_VPMON_VAL_MASK CS42L4 455 456 #define CS42L42_PLL_LOCK_INT_MASK (CS42L 457 #define CS42L42_PLL_LOCK_SHIFT 0 458 #define CS42L42_PLL_LOCK_MASK (1 << 459 #define CS42L42_PLL_LOCK_VAL_MASK CS42L4 460 461 #define CS42L42_TSRS_PLUG_INT_MASK (CS42L 462 #define CS42L42_RS_PLUG_SHIFT 0 463 #define CS42L42_RS_PLUG_MASK (1 << 464 #define CS42L42_RS_UNPLUG_SHIFT 1 465 #define CS42L42_RS_UNPLUG_MASK (1 << 466 #define CS42L42_TS_PLUG_SHIFT 2 467 #define CS42L42_TS_PLUG_MASK (1 << 468 #define CS42L42_TS_UNPLUG_SHIFT 3 469 #define CS42L42_TS_UNPLUG_MASK (1 << 470 #define CS42L42_TSRS_PLUG_VAL_MASK (CS42L 471 CS42L4 472 CS42L4 473 CS42L4 474 #define CS42L42_TS_PLUG 3 475 #define CS42L42_TS_UNPLUG 0 476 #define CS42L42_TS_TRANS 1 477 478 /* 479 * NOTE: PLL_START must be 0 while both ADC_PD 480 * Otherwise it will prevent FILT+ from chargi 481 */ 482 #define CS42L42_PLL_CTL1 (CS42L 483 #define CS42L42_PLL_START_SHIFT 0 484 #define CS42L42_PLL_START_MASK (1 << 485 486 #define CS42L42_PLL_DIV_FRAC0 (CS42L 487 #define CS42L42_PLL_DIV_FRAC_SHIFT 0 488 #define CS42L42_PLL_DIV_FRAC_MASK (0xff 489 490 #define CS42L42_PLL_DIV_FRAC1 (CS42L 491 #define CS42L42_PLL_DIV_FRAC2 (CS42L 492 493 #define CS42L42_PLL_DIV_INT (CS42L 494 #define CS42L42_PLL_DIV_INT_SHIFT 0 495 #define CS42L42_PLL_DIV_INT_MASK (0xff 496 497 #define CS42L42_PLL_CTL3 (CS42L 498 #define CS42L42_PLL_DIVOUT_SHIFT 0 499 #define CS42L42_PLL_DIVOUT_MASK (0xff 500 501 #define CS42L42_PLL_CAL_RATIO (CS42L 502 #define CS42L42_PLL_CAL_RATIO_SHIFT 0 503 #define CS42L42_PLL_CAL_RATIO_MASK (0xff 504 505 #define CS42L42_PLL_CTL4 (CS42L 506 #define CS42L42_PLL_MODE_SHIFT 0 507 #define CS42L42_PLL_MODE_MASK (3 << 508 509 /* Page 0x19 HP Load Detect Registers */ 510 #define CS42L42_LOAD_DET_RCSTAT (CS42L 511 #define CS42L42_RLA_STAT_SHIFT 0 512 #define CS42L42_RLA_STAT_MASK (3 << 513 #define CS42L42_RLA_STAT_15_OHM 0 514 515 #define CS42L42_LOAD_DET_DONE (CS42L 516 #define CS42L42_HPLOAD_DET_DONE_SHIFT 0 517 #define CS42L42_HPLOAD_DET_DONE_MASK (1 << 518 519 #define CS42L42_LOAD_DET_EN (CS42L 520 #define CS42L42_HP_LD_EN_SHIFT 0 521 #define CS42L42_HP_LD_EN_MASK (1 << 522 523 /* Page 0x1B Headset Interface Registers */ 524 #define CS42L42_HSBIAS_SC_AUTOCTL 525 #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 526 #define CS42L42_HSBIAS_SENSE_TRIP_MASK 527 #define CS42L42_TIP_SENSE_EN_SHIFT 528 #define CS42L42_TIP_SENSE_EN_MASK 529 #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 530 #define CS42L42_AUTO_HSBIAS_HIZ_MASK 531 #define CS42L42_HSBIAS_SENSE_EN_SHIFT 532 #define CS42L42_HSBIAS_SENSE_EN_MASK 533 534 #define CS42L42_WAKE_CTL (CS42L 535 #define CS42L42_WAKEB_CLEAR_SHIFT 0 536 #define CS42L42_WAKEB_CLEAR_MASK (1 << 537 #define CS42L42_WAKEB_MODE_SHIFT 5 538 #define CS42L42_WAKEB_MODE_MASK (1 << 539 #define CS42L42_M_HP_WAKE_SHIFT 6 540 #define CS42L42_M_HP_WAKE_MASK (1 << 541 #define CS42L42_M_MIC_WAKE_SHIFT 7 542 #define CS42L42_M_MIC_WAKE_MASK (1 << 543 544 #define CS42L42_ADC_DISABLE_MUTE 545 #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 546 #define CS42L42_ADC_DISABLE_S0_MUTE_MASK 547 548 #define CS42L42_TIPSENSE_CTL 549 #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 550 #define CS42L42_TIP_SENSE_DEBOUNCE_MASK 551 #define CS42L42_TIP_SENSE_INV_SHIFT 552 #define CS42L42_TIP_SENSE_INV_MASK 553 #define CS42L42_TIP_SENSE_CTRL_SHIFT 554 #define CS42L42_TIP_SENSE_CTRL_MASK 555 556 /* 557 * NOTE: DETECT_MODE must be 0 while both ADC_ 558 * Otherwise it will prevent FILT+ from chargi 559 */ 560 #define CS42L42_MISC_DET_CTL (CS42L 561 #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0 562 #define CS42L42_PDN_MIC_LVL_DET_MASK (1 << 563 #define CS42L42_HSBIAS_CTL_SHIFT 1 564 #define CS42L42_HSBIAS_CTL_MASK (3 << 565 #define CS42L42_DETECT_MODE_SHIFT 3 566 #define CS42L42_DETECT_MODE_MASK (3 << 567 568 #define CS42L42_MIC_DET_CTL1 (CS42L 569 #define CS42L42_HS_DET_LEVEL_SHIFT 0 570 #define CS42L42_HS_DET_LEVEL_MASK (0x3F 571 #define CS42L42_EVENT_STAT_SEL_SHIFT 6 572 #define CS42L42_EVENT_STAT_SEL_MASK (1 << 573 #define CS42L42_LATCH_TO_VP_SHIFT 7 574 #define CS42L42_LATCH_TO_VP_MASK (1 << 575 576 #define CS42L42_MIC_DET_CTL2 (CS42L 577 #define CS42L42_DEBOUNCE_TIME_SHIFT 5 578 #define CS42L42_DEBOUNCE_TIME_MASK (0x07 579 580 #define CS42L42_DET_STATUS1 (CS42L 581 #define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6 582 #define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << 583 #define CS42L42_TIP_SENSE_SHIFT 7 584 #define CS42L42_TIP_SENSE_MASK (1 << 585 586 #define CS42L42_DET_STATUS2 (CS42L 587 #define CS42L42_SHORT_TRUE_SHIFT 0 588 #define CS42L42_SHORT_TRUE_MASK (1 << 589 #define CS42L42_HS_TRUE_SHIFT 1 590 #define CS42L42_HS_TRUE_MASK (1 << 591 592 #define CS42L42_DET_INT1_MASK (CS42L 593 #define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5 594 #define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << 595 #define CS42L42_TIP_SENSE_PLUG_SHIFT 6 596 #define CS42L42_TIP_SENSE_PLUG_MASK (1 << 597 #define CS42L42_HSBIAS_SENSE_SHIFT 7 598 #define CS42L42_HSBIAS_SENSE_MASK (1 << 599 #define CS42L42_DET_INT_VAL1_MASK (CS42L 600 CS42L4 601 CS42L4 602 603 #define CS42L42_DET_INT2_MASK (CS42L 604 #define CS42L42_M_SHORT_DET_SHIFT 0 605 #define CS42L42_M_SHORT_DET_MASK (1 << 606 #define CS42L42_M_SHORT_RLS_SHIFT 1 607 #define CS42L42_M_SHORT_RLS_MASK (1 << 608 #define CS42L42_M_HSBIAS_HIZ_SHIFT 2 609 #define CS42L42_M_HSBIAS_HIZ_MASK (1 << 610 #define CS42L42_M_DETECT_FT_SHIFT 6 611 #define CS42L42_M_DETECT_FT_MASK (1 << 612 #define CS42L42_M_DETECT_TF_SHIFT 7 613 #define CS42L42_M_DETECT_TF_MASK (1 << 614 #define CS42L42_DET_INT_VAL2_MASK (CS42L 615 CS42L4 616 CS42L4 617 CS42L4 618 CS42L4 619 620 /* Page 0x1C Headset Bias Registers */ 621 #define CS42L42_HS_BIAS_CTL (CS42L 622 #define CS42L42_HSBIAS_RAMP_SHIFT 0 623 #define CS42L42_HSBIAS_RAMP_MASK (3 << 624 #define CS42L42_HSBIAS_PD_SHIFT 4 625 #define CS42L42_HSBIAS_PD_MASK (1 << 626 #define CS42L42_HSBIAS_CAPLESS_SHIFT 7 627 #define CS42L42_HSBIAS_CAPLESS_MASK (1 << 628 629 /* Page 0x1D ADC Registers */ 630 #define CS42L42_ADC_CTL (CS42L 631 #define CS42L42_ADC_NOTCH_DIS_SHIFT 632 #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 633 #define CS42L42_ADC_INV_SHIFT 634 #define CS42L42_ADC_DIG_BOOST_SHIFT 635 636 #define CS42L42_ADC_VOLUME (CS42L 637 #define CS42L42_ADC_VOL_SHIFT 0 638 639 #define CS42L42_ADC_WNF_HPF_CTL (CS42L 640 #define CS42L42_ADC_WNF_CF_SHIFT 4 641 #define CS42L42_ADC_WNF_EN_SHIFT 3 642 #define CS42L42_ADC_HPF_CF_SHIFT 1 643 #define CS42L42_ADC_HPF_EN_SHIFT 0 644 645 /* Page 0x1F DAC Registers */ 646 #define CS42L42_DAC_CTL1 (CS42L 647 #define CS42L42_DACB_INV_SHIFT 1 648 #define CS42L42_DACA_INV_SHIFT 0 649 650 #define CS42L42_DAC_CTL2 (CS42L 651 #define CS42L42_HPOUT_PULLDOWN_SHIFT 4 652 #define CS42L42_HPOUT_PULLDOWN_MASK (15 << 653 #define CS42L42_HPOUT_LOAD_SHIFT 3 654 #define CS42L42_HPOUT_LOAD_MASK (1 << 655 #define CS42L42_HPOUT_CLAMP_SHIFT 2 656 #define CS42L42_HPOUT_CLAMP_MASK (1 << 657 #define CS42L42_DAC_HPF_EN_SHIFT 1 658 #define CS42L42_DAC_HPF_EN_MASK (1 << 659 #define CS42L42_DAC_MON_EN_SHIFT 0 660 #define CS42L42_DAC_MON_EN_MASK (1 << 661 662 /* Page 0x20 HP CTL Registers */ 663 #define CS42L42_HP_CTL (CS42L 664 #define CS42L42_HP_ANA_BMUTE_SHIFT 3 665 #define CS42L42_HP_ANA_BMUTE_MASK (1 << 666 #define CS42L42_HP_ANA_AMUTE_SHIFT 2 667 #define CS42L42_HP_ANA_AMUTE_MASK (1 << 668 #define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1 669 #define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << 670 671 /* Page 0x21 Class H Registers */ 672 #define CS42L42_CLASSH_CTL (CS42L 673 674 /* Page 0x23 Mixer Volume Registers */ 675 #define CS42L42_MIXER_CHA_VOL (CS42L 676 #define CS42L42_MIXER_ADC_VOL (CS42L 677 678 #define CS42L42_MIXER_CHB_VOL (CS42L 679 #define CS42L42_MIXER_CH_VOL_SHIFT 0 680 #define CS42L42_MIXER_CH_VOL_MASK (0x3f 681 682 /* Page 0x24 EQ Registers */ 683 #define CS42L42_EQ_COEF_IN0 (CS42L 684 #define CS42L42_EQ_COEF_IN1 (CS42L 685 #define CS42L42_EQ_COEF_IN2 (CS42L 686 #define CS42L42_EQ_COEF_IN3 (CS42L 687 #define CS42L42_EQ_COEF_RW (CS42L 688 #define CS42L42_EQ_COEF_OUT0 (CS42L 689 #define CS42L42_EQ_COEF_OUT1 (CS42L 690 #define CS42L42_EQ_COEF_OUT2 (CS42L 691 #define CS42L42_EQ_COEF_OUT3 (CS42L 692 #define CS42L42_EQ_INIT_STAT (CS42L 693 #define CS42L42_EQ_START_FILT (CS42L 694 #define CS42L42_EQ_MUTE_CTL (CS42L 695 696 /* Page 0x25 Audio Port Registers */ 697 #define CS42L42_SP_RX_CH_SEL (CS42L 698 #define CS42L42_SP_RX_CHB_SEL_SHIFT 2 699 #define CS42L42_SP_RX_CHB_SEL_MASK (3 << 700 701 #define CS42L42_SP_RX_ISOC_CTL (CS42L 702 #define CS42L42_SP_RX_RSYNC_SHIFT 6 703 #define CS42L42_SP_RX_RSYNC_MASK (1 << 704 #define CS42L42_SP_RX_NSB_POS_SHIFT 3 705 #define CS42L42_SP_RX_NSB_POS_MASK (7 << 706 #define CS42L42_SP_RX_NFS_NSBB_SHIFT 2 707 #define CS42L42_SP_RX_NFS_NSBB_MASK (1 << 708 #define CS42L42_SP_RX_ISOC_MODE_SHIFT 0 709 #define CS42L42_SP_RX_ISOC_MODE_MASK (3 << 710 711 #define CS42L42_SP_RX_FS (CS42L 712 #define CS42l42_SPDIF_CH_SEL (CS42L 713 #define CS42L42_SP_TX_ISOC_CTL (CS42L 714 #define CS42L42_SP_TX_FS (CS42L 715 #define CS42L42_SPDIF_SW_CTL1 (CS42L 716 717 /* Page 0x26 SRC Registers */ 718 #define CS42L42_SRC_SDIN_FS (CS42L 719 #define CS42L42_SRC_SDIN_FS_SHIFT 0 720 #define CS42L42_SRC_SDIN_FS_MASK (0x1f 721 722 #define CS42L42_SRC_SDOUT_FS (CS42L 723 724 /* Page 0x27 DMA */ 725 #define CS42L42_SOFT_RESET_REBOOT (CS42L 726 #define CS42L42_SFT_RST_REBOOT_MASK BIT(1) 727 728 /* Page 0x28 S/PDIF Registers */ 729 #define CS42L42_SPDIF_CTL1 (CS42L 730 #define CS42L42_SPDIF_CTL2 (CS42L 731 #define CS42L42_SPDIF_CTL3 (CS42L 732 #define CS42L42_SPDIF_CTL4 (CS42L 733 734 /* Page 0x29 Serial Port TX Registers */ 735 #define CS42L42_ASP_TX_SZ_EN (CS42L 736 #define CS42L42_ASP_TX_EN_SHIFT 0 737 #define CS42L42_ASP_TX_CH_EN (CS42L 738 #define CS42L42_ASP_TX0_CH2_SHIFT 1 739 #define CS42L42_ASP_TX0_CH1_SHIFT 0 740 741 #define CS42L42_ASP_TX_CH_AP_RES (CS42L 742 #define CS42L42_ASP_TX_CH1_AP_SHIFT 7 743 #define CS42L42_ASP_TX_CH1_AP_MASK (1 << 744 #define CS42L42_ASP_TX_CH2_AP_SHIFT 6 745 #define CS42L42_ASP_TX_CH2_AP_MASK (1 << 746 #define CS42L42_ASP_TX_CH2_RES_SHIFT 2 747 #define CS42L42_ASP_TX_CH2_RES_MASK (3 << 748 #define CS42L42_ASP_TX_CH1_RES_SHIFT 0 749 #define CS42L42_ASP_TX_CH1_RES_MASK (3 << 750 #define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L 751 #define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L 752 #define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L 753 #define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L 754 #define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L 755 756 /* Page 0x2A Serial Port RX Registers */ 757 #define CS42L42_ASP_RX_DAI0_EN (CS42L 758 #define CS42L42_ASP_RX0_CH_EN_SHIFT 2 759 #define CS42L42_ASP_RX0_CH_EN_MASK (0xf < 760 #define CS42L42_ASP_RX0_CH1_SHIFT 2 761 #define CS42L42_ASP_RX0_CH2_SHIFT 3 762 #define CS42L42_ASP_RX0_CH3_SHIFT 4 763 #define CS42L42_ASP_RX0_CH4_SHIFT 5 764 765 #define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L 766 #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L 767 #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L 768 #define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L 769 #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L 770 #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L 771 #define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L 772 #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L 773 #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L 774 #define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L 775 #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L 776 #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L 777 #define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L 778 #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L 779 #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L 780 #define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L 781 #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L 782 #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L 783 784 #define CS42L42_ASP_RX_CH_AP_SHIFT 6 785 #define CS42L42_ASP_RX_CH_AP_MASK (1 << 786 #define CS42L42_ASP_RX_CH_AP_LOW 0 787 #define CS42L42_ASP_RX_CH_AP_HI 1 788 #define CS42L42_ASP_RX_CH_RES_SHIFT 0 789 #define CS42L42_ASP_RX_CH_RES_MASK (3 << 790 #define CS42L42_ASP_RX_CH_RES_32 3 791 #define CS42L42_ASP_RX_CH_RES_16 1 792 #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0 793 #define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff 794 795 /* Page 0x30 ID Registers */ 796 #define CS42L42_SUB_REVID (CS42L 797 #define CS42L42_MAX_REGISTER (CS42L 798 799 /* Defines for fracturing values spread across 800 #define CS42L42_FRAC0_VAL(val) ((val) & 0x000 801 #define CS42L42_FRAC1_VAL(val) (((val) & 0x00 802 #define CS42L42_FRAC2_VAL(val) (((val) & 0xff 803 804 #define CS42L42_NUM_SUPPLIES 5 805 #define CS42L42_BOOT_TIME_US 3000 806 #define CS42L42_PLL_DIVOUT_TIME_US 800 807 #define CS42L42_CLOCK_SWITCH_DELAY_US 150 808 #define CS42L42_PLL_LOCK_POLL_US 250 809 #define CS42L42_PLL_LOCK_TIMEOUT_US 1250 810 #define CS42L42_HP_ADC_EN_TIME_US 20000 811 #define CS42L42_PDN_DONE_POLL_US 1000 812 #define CS42L42_PDN_DONE_TIMEOUT_US 235000 813 #define CS42L42_PDN_DONE_TIME_MS 65 814 815 #endif /* __CS42L42_H */ 816
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