1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1
2 /*
3 * This file is provided under a dual BSD/GPLv
4 * redistributing this file, you may do so und
5 *
6 * Copyright(c) 2018 Intel Corporation
7 */
8
9 #ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__
10 #define __INCLUDE_SOUND_SOF_DAI_INTEL_H__
11
12 #include <sound/sof/header.h>
13
14 /* ssc1: TINTE */
15 #define SOF_DAI_INTEL_SSP_QUIRK_TINTE
16 /* ssc1: PINTE */
17 #define SOF_DAI_INTEL_SSP_QUIRK_PINTE
18 /* ssc2: SMTATF */
19 #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF
20 /* ssc2: MMRATF */
21 #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF
22 /* ssc2: PSPSTWFDFD */
23 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD
24 /* ssc2: PSPSRWFDFD */
25 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD
26 /* ssc1: LBM */
27 #define SOF_DAI_INTEL_SSP_QUIRK_LBM
28
29 /* here is the possibility to define others a
30
31 #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MA
32 #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX
33
34 /* SSP clocks control settings
35 *
36 * Macros for clks_control field in sof_ipc_da
37 */
38
39 /* mclk 0 disable */
40 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE
41 /* mclk 1 disable */
42 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE
43 /* mclk keep active */
44 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA
45 /* bclk keep active */
46 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA
47 /* fs keep active */
48 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA
49 /* bclk idle */
50 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HI
51 /* mclk early start */
52 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES
53 /* bclk early start */
54 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES
55 /* mclk always on */
56 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_AON
57
58 /* DMIC max. four controllers for eight microp
59 #define SOF_DAI_INTEL_DMIC_NUM_CTRL
60
61 /* SSP Configuration Request - SOF_IPC_DAI_SSP
62 struct sof_ipc_dai_ssp_params {
63 struct sof_ipc_hdr hdr;
64 uint16_t reserved1;
65 uint16_t mclk_id;
66
67 uint32_t mclk_rate; /* mclk freque
68 uint32_t fsync_rate; /* fsync frequ
69 uint32_t bclk_rate; /* bclk freque
70
71 /* TDM */
72 uint32_t tdm_slots;
73 uint32_t rx_slots;
74 uint32_t tx_slots;
75
76 /* data */
77 uint32_t sample_valid_bits;
78 uint16_t tdm_slot_width;
79 uint16_t reserved2; /* alignment *
80
81 /* MCLK */
82 uint32_t mclk_direction;
83
84 uint16_t frame_pulse_width;
85 uint16_t tdm_per_slot_padding_flag;
86 uint32_t clks_control;
87 uint32_t quirks;
88 uint32_t bclk_delay; /* guaranteed
89 * will be dri
90 */
91 } __packed;
92
93 /* HDA Configuration Request - SOF_IPC_DAI_HDA
94 struct sof_ipc_dai_hda_params {
95 struct sof_ipc_hdr hdr;
96 uint32_t link_dma_ch;
97 uint32_t rate;
98 uint32_t channels;
99 } __packed;
100
101 /* ALH Configuration Request - SOF_IPC_DAI_ALH
102 struct sof_ipc_dai_alh_params {
103 struct sof_ipc_hdr hdr;
104 uint32_t stream_id;
105 uint32_t rate;
106 uint32_t channels;
107
108 /* reserved for future use */
109 uint32_t reserved[13];
110 } __packed;
111
112 /* DMIC Configuration Request - SOF_IPC_DAI_DM
113
114 /* This struct is defined per 2ch PDM controll
115 * Normally it is sufficient to set the used m
116 * and keep other parameters as zero. The cust
117 *
118 * 1. If a device mixes different microphones
119 * and/or the absolute polarity matters the PC
120 * can be inverted with the controls.
121 *
122 * 2. If the microphones in a stereo pair do n
123 * in desired order due to board schematics ch
124 * the clk_edge parameter.
125 *
126 * 3. If PDM bit errors are seen in capture (p
127 * that delays the sampling time of data by ha
128 * can be tried for improvement. However there
129 * data integrity problems.
130 */
131 struct sof_ipc_dai_dmic_pdm_ctrl {
132 struct sof_ipc_hdr hdr;
133 uint16_t id; /**< PDM contr
134
135 uint16_t enable_mic_a; /**< Use A (le
136 uint16_t enable_mic_b; /**< Use B (ri
137
138 uint16_t polarity_mic_a; /**< Optional
139 uint16_t polarity_mic_b; /**< Optional
140
141 uint16_t clk_edge; /**< Optionall
142 uint16_t skew; /**< Adjust PD
143
144 uint16_t reserved[3]; /**< Make sure
145 } __packed;
146
147 /* This struct contains the global settings fo
148 * version number used in configuration data i
149 * device driver src/drivers/dmic.c need to ma
150 * initial value 1 if updates done for the to
151 * of the microphone.
152 *
153 * Note: The microphone clock (pdmclk_min, pdm
154 * parameters need to be set as defined in mic
155 * range 1.0 - 3.2 MHz is usually supported mi
156 * multi-mode capable and there may be denied
157 * the modes. In such case set the clock range
158 * avoid the driver to set clock to an illegal
159 *
160 * The duty cycle could be set to 48-52% if no
161 * parameters can be altered within data sheet
162 * required audio application performance powe
163 *
164 * The microphone clock needs to be usually ab
165 * sample rate. With highest sample rates abov
166 * somewhat.
167 *
168 * The parameter wake_up_time describes how lo
169 * for the data line to produce valid output f
170 * will mute the captured audio for the given
171 * parameter is used to prevent too short cloc
172 * will keep the clock active after capture st
173 * met. The unit for both is microseconds (us)
174 * treated as an error.
175 */
176 struct sof_ipc_dai_dmic_params {
177 struct sof_ipc_hdr hdr;
178 uint32_t driver_ipc_version; /**< V
179
180 uint32_t pdmclk_min; /**< Minimum m
181 uint32_t pdmclk_max; /**< Maximum m
182
183 uint32_t fifo_fs; /**< FIFO samp
184 uint32_t reserved_1; /**< Reserved
185 uint16_t fifo_bits; /**< FIFO word
186 uint16_t fifo_bits_b; /**< Deprecate
187
188 uint16_t duty_min; /**< Min. mic
189 uint16_t duty_max; /**< Max. mic
190
191 uint32_t num_pdm_active; /**< Number o
192 /**< Range is
193
194 uint32_t wake_up_time; /**< Time
195 uint32_t min_clock_on_time; /**< Min.
196 uint32_t unmute_ramp_time; /**< Lengt
197
198 /* reserved for future use */
199 uint32_t reserved[5];
200
201 /**< PDM controllers configuration */
202 struct sof_ipc_dai_dmic_pdm_ctrl pdm[S
203 } __packed;
204
205 #endif
206
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