1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1
2 /*
3 * This file is provided under a dual BSD/GPLv
4 * redistributing this file, you may do so und
5 *
6 * Copyright(c) 2018 Intel Corporation
7 */
8
9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
11
12 #include <sound/sof/header.h>
13
14 /*
15 * Component
16 */
17
18 /* types of component */
19 enum sof_comp_type {
20 SOF_COMP_NONE = 0,
21 SOF_COMP_HOST,
22 SOF_COMP_DAI,
23 SOF_COMP_SG_HOST, /**< scatter g
24 SOF_COMP_SG_DAI, /**< scatter g
25 SOF_COMP_VOLUME,
26 SOF_COMP_MIXER,
27 SOF_COMP_MUX,
28 SOF_COMP_SRC,
29 SOF_COMP_DEPRECATED0, /* Formerly SOF_
30 SOF_COMP_TONE,
31 SOF_COMP_DEPRECATED1, /* Formerly SOF_
32 SOF_COMP_BUFFER,
33 SOF_COMP_EQ_IIR,
34 SOF_COMP_EQ_FIR,
35 SOF_COMP_KEYWORD_DETECT,
36 SOF_COMP_KPB, /* A k
37 SOF_COMP_SELECTOR, /**< c
38 SOF_COMP_DEMUX,
39 SOF_COMP_ASRC, /**< Asynchron
40 SOF_COMP_DCBLOCK,
41 SOF_COMP_SMART_AMP, /**< s
42 SOF_COMP_MODULE_ADAPTER,
43 /* keep FILEREAD/FILEWRITE as the last
44 SOF_COMP_FILEREAD = 10000, /**< h
45 SOF_COMP_FILEWRITE = 10001, /**< h
46 };
47
48 /* XRUN action for component */
49 #define SOF_XRUN_STOP 1 /**< s
50 #define SOF_XRUN_UNDER_ZERO 2 /**< s
51 #define SOF_XRUN_OVER_NULL 4 /**< s
52
53 /* create new generic component - SOF_IPC_TPLG
54 struct sof_ipc_comp {
55 struct sof_ipc_cmd_hdr hdr;
56 uint32_t id;
57 enum sof_comp_type type;
58 uint32_t pipeline_id;
59 uint32_t core;
60
61 /* extended data length, 0 if no exten
62 uint32_t ext_data_length;
63 } __packed __aligned(4);
64
65 /*
66 * Component Buffers
67 */
68
69 /*
70 * SOF memory capabilities, add new ones at th
71 */
72 #define SOF_MEM_CAPS_RAM BIT(0)
73 #define SOF_MEM_CAPS_ROM BIT(1)
74 #define SOF_MEM_CAPS_EXT BIT(2)
75 #define SOF_MEM_CAPS_LP BIT(3)
76 #define SOF_MEM_CAPS_HP BIT(4)
77 #define SOF_MEM_CAPS_DMA BIT(5)
78 #define SOF_MEM_CAPS_CACHE BIT(6)
79 #define SOF_MEM_CAPS_EXEC BIT(7)
80 #define SOF_MEM_CAPS_L3 BIT(8)
81
82 /*
83 * overrun will cause ring buffer overwrite, i
84 */
85 #define SOF_BUF_OVERRUN_PERMITTED BIT(0)
86
87 /*
88 * underrun will cause readback of 0s, instead
89 */
90 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1)
91
92 /* the UUID size in bytes, shared between FW a
93 #define SOF_UUID_SIZE 16
94
95 /* create new component buffer - SOF_IPC_TPLG_
96 struct sof_ipc_buffer {
97 struct sof_ipc_comp comp;
98 uint32_t size; /**< buffer si
99 uint32_t caps; /**< SOF_MEM_C
100 uint32_t flags; /**< SOF_BUF_
101 uint32_t reserved; /**< reserved
102 } __packed __aligned(4);
103
104 /* generic component config data - must always
105 struct sof_ipc_comp_config {
106 struct sof_ipc_cmd_hdr hdr;
107 uint32_t periods_sink; /**< 0 means v
108 uint32_t periods_source;/**< 0 means v
109 uint32_t reserved1; /**< reserved
110 uint32_t frame_fmt; /**< SOF_IPC_F
111 uint32_t xrun_action;
112
113 /* reserved for future use */
114 uint32_t reserved[2];
115 } __packed __aligned(4);
116
117 /* generic host component */
118 struct sof_ipc_comp_host {
119 struct sof_ipc_comp comp;
120 struct sof_ipc_comp_config config;
121 uint32_t direction; /**< SOF_IPC_S
122 uint32_t no_irq; /**< don't sen
123 uint32_t dmac_config; /**< DMA engine
124 } __packed __aligned(4);
125
126 /* generic DAI component */
127 struct sof_ipc_comp_dai {
128 struct sof_ipc_comp comp;
129 struct sof_ipc_comp_config config;
130 uint32_t direction; /**< SOF_IPC_S
131 uint32_t dai_index; /**< index of
132 uint32_t type; /**< DAI type
133 uint32_t reserved; /**< reserved
134 } __packed __aligned(4);
135
136 /* generic mixer component */
137 struct sof_ipc_comp_mixer {
138 struct sof_ipc_comp comp;
139 struct sof_ipc_comp_config config;
140 } __packed __aligned(4);
141
142 /* volume ramping types */
143 enum sof_volume_ramp {
144 SOF_VOLUME_LINEAR = 0,
145 SOF_VOLUME_LOG,
146 SOF_VOLUME_LINEAR_ZC,
147 SOF_VOLUME_LOG_ZC,
148 SOF_VOLUME_WINDOWS_FADE,
149 SOF_VOLUME_WINDOWS_NO_FADE,
150 };
151
152 /* generic volume component */
153 struct sof_ipc_comp_volume {
154 struct sof_ipc_comp comp;
155 struct sof_ipc_comp_config config;
156 uint32_t channels;
157 uint32_t min_value;
158 uint32_t max_value;
159 uint32_t ramp; /**< SOF_VOLUM
160 uint32_t initial_ramp; /**< ramp spac
161 } __packed __aligned(4);
162
163 /* generic SRC component */
164 struct sof_ipc_comp_src {
165 struct sof_ipc_comp comp;
166 struct sof_ipc_comp_config config;
167 /* either source or sink rate must be
168 uint32_t source_rate; /**< source ra
169 uint32_t sink_rate; /**< sink rate
170 uint32_t rate_mask; /**< SOF_RATE_
171 } __packed __aligned(4);
172
173 /* generic ASRC component */
174 struct sof_ipc_comp_asrc {
175 struct sof_ipc_comp comp;
176 struct sof_ipc_comp_config config;
177 /* either source or sink rate must be
178 uint32_t source_rate; /**< D
179 /**< u
180 /**< t
181 uint32_t sink_rate; /**< D
182 /**< u
183 /**< t
184 uint32_t asynchronous_mode; /**< s
185 /**< W
186 /**< c
187 uint32_t operation_mode; /**< p
188 /**< A
189 /**< o
190 /**< n
191 /**< I
192 /**< a
193 /**< n
194
195 /* reserved for future use */
196 uint32_t reserved[4];
197 } __packed __aligned(4);
198
199 /* generic MUX component */
200 struct sof_ipc_comp_mux {
201 struct sof_ipc_comp comp;
202 struct sof_ipc_comp_config config;
203 } __packed __aligned(4);
204
205 /* generic tone generator component */
206 struct sof_ipc_comp_tone {
207 struct sof_ipc_comp comp;
208 struct sof_ipc_comp_config config;
209 int32_t sample_rate;
210 int32_t frequency;
211 int32_t amplitude;
212 int32_t freq_mult;
213 int32_t ampl_mult;
214 int32_t length;
215 int32_t period;
216 int32_t repeats;
217 int32_t ramp_step;
218 } __packed __aligned(4);
219
220 /** \brief Types of processing components */
221 enum sof_ipc_process_type {
222 SOF_PROCESS_NONE = 0, /**< N
223 SOF_PROCESS_EQFIR, /**< I
224 SOF_PROCESS_EQIIR, /**< I
225 SOF_PROCESS_KEYWORD_DETECT, /**< K
226 SOF_PROCESS_KPB, /**< K
227 SOF_PROCESS_CHAN_SELECTOR, /**< C
228 SOF_PROCESS_MUX,
229 SOF_PROCESS_DEMUX,
230 SOF_PROCESS_DCBLOCK,
231 SOF_PROCESS_SMART_AMP, /**< Smart Amp
232 };
233
234 /* generic "effect", "codec" or proprietary pr
235 struct sof_ipc_comp_process {
236 struct sof_ipc_comp comp;
237 struct sof_ipc_comp_config config;
238 uint32_t size; /**< size of bespoke d
239 uint32_t type; /**< sof_ipc_process_t
240
241 /* reserved for future use */
242 uint32_t reserved[7];
243
244 unsigned char data[];
245 } __packed __aligned(4);
246
247 /* frees components, buffers and pipelines
248 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_F
249 */
250 struct sof_ipc_free {
251 struct sof_ipc_cmd_hdr hdr;
252 uint32_t id;
253 } __packed __aligned(4);
254
255 struct sof_ipc_comp_reply {
256 struct sof_ipc_reply rhdr;
257 uint32_t id;
258 uint32_t offset;
259 } __packed __aligned(4);
260
261 /*
262 * Pipeline
263 */
264
265 /** \brief Types of pipeline scheduling time d
266 enum sof_ipc_pipe_sched_time_domain {
267 SOF_TIME_DOMAIN_DMA = 0, /**< D
268 SOF_TIME_DOMAIN_TIMER, /**< T
269 };
270
271 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
272 struct sof_ipc_pipe_new {
273 struct sof_ipc_cmd_hdr hdr;
274 uint32_t comp_id; /**< component
275 uint32_t pipeline_id; /**< pipeline
276 uint32_t sched_id; /**< Schedulin
277 uint32_t core; /**< core we r
278 uint32_t period; /**< execution
279 uint32_t priority; /**< priority
280 uint32_t period_mips; /**< worst cas
281 uint32_t frames_per_sched;/**< output
282 uint32_t xrun_limit_usecs; /**< report
283 uint32_t time_domain; /**< schedulin
284 } __packed __aligned(4);
285
286 /* pipeline construction complete - SOF_IPC_TP
287 struct sof_ipc_pipe_ready {
288 struct sof_ipc_cmd_hdr hdr;
289 uint32_t comp_id;
290 } __packed __aligned(4);
291
292 struct sof_ipc_pipe_free {
293 struct sof_ipc_cmd_hdr hdr;
294 uint32_t comp_id;
295 } __packed __aligned(4);
296
297 /* connect two components in pipeline - SOF_IP
298 struct sof_ipc_pipe_comp_connect {
299 struct sof_ipc_cmd_hdr hdr;
300 uint32_t source_id;
301 uint32_t sink_id;
302 } __packed __aligned(4);
303
304 /* external events */
305 enum sof_event_types {
306 SOF_EVENT_NONE = 0,
307 SOF_KEYWORD_DETECT_DAPM_EVENT,
308 };
309
310 #endif
311
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