1 /* SPDX-License-Identifier: (GPL-2.0-only OR B !! 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* 2 /*
3 * This file is provided under a dual BSD/GPLv 3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so und 4 * redistributing this file, you may do so under either license.
5 * 5 *
6 * Copyright(c) 2018 Intel Corporation !! 6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
7 */ 7 */
8 8
9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
11 11
12 #include <sound/sof/header.h> 12 #include <sound/sof/header.h>
13 13
14 /* 14 /*
15 * Component 15 * Component
16 */ 16 */
17 17
18 /* types of component */ 18 /* types of component */
19 enum sof_comp_type { 19 enum sof_comp_type {
20 SOF_COMP_NONE = 0, 20 SOF_COMP_NONE = 0,
21 SOF_COMP_HOST, 21 SOF_COMP_HOST,
22 SOF_COMP_DAI, 22 SOF_COMP_DAI,
23 SOF_COMP_SG_HOST, /**< scatter g 23 SOF_COMP_SG_HOST, /**< scatter gather variant */
24 SOF_COMP_SG_DAI, /**< scatter g 24 SOF_COMP_SG_DAI, /**< scatter gather variant */
25 SOF_COMP_VOLUME, 25 SOF_COMP_VOLUME,
26 SOF_COMP_MIXER, 26 SOF_COMP_MIXER,
27 SOF_COMP_MUX, 27 SOF_COMP_MUX,
28 SOF_COMP_SRC, 28 SOF_COMP_SRC,
29 SOF_COMP_DEPRECATED0, /* Formerly SOF_ !! 29 SOF_COMP_SPLITTER,
30 SOF_COMP_TONE, 30 SOF_COMP_TONE,
31 SOF_COMP_DEPRECATED1, /* Formerly SOF_ !! 31 SOF_COMP_SWITCH,
32 SOF_COMP_BUFFER, 32 SOF_COMP_BUFFER,
33 SOF_COMP_EQ_IIR, 33 SOF_COMP_EQ_IIR,
34 SOF_COMP_EQ_FIR, 34 SOF_COMP_EQ_FIR,
35 SOF_COMP_KEYWORD_DETECT, 35 SOF_COMP_KEYWORD_DETECT,
36 SOF_COMP_KPB, /* A k 36 SOF_COMP_KPB, /* A key phrase buffer component */
37 SOF_COMP_SELECTOR, /**< c 37 SOF_COMP_SELECTOR, /**< channel selector component */
38 SOF_COMP_DEMUX, 38 SOF_COMP_DEMUX,
39 SOF_COMP_ASRC, /**< Asynchron 39 SOF_COMP_ASRC, /**< Asynchronous sample rate converter */
40 SOF_COMP_DCBLOCK, <<
41 SOF_COMP_SMART_AMP, /**< s <<
42 SOF_COMP_MODULE_ADAPTER, <<
43 /* keep FILEREAD/FILEWRITE as the last 40 /* keep FILEREAD/FILEWRITE as the last ones */
44 SOF_COMP_FILEREAD = 10000, /**< h 41 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */
45 SOF_COMP_FILEWRITE = 10001, /**< h 42 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
46 }; 43 };
47 44
48 /* XRUN action for component */ 45 /* XRUN action for component */
49 #define SOF_XRUN_STOP 1 /**< s 46 #define SOF_XRUN_STOP 1 /**< stop stream */
50 #define SOF_XRUN_UNDER_ZERO 2 /**< s 47 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */
51 #define SOF_XRUN_OVER_NULL 4 /**< s 48 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */
52 49
53 /* create new generic component - SOF_IPC_TPLG 50 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
54 struct sof_ipc_comp { 51 struct sof_ipc_comp {
55 struct sof_ipc_cmd_hdr hdr; 52 struct sof_ipc_cmd_hdr hdr;
56 uint32_t id; 53 uint32_t id;
57 uint32_t type; !! 54 enum sof_comp_type type;
58 uint32_t pipeline_id; 55 uint32_t pipeline_id;
59 uint32_t core; 56 uint32_t core;
60 57
61 /* extended data length, 0 if no exten !! 58 /* reserved for future use */
62 uint32_t ext_data_length; !! 59 uint32_t reserved[1];
63 } __packed __aligned(4); !! 60 } __packed;
64 61
65 /* 62 /*
66 * Component Buffers 63 * Component Buffers
67 */ 64 */
68 65
69 /* 66 /*
70 * SOF memory capabilities, add new ones at th 67 * SOF memory capabilities, add new ones at the end
71 */ 68 */
72 #define SOF_MEM_CAPS_RAM BIT(0) !! 69 #define SOF_MEM_CAPS_RAM (1 << 0)
73 #define SOF_MEM_CAPS_ROM BIT(1) !! 70 #define SOF_MEM_CAPS_ROM (1 << 1)
74 #define SOF_MEM_CAPS_EXT BIT(2) !! 71 #define SOF_MEM_CAPS_EXT (1 << 2) /**< external */
75 #define SOF_MEM_CAPS_LP BIT(3) !! 72 #define SOF_MEM_CAPS_LP (1 << 3) /**< low power */
76 #define SOF_MEM_CAPS_HP BIT(4) !! 73 #define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */
77 #define SOF_MEM_CAPS_DMA BIT(5) !! 74 #define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */
78 #define SOF_MEM_CAPS_CACHE BIT(6) !! 75 #define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */
79 #define SOF_MEM_CAPS_EXEC BIT(7) !! 76 #define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */
80 #define SOF_MEM_CAPS_L3 BIT(8) <<
81 <<
82 /* <<
83 * overrun will cause ring buffer overwrite, i <<
84 */ <<
85 #define SOF_BUF_OVERRUN_PERMITTED BIT(0) <<
86 <<
87 /* <<
88 * underrun will cause readback of 0s, instead <<
89 */ <<
90 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1) <<
91 <<
92 /* the UUID size in bytes, shared between FW a <<
93 #define SOF_UUID_SIZE 16 <<
94 77
95 /* create new component buffer - SOF_IPC_TPLG_ 78 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
96 struct sof_ipc_buffer { 79 struct sof_ipc_buffer {
97 struct sof_ipc_comp comp; 80 struct sof_ipc_comp comp;
98 uint32_t size; /**< buffer si 81 uint32_t size; /**< buffer size in bytes */
99 uint32_t caps; /**< SOF_MEM_C 82 uint32_t caps; /**< SOF_MEM_CAPS_ */
100 uint32_t flags; /**< SOF_BUF_ !! 83 } __packed;
101 uint32_t reserved; /**< reserved <<
102 } __packed __aligned(4); <<
103 84
104 /* generic component config data - must always 85 /* generic component config data - must always be after struct sof_ipc_comp */
105 struct sof_ipc_comp_config { 86 struct sof_ipc_comp_config {
106 struct sof_ipc_cmd_hdr hdr; 87 struct sof_ipc_cmd_hdr hdr;
107 uint32_t periods_sink; /**< 0 means v 88 uint32_t periods_sink; /**< 0 means variable */
108 uint32_t periods_source;/**< 0 means v 89 uint32_t periods_source;/**< 0 means variable */
109 uint32_t reserved1; /**< reserved 90 uint32_t reserved1; /**< reserved */
110 uint32_t frame_fmt; /**< SOF_IPC_F 91 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
111 uint32_t xrun_action; 92 uint32_t xrun_action;
112 93
113 /* reserved for future use */ 94 /* reserved for future use */
114 uint32_t reserved[2]; 95 uint32_t reserved[2];
115 } __packed __aligned(4); !! 96 } __packed;
116 97
117 /* generic host component */ 98 /* generic host component */
118 struct sof_ipc_comp_host { 99 struct sof_ipc_comp_host {
119 struct sof_ipc_comp comp; 100 struct sof_ipc_comp comp;
120 struct sof_ipc_comp_config config; 101 struct sof_ipc_comp_config config;
121 uint32_t direction; /**< SOF_IPC_S 102 uint32_t direction; /**< SOF_IPC_STREAM_ */
122 uint32_t no_irq; /**< don't sen 103 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */
123 uint32_t dmac_config; /**< DMA engine 104 uint32_t dmac_config; /**< DMA engine specific */
124 } __packed __aligned(4); !! 105 } __packed;
125 106
126 /* generic DAI component */ 107 /* generic DAI component */
127 struct sof_ipc_comp_dai { 108 struct sof_ipc_comp_dai {
128 struct sof_ipc_comp comp; 109 struct sof_ipc_comp comp;
129 struct sof_ipc_comp_config config; 110 struct sof_ipc_comp_config config;
130 uint32_t direction; /**< SOF_IPC_S 111 uint32_t direction; /**< SOF_IPC_STREAM_ */
131 uint32_t dai_index; /**< index of 112 uint32_t dai_index; /**< index of this type dai */
132 uint32_t type; /**< DAI type 113 uint32_t type; /**< DAI type - SOF_DAI_ */
133 uint32_t reserved; /**< reserved 114 uint32_t reserved; /**< reserved */
134 } __packed __aligned(4); !! 115 } __packed;
135 116
136 /* generic mixer component */ 117 /* generic mixer component */
137 struct sof_ipc_comp_mixer { 118 struct sof_ipc_comp_mixer {
138 struct sof_ipc_comp comp; 119 struct sof_ipc_comp comp;
139 struct sof_ipc_comp_config config; 120 struct sof_ipc_comp_config config;
140 } __packed __aligned(4); !! 121 } __packed;
141 122
142 /* volume ramping types */ 123 /* volume ramping types */
143 enum sof_volume_ramp { 124 enum sof_volume_ramp {
144 SOF_VOLUME_LINEAR = 0, 125 SOF_VOLUME_LINEAR = 0,
145 SOF_VOLUME_LOG, 126 SOF_VOLUME_LOG,
146 SOF_VOLUME_LINEAR_ZC, 127 SOF_VOLUME_LINEAR_ZC,
147 SOF_VOLUME_LOG_ZC, 128 SOF_VOLUME_LOG_ZC,
148 SOF_VOLUME_WINDOWS_FADE, <<
149 SOF_VOLUME_WINDOWS_NO_FADE, <<
150 }; 129 };
151 130
152 /* generic volume component */ 131 /* generic volume component */
153 struct sof_ipc_comp_volume { 132 struct sof_ipc_comp_volume {
154 struct sof_ipc_comp comp; 133 struct sof_ipc_comp comp;
155 struct sof_ipc_comp_config config; 134 struct sof_ipc_comp_config config;
156 uint32_t channels; 135 uint32_t channels;
157 uint32_t min_value; 136 uint32_t min_value;
158 uint32_t max_value; 137 uint32_t max_value;
159 uint32_t ramp; /**< SOF_VOLUM 138 uint32_t ramp; /**< SOF_VOLUME_ */
160 uint32_t initial_ramp; /**< ramp spac 139 uint32_t initial_ramp; /**< ramp space in ms */
161 } __packed __aligned(4); !! 140 } __packed;
162 141
163 /* generic SRC component */ 142 /* generic SRC component */
164 struct sof_ipc_comp_src { 143 struct sof_ipc_comp_src {
165 struct sof_ipc_comp comp; 144 struct sof_ipc_comp comp;
166 struct sof_ipc_comp_config config; 145 struct sof_ipc_comp_config config;
167 /* either source or sink rate must be 146 /* either source or sink rate must be non zero */
168 uint32_t source_rate; /**< source ra 147 uint32_t source_rate; /**< source rate or 0 for variable */
169 uint32_t sink_rate; /**< sink rate 148 uint32_t sink_rate; /**< sink rate or 0 for variable */
170 uint32_t rate_mask; /**< SOF_RATE_ 149 uint32_t rate_mask; /**< SOF_RATE_ supported rates */
171 } __packed __aligned(4); !! 150 } __packed;
172 151
173 /* generic ASRC component */ 152 /* generic ASRC component */
174 struct sof_ipc_comp_asrc { 153 struct sof_ipc_comp_asrc {
175 struct sof_ipc_comp comp; 154 struct sof_ipc_comp comp;
176 struct sof_ipc_comp_config config; 155 struct sof_ipc_comp_config config;
177 /* either source or sink rate must be 156 /* either source or sink rate must be non zero */
178 uint32_t source_rate; /**< D 157 uint32_t source_rate; /**< Define fixed source rate or */
179 /**< u 158 /**< use 0 to indicate need to get */
180 /**< t 159 /**< the rate from stream */
181 uint32_t sink_rate; /**< D 160 uint32_t sink_rate; /**< Define fixed sink rate or */
182 /**< u 161 /**< use 0 to indicate need to get */
183 /**< t 162 /**< the rate from stream */
184 uint32_t asynchronous_mode; /**< s 163 uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */
185 /**< W 164 /**< When 1 the ASRC tracks and */
186 /**< c 165 /**< compensates for drift. */
187 uint32_t operation_mode; /**< p 166 uint32_t operation_mode; /**< push 0, pull 1, In push mode the */
188 /**< A 167 /**< ASRC consumes a defined number */
189 /**< o 168 /**< of frames at input, with varying */
190 /**< n 169 /**< number of frames at output. */
191 /**< I 170 /**< In pull mode the ASRC outputs */
192 /**< a 171 /**< a defined number of frames while */
193 /**< n 172 /**< number of input frames varies. */
194 173
195 /* reserved for future use */ 174 /* reserved for future use */
196 uint32_t reserved[4]; 175 uint32_t reserved[4];
197 } __packed __aligned(4); !! 176 } __attribute__((packed));
198 177
199 /* generic MUX component */ 178 /* generic MUX component */
200 struct sof_ipc_comp_mux { 179 struct sof_ipc_comp_mux {
201 struct sof_ipc_comp comp; 180 struct sof_ipc_comp comp;
202 struct sof_ipc_comp_config config; 181 struct sof_ipc_comp_config config;
203 } __packed __aligned(4); !! 182 } __packed;
204 183
205 /* generic tone generator component */ 184 /* generic tone generator component */
206 struct sof_ipc_comp_tone { 185 struct sof_ipc_comp_tone {
207 struct sof_ipc_comp comp; 186 struct sof_ipc_comp comp;
208 struct sof_ipc_comp_config config; 187 struct sof_ipc_comp_config config;
209 int32_t sample_rate; 188 int32_t sample_rate;
210 int32_t frequency; 189 int32_t frequency;
211 int32_t amplitude; 190 int32_t amplitude;
212 int32_t freq_mult; 191 int32_t freq_mult;
213 int32_t ampl_mult; 192 int32_t ampl_mult;
214 int32_t length; 193 int32_t length;
215 int32_t period; 194 int32_t period;
216 int32_t repeats; 195 int32_t repeats;
217 int32_t ramp_step; 196 int32_t ramp_step;
218 } __packed __aligned(4); !! 197 } __packed;
219 198
220 /** \brief Types of processing components */ 199 /** \brief Types of processing components */
221 enum sof_ipc_process_type { 200 enum sof_ipc_process_type {
222 SOF_PROCESS_NONE = 0, /**< N 201 SOF_PROCESS_NONE = 0, /**< None */
223 SOF_PROCESS_EQFIR, /**< I 202 SOF_PROCESS_EQFIR, /**< Intel FIR */
224 SOF_PROCESS_EQIIR, /**< I 203 SOF_PROCESS_EQIIR, /**< Intel IIR */
225 SOF_PROCESS_KEYWORD_DETECT, /**< K 204 SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
226 SOF_PROCESS_KPB, /**< K 205 SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */
227 SOF_PROCESS_CHAN_SELECTOR, /**< C 206 SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */
228 SOF_PROCESS_MUX, 207 SOF_PROCESS_MUX,
229 SOF_PROCESS_DEMUX, 208 SOF_PROCESS_DEMUX,
230 SOF_PROCESS_DCBLOCK, <<
231 SOF_PROCESS_SMART_AMP, /**< Smart Amp <<
232 }; 209 };
233 210
234 /* generic "effect", "codec" or proprietary pr 211 /* generic "effect", "codec" or proprietary processing component */
235 struct sof_ipc_comp_process { 212 struct sof_ipc_comp_process {
236 struct sof_ipc_comp comp; 213 struct sof_ipc_comp comp;
237 struct sof_ipc_comp_config config; 214 struct sof_ipc_comp_config config;
238 uint32_t size; /**< size of bespoke d 215 uint32_t size; /**< size of bespoke data section in bytes */
239 uint32_t type; /**< sof_ipc_process_t 216 uint32_t type; /**< sof_ipc_process_type */
240 217
241 /* reserved for future use */ 218 /* reserved for future use */
242 uint32_t reserved[7]; 219 uint32_t reserved[7];
243 220
244 unsigned char data[]; !! 221 unsigned char data[0];
245 } __packed __aligned(4); !! 222 } __packed;
246 223
247 /* frees components, buffers and pipelines 224 /* frees components, buffers and pipelines
248 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_F 225 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
249 */ 226 */
250 struct sof_ipc_free { 227 struct sof_ipc_free {
251 struct sof_ipc_cmd_hdr hdr; 228 struct sof_ipc_cmd_hdr hdr;
252 uint32_t id; 229 uint32_t id;
253 } __packed __aligned(4); !! 230 } __packed;
254 231
255 struct sof_ipc_comp_reply { 232 struct sof_ipc_comp_reply {
256 struct sof_ipc_reply rhdr; 233 struct sof_ipc_reply rhdr;
257 uint32_t id; 234 uint32_t id;
258 uint32_t offset; 235 uint32_t offset;
259 } __packed __aligned(4); !! 236 } __packed;
260 237
261 /* 238 /*
262 * Pipeline 239 * Pipeline
263 */ 240 */
264 241
265 /** \brief Types of pipeline scheduling time d 242 /** \brief Types of pipeline scheduling time domains */
266 enum sof_ipc_pipe_sched_time_domain { 243 enum sof_ipc_pipe_sched_time_domain {
267 SOF_TIME_DOMAIN_DMA = 0, /**< D 244 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */
268 SOF_TIME_DOMAIN_TIMER, /**< T 245 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */
269 }; 246 };
270 247
271 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ 248 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
272 struct sof_ipc_pipe_new { 249 struct sof_ipc_pipe_new {
273 struct sof_ipc_cmd_hdr hdr; 250 struct sof_ipc_cmd_hdr hdr;
274 uint32_t comp_id; /**< component 251 uint32_t comp_id; /**< component id for pipeline */
275 uint32_t pipeline_id; /**< pipeline 252 uint32_t pipeline_id; /**< pipeline id */
276 uint32_t sched_id; /**< Schedulin 253 uint32_t sched_id; /**< Scheduling component id */
277 uint32_t core; /**< core we r 254 uint32_t core; /**< core we run on */
278 uint32_t period; /**< execution 255 uint32_t period; /**< execution period in us*/
279 uint32_t priority; /**< priority 256 uint32_t priority; /**< priority level 0 (low) to 10 (max) */
280 uint32_t period_mips; /**< worst cas 257 uint32_t period_mips; /**< worst case instruction count per period */
281 uint32_t frames_per_sched;/**< output 258 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
282 uint32_t xrun_limit_usecs; /**< report 259 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
283 uint32_t time_domain; /**< schedulin 260 uint32_t time_domain; /**< scheduling time domain */
284 } __packed __aligned(4); !! 261 } __packed;
285 262
286 /* pipeline construction complete - SOF_IPC_TP 263 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
287 struct sof_ipc_pipe_ready { 264 struct sof_ipc_pipe_ready {
288 struct sof_ipc_cmd_hdr hdr; 265 struct sof_ipc_cmd_hdr hdr;
289 uint32_t comp_id; 266 uint32_t comp_id;
290 } __packed __aligned(4); !! 267 } __packed;
291 268
292 struct sof_ipc_pipe_free { 269 struct sof_ipc_pipe_free {
293 struct sof_ipc_cmd_hdr hdr; 270 struct sof_ipc_cmd_hdr hdr;
294 uint32_t comp_id; 271 uint32_t comp_id;
295 } __packed __aligned(4); !! 272 } __packed;
296 273
297 /* connect two components in pipeline - SOF_IP 274 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
298 struct sof_ipc_pipe_comp_connect { 275 struct sof_ipc_pipe_comp_connect {
299 struct sof_ipc_cmd_hdr hdr; 276 struct sof_ipc_cmd_hdr hdr;
300 uint32_t source_id; 277 uint32_t source_id;
301 uint32_t sink_id; 278 uint32_t sink_id;
302 } __packed __aligned(4); !! 279 } __packed;
303 280
304 /* external events */ 281 /* external events */
305 enum sof_event_types { 282 enum sof_event_types {
306 SOF_EVENT_NONE = 0, 283 SOF_EVENT_NONE = 0,
307 SOF_KEYWORD_DETECT_DAPM_EVENT, 284 SOF_KEYWORD_DETECT_DAPM_EVENT,
308 }; 285 };
309 286
310 #endif 287 #endif
311 288
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