1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* 2 /*
3 * This file is provided under a dual BSD/GPLv 3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so und 4 * redistributing this file, you may do so under either license.
5 * 5 *
6 * Copyright(c) 2018 Intel Corporation 6 * Copyright(c) 2018 Intel Corporation
7 */ 7 */
8 8
9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 9 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__ 10 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
11 11
12 #include <sound/sof/header.h> 12 #include <sound/sof/header.h>
13 13
14 /* 14 /*
15 * Component 15 * Component
16 */ 16 */
17 17
18 /* types of component */ 18 /* types of component */
19 enum sof_comp_type { 19 enum sof_comp_type {
20 SOF_COMP_NONE = 0, 20 SOF_COMP_NONE = 0,
21 SOF_COMP_HOST, 21 SOF_COMP_HOST,
22 SOF_COMP_DAI, 22 SOF_COMP_DAI,
23 SOF_COMP_SG_HOST, /**< scatter g 23 SOF_COMP_SG_HOST, /**< scatter gather variant */
24 SOF_COMP_SG_DAI, /**< scatter g 24 SOF_COMP_SG_DAI, /**< scatter gather variant */
25 SOF_COMP_VOLUME, 25 SOF_COMP_VOLUME,
26 SOF_COMP_MIXER, 26 SOF_COMP_MIXER,
27 SOF_COMP_MUX, 27 SOF_COMP_MUX,
28 SOF_COMP_SRC, 28 SOF_COMP_SRC,
29 SOF_COMP_DEPRECATED0, /* Formerly SOF_ 29 SOF_COMP_DEPRECATED0, /* Formerly SOF_COMP_SPLITTER */
30 SOF_COMP_TONE, 30 SOF_COMP_TONE,
31 SOF_COMP_DEPRECATED1, /* Formerly SOF_ 31 SOF_COMP_DEPRECATED1, /* Formerly SOF_COMP_SWITCH */
32 SOF_COMP_BUFFER, 32 SOF_COMP_BUFFER,
33 SOF_COMP_EQ_IIR, 33 SOF_COMP_EQ_IIR,
34 SOF_COMP_EQ_FIR, 34 SOF_COMP_EQ_FIR,
35 SOF_COMP_KEYWORD_DETECT, 35 SOF_COMP_KEYWORD_DETECT,
36 SOF_COMP_KPB, /* A k 36 SOF_COMP_KPB, /* A key phrase buffer component */
37 SOF_COMP_SELECTOR, /**< c 37 SOF_COMP_SELECTOR, /**< channel selector component */
38 SOF_COMP_DEMUX, 38 SOF_COMP_DEMUX,
39 SOF_COMP_ASRC, /**< Asynchron 39 SOF_COMP_ASRC, /**< Asynchronous sample rate converter */
40 SOF_COMP_DCBLOCK, 40 SOF_COMP_DCBLOCK,
41 SOF_COMP_SMART_AMP, /**< s 41 SOF_COMP_SMART_AMP, /**< smart amplifier component */
42 SOF_COMP_MODULE_ADAPTER, 42 SOF_COMP_MODULE_ADAPTER, /**< module adapter */
43 /* keep FILEREAD/FILEWRITE as the last 43 /* keep FILEREAD/FILEWRITE as the last ones */
44 SOF_COMP_FILEREAD = 10000, /**< h 44 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */
45 SOF_COMP_FILEWRITE = 10001, /**< h 45 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
46 }; 46 };
47 47
48 /* XRUN action for component */ 48 /* XRUN action for component */
49 #define SOF_XRUN_STOP 1 /**< s 49 #define SOF_XRUN_STOP 1 /**< stop stream */
50 #define SOF_XRUN_UNDER_ZERO 2 /**< s 50 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */
51 #define SOF_XRUN_OVER_NULL 4 /**< s 51 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */
52 52
53 /* create new generic component - SOF_IPC_TPLG 53 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
54 struct sof_ipc_comp { 54 struct sof_ipc_comp {
55 struct sof_ipc_cmd_hdr hdr; 55 struct sof_ipc_cmd_hdr hdr;
56 uint32_t id; 56 uint32_t id;
57 enum sof_comp_type type; 57 enum sof_comp_type type;
58 uint32_t pipeline_id; 58 uint32_t pipeline_id;
59 uint32_t core; 59 uint32_t core;
60 60
61 /* extended data length, 0 if no exten 61 /* extended data length, 0 if no extended data */
62 uint32_t ext_data_length; 62 uint32_t ext_data_length;
63 } __packed __aligned(4); 63 } __packed __aligned(4);
64 64
65 /* 65 /*
66 * Component Buffers 66 * Component Buffers
67 */ 67 */
68 68
69 /* 69 /*
70 * SOF memory capabilities, add new ones at th 70 * SOF memory capabilities, add new ones at the end
71 */ 71 */
72 #define SOF_MEM_CAPS_RAM BIT(0) 72 #define SOF_MEM_CAPS_RAM BIT(0)
73 #define SOF_MEM_CAPS_ROM BIT(1) 73 #define SOF_MEM_CAPS_ROM BIT(1)
74 #define SOF_MEM_CAPS_EXT BIT(2) 74 #define SOF_MEM_CAPS_EXT BIT(2) /**< external */
75 #define SOF_MEM_CAPS_LP BIT(3) 75 #define SOF_MEM_CAPS_LP BIT(3) /**< low power */
76 #define SOF_MEM_CAPS_HP BIT(4) 76 #define SOF_MEM_CAPS_HP BIT(4) /**< high performance */
77 #define SOF_MEM_CAPS_DMA BIT(5) 77 #define SOF_MEM_CAPS_DMA BIT(5) /**< DMA'able */
78 #define SOF_MEM_CAPS_CACHE BIT(6) 78 #define SOF_MEM_CAPS_CACHE BIT(6) /**< cacheable */
79 #define SOF_MEM_CAPS_EXEC BIT(7) 79 #define SOF_MEM_CAPS_EXEC BIT(7) /**< executable */
80 #define SOF_MEM_CAPS_L3 BIT(8) 80 #define SOF_MEM_CAPS_L3 BIT(8) /**< L3 memory */
81 81
82 /* 82 /*
83 * overrun will cause ring buffer overwrite, i 83 * overrun will cause ring buffer overwrite, instead of XRUN.
84 */ 84 */
85 #define SOF_BUF_OVERRUN_PERMITTED BIT(0) 85 #define SOF_BUF_OVERRUN_PERMITTED BIT(0)
86 86
87 /* 87 /*
88 * underrun will cause readback of 0s, instead 88 * underrun will cause readback of 0s, instead of XRUN.
89 */ 89 */
90 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1) 90 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1)
91 91
92 /* the UUID size in bytes, shared between FW a 92 /* the UUID size in bytes, shared between FW and host */
93 #define SOF_UUID_SIZE 16 93 #define SOF_UUID_SIZE 16
94 94
95 /* create new component buffer - SOF_IPC_TPLG_ 95 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
96 struct sof_ipc_buffer { 96 struct sof_ipc_buffer {
97 struct sof_ipc_comp comp; 97 struct sof_ipc_comp comp;
98 uint32_t size; /**< buffer si 98 uint32_t size; /**< buffer size in bytes */
99 uint32_t caps; /**< SOF_MEM_C 99 uint32_t caps; /**< SOF_MEM_CAPS_ */
100 uint32_t flags; /**< SOF_BUF_ 100 uint32_t flags; /**< SOF_BUF_ flags defined above */
101 uint32_t reserved; /**< reserved 101 uint32_t reserved; /**< reserved for future use */
102 } __packed __aligned(4); 102 } __packed __aligned(4);
103 103
104 /* generic component config data - must always 104 /* generic component config data - must always be after struct sof_ipc_comp */
105 struct sof_ipc_comp_config { 105 struct sof_ipc_comp_config {
106 struct sof_ipc_cmd_hdr hdr; 106 struct sof_ipc_cmd_hdr hdr;
107 uint32_t periods_sink; /**< 0 means v 107 uint32_t periods_sink; /**< 0 means variable */
108 uint32_t periods_source;/**< 0 means v 108 uint32_t periods_source;/**< 0 means variable */
109 uint32_t reserved1; /**< reserved 109 uint32_t reserved1; /**< reserved */
110 uint32_t frame_fmt; /**< SOF_IPC_F 110 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
111 uint32_t xrun_action; 111 uint32_t xrun_action;
112 112
113 /* reserved for future use */ 113 /* reserved for future use */
114 uint32_t reserved[2]; 114 uint32_t reserved[2];
115 } __packed __aligned(4); 115 } __packed __aligned(4);
116 116
117 /* generic host component */ 117 /* generic host component */
118 struct sof_ipc_comp_host { 118 struct sof_ipc_comp_host {
119 struct sof_ipc_comp comp; 119 struct sof_ipc_comp comp;
120 struct sof_ipc_comp_config config; 120 struct sof_ipc_comp_config config;
121 uint32_t direction; /**< SOF_IPC_S 121 uint32_t direction; /**< SOF_IPC_STREAM_ */
122 uint32_t no_irq; /**< don't sen 122 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */
123 uint32_t dmac_config; /**< DMA engine 123 uint32_t dmac_config; /**< DMA engine specific */
124 } __packed __aligned(4); 124 } __packed __aligned(4);
125 125
126 /* generic DAI component */ 126 /* generic DAI component */
127 struct sof_ipc_comp_dai { 127 struct sof_ipc_comp_dai {
128 struct sof_ipc_comp comp; 128 struct sof_ipc_comp comp;
129 struct sof_ipc_comp_config config; 129 struct sof_ipc_comp_config config;
130 uint32_t direction; /**< SOF_IPC_S 130 uint32_t direction; /**< SOF_IPC_STREAM_ */
131 uint32_t dai_index; /**< index of 131 uint32_t dai_index; /**< index of this type dai */
132 uint32_t type; /**< DAI type 132 uint32_t type; /**< DAI type - SOF_DAI_ */
133 uint32_t reserved; /**< reserved 133 uint32_t reserved; /**< reserved */
134 } __packed __aligned(4); 134 } __packed __aligned(4);
135 135
136 /* generic mixer component */ 136 /* generic mixer component */
137 struct sof_ipc_comp_mixer { 137 struct sof_ipc_comp_mixer {
138 struct sof_ipc_comp comp; 138 struct sof_ipc_comp comp;
139 struct sof_ipc_comp_config config; 139 struct sof_ipc_comp_config config;
140 } __packed __aligned(4); 140 } __packed __aligned(4);
141 141
142 /* volume ramping types */ 142 /* volume ramping types */
143 enum sof_volume_ramp { 143 enum sof_volume_ramp {
144 SOF_VOLUME_LINEAR = 0, 144 SOF_VOLUME_LINEAR = 0,
145 SOF_VOLUME_LOG, 145 SOF_VOLUME_LOG,
146 SOF_VOLUME_LINEAR_ZC, 146 SOF_VOLUME_LINEAR_ZC,
147 SOF_VOLUME_LOG_ZC, 147 SOF_VOLUME_LOG_ZC,
148 SOF_VOLUME_WINDOWS_FADE, 148 SOF_VOLUME_WINDOWS_FADE,
149 SOF_VOLUME_WINDOWS_NO_FADE, 149 SOF_VOLUME_WINDOWS_NO_FADE,
150 }; 150 };
151 151
152 /* generic volume component */ 152 /* generic volume component */
153 struct sof_ipc_comp_volume { 153 struct sof_ipc_comp_volume {
154 struct sof_ipc_comp comp; 154 struct sof_ipc_comp comp;
155 struct sof_ipc_comp_config config; 155 struct sof_ipc_comp_config config;
156 uint32_t channels; 156 uint32_t channels;
157 uint32_t min_value; 157 uint32_t min_value;
158 uint32_t max_value; 158 uint32_t max_value;
159 uint32_t ramp; /**< SOF_VOLUM 159 uint32_t ramp; /**< SOF_VOLUME_ */
160 uint32_t initial_ramp; /**< ramp spac 160 uint32_t initial_ramp; /**< ramp space in ms */
161 } __packed __aligned(4); 161 } __packed __aligned(4);
162 162
163 /* generic SRC component */ 163 /* generic SRC component */
164 struct sof_ipc_comp_src { 164 struct sof_ipc_comp_src {
165 struct sof_ipc_comp comp; 165 struct sof_ipc_comp comp;
166 struct sof_ipc_comp_config config; 166 struct sof_ipc_comp_config config;
167 /* either source or sink rate must be 167 /* either source or sink rate must be non zero */
168 uint32_t source_rate; /**< source ra 168 uint32_t source_rate; /**< source rate or 0 for variable */
169 uint32_t sink_rate; /**< sink rate 169 uint32_t sink_rate; /**< sink rate or 0 for variable */
170 uint32_t rate_mask; /**< SOF_RATE_ 170 uint32_t rate_mask; /**< SOF_RATE_ supported rates */
171 } __packed __aligned(4); 171 } __packed __aligned(4);
172 172
173 /* generic ASRC component */ 173 /* generic ASRC component */
174 struct sof_ipc_comp_asrc { 174 struct sof_ipc_comp_asrc {
175 struct sof_ipc_comp comp; 175 struct sof_ipc_comp comp;
176 struct sof_ipc_comp_config config; 176 struct sof_ipc_comp_config config;
177 /* either source or sink rate must be 177 /* either source or sink rate must be non zero */
178 uint32_t source_rate; /**< D 178 uint32_t source_rate; /**< Define fixed source rate or */
179 /**< u 179 /**< use 0 to indicate need to get */
180 /**< t 180 /**< the rate from stream */
181 uint32_t sink_rate; /**< D 181 uint32_t sink_rate; /**< Define fixed sink rate or */
182 /**< u 182 /**< use 0 to indicate need to get */
183 /**< t 183 /**< the rate from stream */
184 uint32_t asynchronous_mode; /**< s 184 uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */
185 /**< W 185 /**< When 1 the ASRC tracks and */
186 /**< c 186 /**< compensates for drift. */
187 uint32_t operation_mode; /**< p 187 uint32_t operation_mode; /**< push 0, pull 1, In push mode the */
188 /**< A 188 /**< ASRC consumes a defined number */
189 /**< o 189 /**< of frames at input, with varying */
190 /**< n 190 /**< number of frames at output. */
191 /**< I 191 /**< In pull mode the ASRC outputs */
192 /**< a 192 /**< a defined number of frames while */
193 /**< n 193 /**< number of input frames varies. */
194 194
195 /* reserved for future use */ 195 /* reserved for future use */
196 uint32_t reserved[4]; 196 uint32_t reserved[4];
197 } __packed __aligned(4); 197 } __packed __aligned(4);
198 198
199 /* generic MUX component */ 199 /* generic MUX component */
200 struct sof_ipc_comp_mux { 200 struct sof_ipc_comp_mux {
201 struct sof_ipc_comp comp; 201 struct sof_ipc_comp comp;
202 struct sof_ipc_comp_config config; 202 struct sof_ipc_comp_config config;
203 } __packed __aligned(4); 203 } __packed __aligned(4);
204 204
205 /* generic tone generator component */ 205 /* generic tone generator component */
206 struct sof_ipc_comp_tone { 206 struct sof_ipc_comp_tone {
207 struct sof_ipc_comp comp; 207 struct sof_ipc_comp comp;
208 struct sof_ipc_comp_config config; 208 struct sof_ipc_comp_config config;
209 int32_t sample_rate; 209 int32_t sample_rate;
210 int32_t frequency; 210 int32_t frequency;
211 int32_t amplitude; 211 int32_t amplitude;
212 int32_t freq_mult; 212 int32_t freq_mult;
213 int32_t ampl_mult; 213 int32_t ampl_mult;
214 int32_t length; 214 int32_t length;
215 int32_t period; 215 int32_t period;
216 int32_t repeats; 216 int32_t repeats;
217 int32_t ramp_step; 217 int32_t ramp_step;
218 } __packed __aligned(4); 218 } __packed __aligned(4);
219 219
220 /** \brief Types of processing components */ 220 /** \brief Types of processing components */
221 enum sof_ipc_process_type { 221 enum sof_ipc_process_type {
222 SOF_PROCESS_NONE = 0, /**< N 222 SOF_PROCESS_NONE = 0, /**< None */
223 SOF_PROCESS_EQFIR, /**< I 223 SOF_PROCESS_EQFIR, /**< Intel FIR */
224 SOF_PROCESS_EQIIR, /**< I 224 SOF_PROCESS_EQIIR, /**< Intel IIR */
225 SOF_PROCESS_KEYWORD_DETECT, /**< K 225 SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
226 SOF_PROCESS_KPB, /**< K 226 SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */
227 SOF_PROCESS_CHAN_SELECTOR, /**< C 227 SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */
228 SOF_PROCESS_MUX, 228 SOF_PROCESS_MUX,
229 SOF_PROCESS_DEMUX, 229 SOF_PROCESS_DEMUX,
230 SOF_PROCESS_DCBLOCK, 230 SOF_PROCESS_DCBLOCK,
231 SOF_PROCESS_SMART_AMP, /**< Smart Amp 231 SOF_PROCESS_SMART_AMP, /**< Smart Amplifier */
232 }; 232 };
233 233
234 /* generic "effect", "codec" or proprietary pr 234 /* generic "effect", "codec" or proprietary processing component */
235 struct sof_ipc_comp_process { 235 struct sof_ipc_comp_process {
236 struct sof_ipc_comp comp; 236 struct sof_ipc_comp comp;
237 struct sof_ipc_comp_config config; 237 struct sof_ipc_comp_config config;
238 uint32_t size; /**< size of bespoke d 238 uint32_t size; /**< size of bespoke data section in bytes */
239 uint32_t type; /**< sof_ipc_process_t 239 uint32_t type; /**< sof_ipc_process_type */
240 240
241 /* reserved for future use */ 241 /* reserved for future use */
242 uint32_t reserved[7]; 242 uint32_t reserved[7];
243 243
244 unsigned char data[]; 244 unsigned char data[];
245 } __packed __aligned(4); 245 } __packed __aligned(4);
246 246
247 /* frees components, buffers and pipelines 247 /* frees components, buffers and pipelines
248 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_F 248 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
249 */ 249 */
250 struct sof_ipc_free { 250 struct sof_ipc_free {
251 struct sof_ipc_cmd_hdr hdr; 251 struct sof_ipc_cmd_hdr hdr;
252 uint32_t id; 252 uint32_t id;
253 } __packed __aligned(4); 253 } __packed __aligned(4);
254 254
255 struct sof_ipc_comp_reply { 255 struct sof_ipc_comp_reply {
256 struct sof_ipc_reply rhdr; 256 struct sof_ipc_reply rhdr;
257 uint32_t id; 257 uint32_t id;
258 uint32_t offset; 258 uint32_t offset;
259 } __packed __aligned(4); 259 } __packed __aligned(4);
260 260
261 /* 261 /*
262 * Pipeline 262 * Pipeline
263 */ 263 */
264 264
265 /** \brief Types of pipeline scheduling time d 265 /** \brief Types of pipeline scheduling time domains */
266 enum sof_ipc_pipe_sched_time_domain { 266 enum sof_ipc_pipe_sched_time_domain {
267 SOF_TIME_DOMAIN_DMA = 0, /**< D 267 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */
268 SOF_TIME_DOMAIN_TIMER, /**< T 268 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */
269 }; 269 };
270 270
271 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ 271 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
272 struct sof_ipc_pipe_new { 272 struct sof_ipc_pipe_new {
273 struct sof_ipc_cmd_hdr hdr; 273 struct sof_ipc_cmd_hdr hdr;
274 uint32_t comp_id; /**< component 274 uint32_t comp_id; /**< component id for pipeline */
275 uint32_t pipeline_id; /**< pipeline 275 uint32_t pipeline_id; /**< pipeline id */
276 uint32_t sched_id; /**< Schedulin 276 uint32_t sched_id; /**< Scheduling component id */
277 uint32_t core; /**< core we r 277 uint32_t core; /**< core we run on */
278 uint32_t period; /**< execution 278 uint32_t period; /**< execution period in us*/
279 uint32_t priority; /**< priority 279 uint32_t priority; /**< priority level 0 (low) to 10 (max) */
280 uint32_t period_mips; /**< worst cas 280 uint32_t period_mips; /**< worst case instruction count per period */
281 uint32_t frames_per_sched;/**< output 281 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
282 uint32_t xrun_limit_usecs; /**< report 282 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
283 uint32_t time_domain; /**< schedulin 283 uint32_t time_domain; /**< scheduling time domain */
284 } __packed __aligned(4); 284 } __packed __aligned(4);
285 285
286 /* pipeline construction complete - SOF_IPC_TP 286 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
287 struct sof_ipc_pipe_ready { 287 struct sof_ipc_pipe_ready {
288 struct sof_ipc_cmd_hdr hdr; 288 struct sof_ipc_cmd_hdr hdr;
289 uint32_t comp_id; 289 uint32_t comp_id;
290 } __packed __aligned(4); 290 } __packed __aligned(4);
291 291
292 struct sof_ipc_pipe_free { 292 struct sof_ipc_pipe_free {
293 struct sof_ipc_cmd_hdr hdr; 293 struct sof_ipc_cmd_hdr hdr;
294 uint32_t comp_id; 294 uint32_t comp_id;
295 } __packed __aligned(4); 295 } __packed __aligned(4);
296 296
297 /* connect two components in pipeline - SOF_IP 297 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
298 struct sof_ipc_pipe_comp_connect { 298 struct sof_ipc_pipe_comp_connect {
299 struct sof_ipc_cmd_hdr hdr; 299 struct sof_ipc_cmd_hdr hdr;
300 uint32_t source_id; 300 uint32_t source_id;
301 uint32_t sink_id; 301 uint32_t sink_id;
302 } __packed __aligned(4); 302 } __packed __aligned(4);
303 303
304 /* external events */ 304 /* external events */
305 enum sof_event_types { 305 enum sof_event_types {
306 SOF_EVENT_NONE = 0, 306 SOF_EVENT_NONE = 0,
307 SOF_KEYWORD_DETECT_DAPM_EVENT, 307 SOF_KEYWORD_DETECT_DAPM_EVENT,
308 }; 308 };
309 309
310 #endif 310 #endif
311 311
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